1291406Sjhb/* SPDX-License-Identifier: GPL-2.0 */ 2291406Sjhb/* 3291406Sjhb * Copyright(c) 2019 Intel Corporation. 4291406Sjhb */ 5291406Sjhb 6291406Sjhb#ifndef __PINCTRL_EQUILIBRIUM_H 7291406Sjhb#define __PINCTRL_EQUILIBRIUM_H 8291406Sjhb 9291406Sjhb/* PINPAD register offset */ 10291406Sjhb#define REG_PMX_BASE 0x0 /* Port Multiplexer Control Register */ 11291406Sjhb#define REG_PUEN 0x80 /* PULL UP Enable Register */ 12291406Sjhb#define REG_PDEN 0x84 /* PULL DOWN Enable Register */ 13291406Sjhb#define REG_SRC 0x88 /* Slew Rate Control Register */ 14291406Sjhb#define REG_DCC0 0x8C /* Drive Current Control Register 0 */ 15291406Sjhb#define REG_DCC1 0x90 /* Drive Current Control Register 1 */ 16291406Sjhb#define REG_OD 0x94 /* Open Drain Enable Register */ 17291406Sjhb#define REG_AVAIL 0x98 /* Pad Control Availability Register */ 18291406Sjhb#define DRV_CUR_PINS 16 /* Drive Current pin number per register */ 19291406Sjhb#define REG_DRCC(x) (REG_DCC0 + (x) * 4) /* Driver current macro */ 20291406Sjhb 21291406Sjhb/* GPIO register offset */ 22291406Sjhb#define GPIO_OUT 0x0 /* Data Output Register */ 23291406Sjhb#define GPIO_IN 0x4 /* Data Input Register */ 24291406Sjhb#define GPIO_DIR 0x8 /* Direction Register */ 25291406Sjhb#define GPIO_EXINTCR0 0x18 /* External Interrupt Control Register 0 */ 26291406Sjhb#define GPIO_EXINTCR1 0x1C /* External Interrupt Control Register 1 */ 27291406Sjhb#define GPIO_IRNCR 0x20 /* IRN Capture Register */ 28291406Sjhb#define GPIO_IRNICR 0x24 /* IRN Interrupt Control Register */ 29291406Sjhb#define GPIO_IRNEN 0x28 /* IRN Interrupt Enable Register */ 30291406Sjhb#define GPIO_IRNCFG 0x2C /* IRN Interrupt Configuration Register */ 31291406Sjhb#define GPIO_IRNRNSET 0x30 /* IRN Interrupt Enable Set Register */ 32291406Sjhb#define GPIO_IRNENCLR 0x34 /* IRN Interrupt Enable Clear Register */ 33291406Sjhb#define GPIO_OUTSET 0x40 /* Output Set Register */ 34291406Sjhb#define GPIO_OUTCLR 0x44 /* Output Clear Register */ 35291406Sjhb#define GPIO_DIRSET 0x48 /* Direction Set Register */ 36291406Sjhb#define GPIO_DIRCLR 0x4C /* Direction Clear Register */ 37291406Sjhb 38291406Sjhb/* parse given pin's driver current value */ 39291406Sjhb#define PARSE_DRV_CURRENT(val, pin) (((val) >> ((pin) * 2)) & 0x3) 40291406Sjhb 41291406Sjhb#define GPIO_EDGE_TRIG 0 42291406Sjhb#define GPIO_LEVEL_TRIG 1 43291406Sjhb#define GPIO_SINGLE_EDGE 0 44291406Sjhb#define GPIO_BOTH_EDGE 1 45291406Sjhb#define GPIO_POSITIVE_TRIG 0 46291406Sjhb#define GPIO_NEGATIVE_TRIG 1 47291406Sjhb 48291406Sjhb#define EQBR_GPIO_MODE 0 49291406Sjhb 50291406Sjhbtypedef enum { 51291406Sjhb OP_COUNT_NR_FUNCS, 52291406Sjhb OP_ADD_FUNCS, 53291406Sjhb OP_COUNT_NR_FUNC_GRPS, 54291406Sjhb OP_ADD_FUNC_GRPS, 55291406Sjhb OP_NONE, 56291406Sjhb} funcs_util_ops; 57291406Sjhb 58291406Sjhb/** 59291406Sjhb * struct gpio_irq_type: gpio irq configuration 60291406Sjhb * @trig_type: level trigger or edge trigger 61 * @edge_type: sigle edge or both edge 62 * @logic_type: positive trigger or negative trigger 63 */ 64struct gpio_irq_type { 65 unsigned int trig_type; 66 unsigned int edge_type; 67 unsigned int logic_type; 68}; 69 70/** 71 * struct eqbr_pmx_func: represent a pin function. 72 * @name: name of the pin function, used to lookup the function. 73 * @groups: one or more names of pin groups that provide this function. 74 * @nr_groups: number of groups included in @groups. 75 */ 76struct eqbr_pmx_func { 77 const char *name; 78 const char **groups; 79 unsigned int nr_groups; 80}; 81 82/** 83 * struct eqbr_pin_bank: represent a pin bank. 84 * @membase: base address of the pin bank register. 85 * @id: bank id, to idenify the unique bank. 86 * @pin_base: starting pin number of the pin bank. 87 * @nr_pins: number of the pins of the pin bank. 88 * @aval_pinmap: available pin bitmap of the pin bank. 89 */ 90struct eqbr_pin_bank { 91 void __iomem *membase; 92 unsigned int id; 93 unsigned int pin_base; 94 unsigned int nr_pins; 95 u32 aval_pinmap; 96}; 97 98struct fwnode_handle; 99 100/** 101 * struct eqbr_gpio_ctrl: represent a gpio controller. 102 * @chip: gpio chip. 103 * @fwnode: firmware node of gpio controller. 104 * @bank: pointer to corresponding pin bank. 105 * @membase: base address of the gpio controller. 106 * @name: gpio chip name. 107 * @virq: irq number of the gpio chip to parent's irq domain. 108 * @lock: spin lock to protect gpio register write. 109 */ 110struct eqbr_gpio_ctrl { 111 struct gpio_chip chip; 112 struct fwnode_handle *fwnode; 113 struct eqbr_pin_bank *bank; 114 void __iomem *membase; 115 const char *name; 116 unsigned int virq; 117 raw_spinlock_t lock; /* protect gpio register */ 118}; 119 120/** 121 * struct eqbr_pinctrl_drv_data: 122 * @dev: device instance representing the controller. 123 * @pctl_desc: pin controller descriptor. 124 * @pctl_dev: pin control class device 125 * @membase: base address of pin controller 126 * @pin_banks: list of pin banks of the driver. 127 * @nr_banks: number of pin banks. 128 * @gpio_ctrls: list of gpio controllers. 129 * @nr_gpio_ctrls: number of gpio controllers. 130 * @lock: protect pinctrl register write 131 */ 132struct eqbr_pinctrl_drv_data { 133 struct device *dev; 134 struct pinctrl_desc pctl_desc; 135 struct pinctrl_dev *pctl_dev; 136 void __iomem *membase; 137 struct eqbr_pin_bank *pin_banks; 138 unsigned int nr_banks; 139 struct eqbr_gpio_ctrl *gpio_ctrls; 140 unsigned int nr_gpio_ctrls; 141 raw_spinlock_t lock; /* protect pinpad register */ 142}; 143 144#endif /* __PINCTRL_EQUILIBRIUM_H */ 145