1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Based on meson_uart.c, by AMLOGIC, INC. 4 * 5 * Copyright (C) 2014 Carlo Caione <carlo@caione.org> 6 */ 7 8#include <linux/clk.h> 9#include <linux/console.h> 10#include <linux/delay.h> 11#include <linux/init.h> 12#include <linux/io.h> 13#include <linux/iopoll.h> 14#include <linux/module.h> 15#include <linux/kernel.h> 16#include <linux/of.h> 17#include <linux/platform_device.h> 18#include <linux/serial.h> 19#include <linux/serial_core.h> 20#include <linux/tty.h> 21#include <linux/tty_flip.h> 22 23/* Register offsets */ 24#define AML_UART_WFIFO 0x00 25#define AML_UART_RFIFO 0x04 26#define AML_UART_CONTROL 0x08 27#define AML_UART_STATUS 0x0c 28#define AML_UART_MISC 0x10 29#define AML_UART_REG5 0x14 30 31/* AML_UART_CONTROL bits */ 32#define AML_UART_TX_EN BIT(12) 33#define AML_UART_RX_EN BIT(13) 34#define AML_UART_TWO_WIRE_EN BIT(15) 35#define AML_UART_STOP_BIT_LEN_MASK (0x03 << 16) 36#define AML_UART_STOP_BIT_1SB (0x00 << 16) 37#define AML_UART_STOP_BIT_2SB (0x01 << 16) 38#define AML_UART_PARITY_TYPE BIT(18) 39#define AML_UART_PARITY_EN BIT(19) 40#define AML_UART_TX_RST BIT(22) 41#define AML_UART_RX_RST BIT(23) 42#define AML_UART_CLEAR_ERR BIT(24) 43#define AML_UART_RX_INT_EN BIT(27) 44#define AML_UART_TX_INT_EN BIT(28) 45#define AML_UART_DATA_LEN_MASK (0x03 << 20) 46#define AML_UART_DATA_LEN_8BIT (0x00 << 20) 47#define AML_UART_DATA_LEN_7BIT (0x01 << 20) 48#define AML_UART_DATA_LEN_6BIT (0x02 << 20) 49#define AML_UART_DATA_LEN_5BIT (0x03 << 20) 50 51/* AML_UART_STATUS bits */ 52#define AML_UART_PARITY_ERR BIT(16) 53#define AML_UART_FRAME_ERR BIT(17) 54#define AML_UART_TX_FIFO_WERR BIT(18) 55#define AML_UART_RX_EMPTY BIT(20) 56#define AML_UART_TX_FULL BIT(21) 57#define AML_UART_TX_EMPTY BIT(22) 58#define AML_UART_XMIT_BUSY BIT(25) 59#define AML_UART_ERR (AML_UART_PARITY_ERR | \ 60 AML_UART_FRAME_ERR | \ 61 AML_UART_TX_FIFO_WERR) 62 63/* AML_UART_MISC bits */ 64#define AML_UART_XMIT_IRQ(c) (((c) & 0xff) << 8) 65#define AML_UART_RECV_IRQ(c) ((c) & 0xff) 66 67/* AML_UART_REG5 bits */ 68#define AML_UART_BAUD_MASK 0x7fffff 69#define AML_UART_BAUD_USE BIT(23) 70#define AML_UART_BAUD_XTAL BIT(24) 71#define AML_UART_BAUD_XTAL_DIV2 BIT(27) 72 73#define AML_UART_PORT_NUM 12 74#define AML_UART_PORT_OFFSET 6 75 76#define AML_UART_POLL_USEC 5 77#define AML_UART_TIMEOUT_USEC 10000 78 79static struct uart_driver meson_uart_driver_ttyAML; 80static struct uart_driver meson_uart_driver_ttyS; 81 82static struct uart_port *meson_ports[AML_UART_PORT_NUM]; 83 84struct meson_uart_data { 85 struct uart_driver *uart_driver; 86 bool has_xtal_div2; 87}; 88 89static void meson_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) 90{ 91} 92 93static unsigned int meson_uart_get_mctrl(struct uart_port *port) 94{ 95 return TIOCM_CTS; 96} 97 98static unsigned int meson_uart_tx_empty(struct uart_port *port) 99{ 100 u32 val; 101 102 val = readl(port->membase + AML_UART_STATUS); 103 val &= (AML_UART_TX_EMPTY | AML_UART_XMIT_BUSY); 104 return (val == AML_UART_TX_EMPTY) ? TIOCSER_TEMT : 0; 105} 106 107static void meson_uart_stop_tx(struct uart_port *port) 108{ 109 u32 val; 110 111 val = readl(port->membase + AML_UART_CONTROL); 112 val &= ~AML_UART_TX_INT_EN; 113 writel(val, port->membase + AML_UART_CONTROL); 114} 115 116static void meson_uart_stop_rx(struct uart_port *port) 117{ 118 u32 val; 119 120 val = readl(port->membase + AML_UART_CONTROL); 121 val &= ~AML_UART_RX_EN; 122 writel(val, port->membase + AML_UART_CONTROL); 123} 124 125static void meson_uart_shutdown(struct uart_port *port) 126{ 127 unsigned long flags; 128 u32 val; 129 130 free_irq(port->irq, port); 131 132 uart_port_lock_irqsave(port, &flags); 133 134 val = readl(port->membase + AML_UART_CONTROL); 135 val &= ~AML_UART_RX_EN; 136 val &= ~(AML_UART_RX_INT_EN | AML_UART_TX_INT_EN); 137 writel(val, port->membase + AML_UART_CONTROL); 138 139 uart_port_unlock_irqrestore(port, flags); 140} 141 142static void meson_uart_start_tx(struct uart_port *port) 143{ 144 struct circ_buf *xmit = &port->state->xmit; 145 unsigned int ch; 146 u32 val; 147 148 if (uart_tx_stopped(port)) { 149 meson_uart_stop_tx(port); 150 return; 151 } 152 153 while (!(readl(port->membase + AML_UART_STATUS) & AML_UART_TX_FULL)) { 154 if (port->x_char) { 155 writel(port->x_char, port->membase + AML_UART_WFIFO); 156 port->icount.tx++; 157 port->x_char = 0; 158 continue; 159 } 160 161 if (uart_circ_empty(xmit)) 162 break; 163 164 ch = xmit->buf[xmit->tail]; 165 writel(ch, port->membase + AML_UART_WFIFO); 166 uart_xmit_advance(port, 1); 167 } 168 169 if (!uart_circ_empty(xmit)) { 170 val = readl(port->membase + AML_UART_CONTROL); 171 val |= AML_UART_TX_INT_EN; 172 writel(val, port->membase + AML_UART_CONTROL); 173 } 174 175 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 176 uart_write_wakeup(port); 177} 178 179static void meson_receive_chars(struct uart_port *port) 180{ 181 struct tty_port *tport = &port->state->port; 182 char flag; 183 u32 ostatus, status, ch, mode; 184 185 do { 186 flag = TTY_NORMAL; 187 port->icount.rx++; 188 ostatus = status = readl(port->membase + AML_UART_STATUS); 189 190 if (status & AML_UART_ERR) { 191 if (status & AML_UART_TX_FIFO_WERR) 192 port->icount.overrun++; 193 else if (status & AML_UART_FRAME_ERR) 194 port->icount.frame++; 195 else if (status & AML_UART_PARITY_ERR) 196 port->icount.frame++; 197 198 mode = readl(port->membase + AML_UART_CONTROL); 199 mode |= AML_UART_CLEAR_ERR; 200 writel(mode, port->membase + AML_UART_CONTROL); 201 202 /* It doesn't clear to 0 automatically */ 203 mode &= ~AML_UART_CLEAR_ERR; 204 writel(mode, port->membase + AML_UART_CONTROL); 205 206 status &= port->read_status_mask; 207 if (status & AML_UART_FRAME_ERR) 208 flag = TTY_FRAME; 209 else if (status & AML_UART_PARITY_ERR) 210 flag = TTY_PARITY; 211 } 212 213 ch = readl(port->membase + AML_UART_RFIFO); 214 ch &= 0xff; 215 216 if ((ostatus & AML_UART_FRAME_ERR) && (ch == 0)) { 217 port->icount.brk++; 218 flag = TTY_BREAK; 219 if (uart_handle_break(port)) 220 continue; 221 } 222 223 if (uart_prepare_sysrq_char(port, ch)) 224 continue; 225 226 if ((status & port->ignore_status_mask) == 0) 227 tty_insert_flip_char(tport, ch, flag); 228 229 if (status & AML_UART_TX_FIFO_WERR) 230 tty_insert_flip_char(tport, 0, TTY_OVERRUN); 231 232 } while (!(readl(port->membase + AML_UART_STATUS) & AML_UART_RX_EMPTY)); 233 234 tty_flip_buffer_push(tport); 235} 236 237static irqreturn_t meson_uart_interrupt(int irq, void *dev_id) 238{ 239 struct uart_port *port = (struct uart_port *)dev_id; 240 241 uart_port_lock(port); 242 243 if (!(readl(port->membase + AML_UART_STATUS) & AML_UART_RX_EMPTY)) 244 meson_receive_chars(port); 245 246 if (!(readl(port->membase + AML_UART_STATUS) & AML_UART_TX_FULL)) { 247 if (readl(port->membase + AML_UART_CONTROL) & AML_UART_TX_INT_EN) 248 meson_uart_start_tx(port); 249 } 250 251 uart_unlock_and_check_sysrq(port); 252 253 return IRQ_HANDLED; 254} 255 256static const char *meson_uart_type(struct uart_port *port) 257{ 258 return (port->type == PORT_MESON) ? "meson_uart" : NULL; 259} 260 261/* 262 * This function is called only from probe() using a temporary io mapping 263 * in order to perform a reset before setting up the device. Since the 264 * temporarily mapped region was successfully requested, there can be no 265 * console on this port at this time. Hence it is not necessary for this 266 * function to acquire the port->lock. (Since there is no console on this 267 * port at this time, the port->lock is not initialized yet.) 268 */ 269static void meson_uart_reset(struct uart_port *port) 270{ 271 u32 val; 272 273 val = readl(port->membase + AML_UART_CONTROL); 274 val |= (AML_UART_RX_RST | AML_UART_TX_RST | AML_UART_CLEAR_ERR); 275 writel(val, port->membase + AML_UART_CONTROL); 276 277 val &= ~(AML_UART_RX_RST | AML_UART_TX_RST | AML_UART_CLEAR_ERR); 278 writel(val, port->membase + AML_UART_CONTROL); 279} 280 281static int meson_uart_startup(struct uart_port *port) 282{ 283 unsigned long flags; 284 u32 val; 285 int ret = 0; 286 287 uart_port_lock_irqsave(port, &flags); 288 289 val = readl(port->membase + AML_UART_CONTROL); 290 val |= AML_UART_CLEAR_ERR; 291 writel(val, port->membase + AML_UART_CONTROL); 292 val &= ~AML_UART_CLEAR_ERR; 293 writel(val, port->membase + AML_UART_CONTROL); 294 295 val |= (AML_UART_RX_EN | AML_UART_TX_EN); 296 writel(val, port->membase + AML_UART_CONTROL); 297 298 val |= (AML_UART_RX_INT_EN | AML_UART_TX_INT_EN); 299 writel(val, port->membase + AML_UART_CONTROL); 300 301 val = (AML_UART_RECV_IRQ(1) | AML_UART_XMIT_IRQ(port->fifosize / 2)); 302 writel(val, port->membase + AML_UART_MISC); 303 304 uart_port_unlock_irqrestore(port, flags); 305 306 ret = request_irq(port->irq, meson_uart_interrupt, 0, 307 port->name, port); 308 309 return ret; 310} 311 312static void meson_uart_change_speed(struct uart_port *port, unsigned long baud) 313{ 314 const struct meson_uart_data *private_data = port->private_data; 315 u32 val = 0; 316 317 while (!meson_uart_tx_empty(port)) 318 cpu_relax(); 319 320 if (port->uartclk == 24000000) { 321 unsigned int xtal_div = 3; 322 323 if (private_data && private_data->has_xtal_div2) { 324 xtal_div = 2; 325 val |= AML_UART_BAUD_XTAL_DIV2; 326 } 327 val |= DIV_ROUND_CLOSEST(port->uartclk / xtal_div, baud) - 1; 328 val |= AML_UART_BAUD_XTAL; 329 } else { 330 val = DIV_ROUND_CLOSEST(port->uartclk / 4, baud) - 1; 331 } 332 val |= AML_UART_BAUD_USE; 333 writel(val, port->membase + AML_UART_REG5); 334} 335 336static void meson_uart_set_termios(struct uart_port *port, 337 struct ktermios *termios, 338 const struct ktermios *old) 339{ 340 unsigned int cflags, iflags, baud; 341 unsigned long flags; 342 u32 val; 343 344 uart_port_lock_irqsave(port, &flags); 345 346 cflags = termios->c_cflag; 347 iflags = termios->c_iflag; 348 349 val = readl(port->membase + AML_UART_CONTROL); 350 351 val &= ~AML_UART_DATA_LEN_MASK; 352 switch (cflags & CSIZE) { 353 case CS8: 354 val |= AML_UART_DATA_LEN_8BIT; 355 break; 356 case CS7: 357 val |= AML_UART_DATA_LEN_7BIT; 358 break; 359 case CS6: 360 val |= AML_UART_DATA_LEN_6BIT; 361 break; 362 case CS5: 363 val |= AML_UART_DATA_LEN_5BIT; 364 break; 365 } 366 367 if (cflags & PARENB) 368 val |= AML_UART_PARITY_EN; 369 else 370 val &= ~AML_UART_PARITY_EN; 371 372 if (cflags & PARODD) 373 val |= AML_UART_PARITY_TYPE; 374 else 375 val &= ~AML_UART_PARITY_TYPE; 376 377 val &= ~AML_UART_STOP_BIT_LEN_MASK; 378 if (cflags & CSTOPB) 379 val |= AML_UART_STOP_BIT_2SB; 380 else 381 val |= AML_UART_STOP_BIT_1SB; 382 383 if (cflags & CRTSCTS) { 384 if (port->flags & UPF_HARD_FLOW) 385 val &= ~AML_UART_TWO_WIRE_EN; 386 else 387 termios->c_cflag &= ~CRTSCTS; 388 } else { 389 val |= AML_UART_TWO_WIRE_EN; 390 } 391 392 writel(val, port->membase + AML_UART_CONTROL); 393 394 baud = uart_get_baud_rate(port, termios, old, 50, 4000000); 395 meson_uart_change_speed(port, baud); 396 397 port->read_status_mask = AML_UART_TX_FIFO_WERR; 398 if (iflags & INPCK) 399 port->read_status_mask |= AML_UART_PARITY_ERR | 400 AML_UART_FRAME_ERR; 401 402 port->ignore_status_mask = 0; 403 if (iflags & IGNPAR) 404 port->ignore_status_mask |= AML_UART_PARITY_ERR | 405 AML_UART_FRAME_ERR; 406 407 uart_update_timeout(port, termios->c_cflag, baud); 408 uart_port_unlock_irqrestore(port, flags); 409} 410 411static int meson_uart_verify_port(struct uart_port *port, 412 struct serial_struct *ser) 413{ 414 int ret = 0; 415 416 if (port->type != PORT_MESON) 417 ret = -EINVAL; 418 if (port->irq != ser->irq) 419 ret = -EINVAL; 420 if (ser->baud_base < 9600) 421 ret = -EINVAL; 422 return ret; 423} 424 425static void meson_uart_release_port(struct uart_port *port) 426{ 427 devm_iounmap(port->dev, port->membase); 428 port->membase = NULL; 429 devm_release_mem_region(port->dev, port->mapbase, port->mapsize); 430} 431 432static int meson_uart_request_port(struct uart_port *port) 433{ 434 if (!devm_request_mem_region(port->dev, port->mapbase, port->mapsize, 435 dev_name(port->dev))) { 436 dev_err(port->dev, "Memory region busy\n"); 437 return -EBUSY; 438 } 439 440 port->membase = devm_ioremap(port->dev, port->mapbase, 441 port->mapsize); 442 if (!port->membase) 443 return -ENOMEM; 444 445 return 0; 446} 447 448static void meson_uart_config_port(struct uart_port *port, int flags) 449{ 450 if (flags & UART_CONFIG_TYPE) { 451 port->type = PORT_MESON; 452 meson_uart_request_port(port); 453 } 454} 455 456#ifdef CONFIG_CONSOLE_POLL 457/* 458 * Console polling routines for writing and reading from the uart while 459 * in an interrupt or debug context (i.e. kgdb). 460 */ 461 462static int meson_uart_poll_get_char(struct uart_port *port) 463{ 464 u32 c; 465 unsigned long flags; 466 467 uart_port_lock_irqsave(port, &flags); 468 469 if (readl(port->membase + AML_UART_STATUS) & AML_UART_RX_EMPTY) 470 c = NO_POLL_CHAR; 471 else 472 c = readl(port->membase + AML_UART_RFIFO); 473 474 uart_port_unlock_irqrestore(port, flags); 475 476 return c; 477} 478 479static void meson_uart_poll_put_char(struct uart_port *port, unsigned char c) 480{ 481 unsigned long flags; 482 u32 reg; 483 int ret; 484 485 uart_port_lock_irqsave(port, &flags); 486 487 /* Wait until FIFO is empty or timeout */ 488 ret = readl_poll_timeout_atomic(port->membase + AML_UART_STATUS, reg, 489 reg & AML_UART_TX_EMPTY, 490 AML_UART_POLL_USEC, 491 AML_UART_TIMEOUT_USEC); 492 if (ret == -ETIMEDOUT) { 493 dev_err(port->dev, "Timeout waiting for UART TX EMPTY\n"); 494 goto out; 495 } 496 497 /* Write the character */ 498 writel(c, port->membase + AML_UART_WFIFO); 499 500 /* Wait until FIFO is empty or timeout */ 501 ret = readl_poll_timeout_atomic(port->membase + AML_UART_STATUS, reg, 502 reg & AML_UART_TX_EMPTY, 503 AML_UART_POLL_USEC, 504 AML_UART_TIMEOUT_USEC); 505 if (ret == -ETIMEDOUT) 506 dev_err(port->dev, "Timeout waiting for UART TX EMPTY\n"); 507 508out: 509 uart_port_unlock_irqrestore(port, flags); 510} 511 512#endif /* CONFIG_CONSOLE_POLL */ 513 514static const struct uart_ops meson_uart_ops = { 515 .set_mctrl = meson_uart_set_mctrl, 516 .get_mctrl = meson_uart_get_mctrl, 517 .tx_empty = meson_uart_tx_empty, 518 .start_tx = meson_uart_start_tx, 519 .stop_tx = meson_uart_stop_tx, 520 .stop_rx = meson_uart_stop_rx, 521 .startup = meson_uart_startup, 522 .shutdown = meson_uart_shutdown, 523 .set_termios = meson_uart_set_termios, 524 .type = meson_uart_type, 525 .config_port = meson_uart_config_port, 526 .request_port = meson_uart_request_port, 527 .release_port = meson_uart_release_port, 528 .verify_port = meson_uart_verify_port, 529#ifdef CONFIG_CONSOLE_POLL 530 .poll_get_char = meson_uart_poll_get_char, 531 .poll_put_char = meson_uart_poll_put_char, 532#endif 533}; 534 535#ifdef CONFIG_SERIAL_MESON_CONSOLE 536static void meson_uart_enable_tx_engine(struct uart_port *port) 537{ 538 u32 val; 539 540 val = readl(port->membase + AML_UART_CONTROL); 541 val |= AML_UART_TX_EN; 542 writel(val, port->membase + AML_UART_CONTROL); 543} 544 545static void meson_console_putchar(struct uart_port *port, unsigned char ch) 546{ 547 if (!port->membase) 548 return; 549 550 while (readl(port->membase + AML_UART_STATUS) & AML_UART_TX_FULL) 551 cpu_relax(); 552 writel(ch, port->membase + AML_UART_WFIFO); 553} 554 555static void meson_serial_port_write(struct uart_port *port, const char *s, 556 u_int count) 557{ 558 unsigned long flags; 559 int locked = 1; 560 u32 val, tmp; 561 562 if (oops_in_progress) 563 locked = uart_port_trylock_irqsave(port, &flags); 564 else 565 uart_port_lock_irqsave(port, &flags); 566 567 val = readl(port->membase + AML_UART_CONTROL); 568 tmp = val & ~(AML_UART_TX_INT_EN | AML_UART_RX_INT_EN); 569 writel(tmp, port->membase + AML_UART_CONTROL); 570 571 uart_console_write(port, s, count, meson_console_putchar); 572 writel(val, port->membase + AML_UART_CONTROL); 573 574 if (locked) 575 uart_port_unlock_irqrestore(port, flags); 576} 577 578static void meson_serial_console_write(struct console *co, const char *s, 579 u_int count) 580{ 581 struct uart_port *port; 582 583 port = meson_ports[co->index]; 584 if (!port) 585 return; 586 587 meson_serial_port_write(port, s, count); 588} 589 590static int meson_serial_console_setup(struct console *co, char *options) 591{ 592 struct uart_port *port; 593 int baud = 115200; 594 int bits = 8; 595 int parity = 'n'; 596 int flow = 'n'; 597 598 if (co->index < 0 || co->index >= AML_UART_PORT_NUM) 599 return -EINVAL; 600 601 port = meson_ports[co->index]; 602 if (!port || !port->membase) 603 return -ENODEV; 604 605 meson_uart_enable_tx_engine(port); 606 607 if (options) 608 uart_parse_options(options, &baud, &parity, &bits, &flow); 609 610 return uart_set_options(port, co, baud, parity, bits, flow); 611} 612 613#define MESON_SERIAL_CONSOLE(_devname) \ 614 static struct console meson_serial_console_##_devname = { \ 615 .name = __stringify(_devname), \ 616 .write = meson_serial_console_write, \ 617 .device = uart_console_device, \ 618 .setup = meson_serial_console_setup, \ 619 .flags = CON_PRINTBUFFER, \ 620 .index = -1, \ 621 .data = &meson_uart_driver_##_devname, \ 622 } 623 624MESON_SERIAL_CONSOLE(ttyAML); 625MESON_SERIAL_CONSOLE(ttyS); 626 627static void meson_serial_early_console_write(struct console *co, 628 const char *s, 629 u_int count) 630{ 631 struct earlycon_device *dev = co->data; 632 633 meson_serial_port_write(&dev->port, s, count); 634} 635 636static int __init 637meson_serial_early_console_setup(struct earlycon_device *device, const char *opt) 638{ 639 if (!device->port.membase) 640 return -ENODEV; 641 642 meson_uart_enable_tx_engine(&device->port); 643 device->con->write = meson_serial_early_console_write; 644 return 0; 645} 646 647OF_EARLYCON_DECLARE(meson, "amlogic,meson-ao-uart", meson_serial_early_console_setup); 648OF_EARLYCON_DECLARE(meson, "amlogic,meson-s4-uart", meson_serial_early_console_setup); 649 650#define MESON_SERIAL_CONSOLE_PTR(_devname) (&meson_serial_console_##_devname) 651#else 652#define MESON_SERIAL_CONSOLE_PTR(_devname) (NULL) 653#endif 654 655#define MESON_UART_DRIVER(_devname) \ 656 static struct uart_driver meson_uart_driver_##_devname = { \ 657 .owner = THIS_MODULE, \ 658 .driver_name = "meson_uart", \ 659 .dev_name = __stringify(_devname), \ 660 .nr = AML_UART_PORT_NUM, \ 661 .cons = MESON_SERIAL_CONSOLE_PTR(_devname), \ 662 } 663 664MESON_UART_DRIVER(ttyAML); 665MESON_UART_DRIVER(ttyS); 666 667static int meson_uart_probe_clocks(struct platform_device *pdev, 668 struct uart_port *port) 669{ 670 struct clk *clk_xtal = NULL; 671 struct clk *clk_pclk = NULL; 672 struct clk *clk_baud = NULL; 673 674 clk_pclk = devm_clk_get_enabled(&pdev->dev, "pclk"); 675 if (IS_ERR(clk_pclk)) 676 return PTR_ERR(clk_pclk); 677 678 clk_xtal = devm_clk_get_enabled(&pdev->dev, "xtal"); 679 if (IS_ERR(clk_xtal)) 680 return PTR_ERR(clk_xtal); 681 682 clk_baud = devm_clk_get_enabled(&pdev->dev, "baud"); 683 if (IS_ERR(clk_baud)) 684 return PTR_ERR(clk_baud); 685 686 port->uartclk = clk_get_rate(clk_baud); 687 688 return 0; 689} 690 691static struct uart_driver *meson_uart_current(const struct meson_uart_data *pd) 692{ 693 return (pd && pd->uart_driver) ? 694 pd->uart_driver : &meson_uart_driver_ttyAML; 695} 696 697static int meson_uart_probe(struct platform_device *pdev) 698{ 699 const struct meson_uart_data *priv_data; 700 struct uart_driver *uart_driver; 701 struct resource *res_mem; 702 struct uart_port *port; 703 u32 fifosize = 64; /* Default is 64, 128 for EE UART_0 */ 704 int ret = 0; 705 int irq; 706 bool has_rtscts; 707 708 if (pdev->dev.of_node) 709 pdev->id = of_alias_get_id(pdev->dev.of_node, "serial"); 710 711 if (pdev->id < 0) { 712 int id; 713 714 for (id = AML_UART_PORT_OFFSET; id < AML_UART_PORT_NUM; id++) { 715 if (!meson_ports[id]) { 716 pdev->id = id; 717 break; 718 } 719 } 720 } 721 722 if (pdev->id < 0 || pdev->id >= AML_UART_PORT_NUM) 723 return -EINVAL; 724 725 res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 726 if (!res_mem) 727 return -ENODEV; 728 729 irq = platform_get_irq(pdev, 0); 730 if (irq < 0) 731 return irq; 732 733 of_property_read_u32(pdev->dev.of_node, "fifo-size", &fifosize); 734 has_rtscts = of_property_read_bool(pdev->dev.of_node, "uart-has-rtscts"); 735 736 if (meson_ports[pdev->id]) { 737 return dev_err_probe(&pdev->dev, -EBUSY, 738 "port %d already allocated\n", pdev->id); 739 } 740 741 port = devm_kzalloc(&pdev->dev, sizeof(struct uart_port), GFP_KERNEL); 742 if (!port) 743 return -ENOMEM; 744 745 ret = meson_uart_probe_clocks(pdev, port); 746 if (ret) 747 return ret; 748 749 priv_data = device_get_match_data(&pdev->dev); 750 751 uart_driver = meson_uart_current(priv_data); 752 753 if (!uart_driver->state) { 754 ret = uart_register_driver(uart_driver); 755 if (ret) 756 return dev_err_probe(&pdev->dev, ret, 757 "can't register uart driver\n"); 758 } 759 760 port->iotype = UPIO_MEM; 761 port->mapbase = res_mem->start; 762 port->mapsize = resource_size(res_mem); 763 port->irq = irq; 764 port->flags = UPF_BOOT_AUTOCONF | UPF_LOW_LATENCY; 765 if (has_rtscts) 766 port->flags |= UPF_HARD_FLOW; 767 port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_MESON_CONSOLE); 768 port->dev = &pdev->dev; 769 port->line = pdev->id; 770 port->type = PORT_MESON; 771 port->x_char = 0; 772 port->ops = &meson_uart_ops; 773 port->fifosize = fifosize; 774 port->private_data = (void *)priv_data; 775 776 meson_ports[pdev->id] = port; 777 platform_set_drvdata(pdev, port); 778 779 /* reset port before registering (and possibly registering console) */ 780 if (meson_uart_request_port(port) >= 0) { 781 meson_uart_reset(port); 782 meson_uart_release_port(port); 783 } 784 785 ret = uart_add_one_port(uart_driver, port); 786 if (ret) 787 meson_ports[pdev->id] = NULL; 788 789 return ret; 790} 791 792static void meson_uart_remove(struct platform_device *pdev) 793{ 794 struct uart_driver *uart_driver; 795 struct uart_port *port; 796 797 port = platform_get_drvdata(pdev); 798 uart_driver = meson_uart_current(port->private_data); 799 uart_remove_one_port(uart_driver, port); 800 meson_ports[pdev->id] = NULL; 801 802 for (int id = 0; id < AML_UART_PORT_NUM; id++) 803 if (meson_ports[id]) 804 return; 805 806 /* No more available uart ports, unregister uart driver */ 807 uart_unregister_driver(uart_driver); 808} 809 810static struct meson_uart_data meson_g12a_uart_data = { 811 .has_xtal_div2 = true, 812}; 813 814static struct meson_uart_data meson_a1_uart_data = { 815 .uart_driver = &meson_uart_driver_ttyS, 816 .has_xtal_div2 = false, 817}; 818 819static struct meson_uart_data meson_s4_uart_data = { 820 .uart_driver = &meson_uart_driver_ttyS, 821 .has_xtal_div2 = true, 822}; 823 824static const struct of_device_id meson_uart_dt_match[] = { 825 { .compatible = "amlogic,meson6-uart" }, 826 { .compatible = "amlogic,meson8-uart" }, 827 { .compatible = "amlogic,meson8b-uart" }, 828 { .compatible = "amlogic,meson-gx-uart" }, 829 { 830 .compatible = "amlogic,meson-g12a-uart", 831 .data = (void *)&meson_g12a_uart_data, 832 }, 833 { 834 .compatible = "amlogic,meson-s4-uart", 835 .data = (void *)&meson_s4_uart_data, 836 }, 837 { 838 .compatible = "amlogic,meson-a1-uart", 839 .data = (void *)&meson_a1_uart_data, 840 }, 841 { /* sentinel */ }, 842}; 843MODULE_DEVICE_TABLE(of, meson_uart_dt_match); 844 845static struct platform_driver meson_uart_platform_driver = { 846 .probe = meson_uart_probe, 847 .remove_new = meson_uart_remove, 848 .driver = { 849 .name = "meson_uart", 850 .of_match_table = meson_uart_dt_match, 851 }, 852}; 853 854module_platform_driver(meson_uart_platform_driver); 855 856MODULE_AUTHOR("Carlo Caione <carlo@caione.org>"); 857MODULE_DESCRIPTION("Amlogic Meson serial port driver"); 858MODULE_LICENSE("GPL v2"); 859