1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Probe module for 8250/16550-type MCHP PCI serial ports. 4 * 5 * Based on drivers/tty/serial/8250/8250_pci.c, 6 * 7 * Copyright (C) 2022 Microchip Technology Inc., All Rights Reserved. 8 */ 9 10#include <linux/array_size.h> 11#include <linux/bitfield.h> 12#include <linux/bits.h> 13#include <linux/circ_buf.h> 14#include <linux/device.h> 15#include <linux/errno.h> 16#include <linux/gfp_types.h> 17#include <linux/io.h> 18#include <linux/iopoll.h> 19#include <linux/minmax.h> 20#include <linux/module.h> 21#include <linux/mutex.h> 22#include <linux/overflow.h> 23#include <linux/pci.h> 24#include <linux/pm.h> 25#include <linux/serial_core.h> 26#include <linux/serial_reg.h> 27#include <linux/serial_8250.h> 28#include <linux/spinlock.h> 29#include <linux/string.h> 30#include <linux/time.h> 31#include <linux/tty.h> 32#include <linux/tty_flip.h> 33#include <linux/types.h> 34#include <linux/units.h> 35 36#include <asm/byteorder.h> 37 38#include "8250.h" 39#include "8250_pcilib.h" 40 41#define PCI_DEVICE_ID_EFAR_PCI12000 0xa002 42#define PCI_DEVICE_ID_EFAR_PCI11010 0xa012 43#define PCI_DEVICE_ID_EFAR_PCI11101 0xa022 44#define PCI_DEVICE_ID_EFAR_PCI11400 0xa032 45#define PCI_DEVICE_ID_EFAR_PCI11414 0xa042 46 47#define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_4p 0x0001 48#define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_3p012 0x0002 49#define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_3p013 0x0003 50#define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_3p023 0x0004 51#define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_3p123 0x0005 52#define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p01 0x0006 53#define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p02 0x0007 54#define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p03 0x0008 55#define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p12 0x0009 56#define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p13 0x000a 57#define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p23 0x000b 58#define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_1p0 0x000c 59#define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_1p1 0x000d 60#define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_1p2 0x000e 61#define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_1p3 0x000f 62 63#define PCI_SUBDEVICE_ID_EFAR_PCI12000 PCI_DEVICE_ID_EFAR_PCI12000 64#define PCI_SUBDEVICE_ID_EFAR_PCI11010 PCI_DEVICE_ID_EFAR_PCI11010 65#define PCI_SUBDEVICE_ID_EFAR_PCI11101 PCI_DEVICE_ID_EFAR_PCI11101 66#define PCI_SUBDEVICE_ID_EFAR_PCI11400 PCI_DEVICE_ID_EFAR_PCI11400 67#define PCI_SUBDEVICE_ID_EFAR_PCI11414 PCI_DEVICE_ID_EFAR_PCI11414 68 69#define UART_SYSTEM_ADDR_BASE 0x1000 70#define UART_DEV_REV_REG (UART_SYSTEM_ADDR_BASE + 0x00) 71#define UART_DEV_REV_MASK GENMASK(7, 0) 72#define UART_SYSLOCK_REG (UART_SYSTEM_ADDR_BASE + 0xA0) 73#define UART_SYSLOCK BIT(2) 74#define SYSLOCK_SLEEP_TIMEOUT 100 75#define SYSLOCK_RETRY_CNT 1000 76 77#define UART_RX_BYTE_FIFO 0x00 78#define UART_TX_BYTE_FIFO 0x00 79#define UART_FIFO_CTL 0x02 80 81#define UART_ACTV_REG 0x11 82#define UART_BLOCK_SET_ACTIVE BIT(0) 83 84#define UART_PCI_CTRL_REG 0x80 85#define UART_PCI_CTRL_SET_MULTIPLE_MSI BIT(4) 86#define UART_PCI_CTRL_D3_CLK_ENABLE BIT(0) 87 88#define ADCL_CFG_REG 0x40 89#define ADCL_CFG_POL_SEL BIT(2) 90#define ADCL_CFG_PIN_SEL BIT(1) 91#define ADCL_CFG_EN BIT(0) 92 93#define UART_BIT_SAMPLE_CNT_8 8 94#define UART_BIT_SAMPLE_CNT_16 16 95#define BAUD_CLOCK_DIV_INT_MSK GENMASK(31, 8) 96#define ADCL_CFG_RTS_DELAY_MASK GENMASK(11, 8) 97 98#define UART_WAKE_REG 0x8C 99#define UART_WAKE_MASK_REG 0x90 100#define UART_WAKE_N_PIN BIT(2) 101#define UART_WAKE_NCTS BIT(1) 102#define UART_WAKE_INT BIT(0) 103#define UART_WAKE_SRCS \ 104 (UART_WAKE_N_PIN | UART_WAKE_NCTS | UART_WAKE_INT) 105 106#define UART_BAUD_CLK_DIVISOR_REG 0x54 107#define FRAC_DIV_CFG_REG 0x58 108 109#define UART_RESET_REG 0x94 110#define UART_RESET_D3_RESET_DISABLE BIT(16) 111 112#define UART_BURST_STATUS_REG 0x9C 113#define UART_TX_BURST_FIFO 0xA0 114#define UART_RX_BURST_FIFO 0xA4 115 116#define UART_BIT_DIVISOR_8 0x26731000 117#define UART_BIT_DIVISOR_16 0x6ef71000 118#define UART_BAUD_4MBPS 4000000 119 120#define MAX_PORTS 4 121#define PORT_OFFSET 0x100 122#define RX_BUF_SIZE 512 123#define UART_BYTE_SIZE 1 124#define UART_BURST_SIZE 4 125 126#define UART_BST_STAT_RX_COUNT_MASK 0x00FF 127#define UART_BST_STAT_TX_COUNT_MASK 0xFF00 128#define UART_BST_STAT_IIR_INT_PEND 0x100000 129#define UART_LSR_OVERRUN_ERR_CLR 0x43 130#define UART_BST_STAT_LSR_RX_MASK 0x9F000000 131#define UART_BST_STAT_LSR_RX_ERR_MASK 0x9E000000 132#define UART_BST_STAT_LSR_OVERRUN_ERR 0x2000000 133#define UART_BST_STAT_LSR_PARITY_ERR 0x4000000 134#define UART_BST_STAT_LSR_FRAME_ERR 0x8000000 135#define UART_BST_STAT_LSR_THRE 0x20000000 136 137struct pci1xxxx_8250 { 138 unsigned int nr; 139 u8 dev_rev; 140 u8 pad[3]; 141 void __iomem *membase; 142 int line[] __counted_by(nr); 143}; 144 145static const struct serial_rs485 pci1xxxx_rs485_supported = { 146 .flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND | 147 SER_RS485_RTS_AFTER_SEND, 148 .delay_rts_after_send = 1, 149 /* Delay RTS before send is not supported */ 150}; 151 152static int pci1xxxx_set_sys_lock(struct pci1xxxx_8250 *port) 153{ 154 writel(UART_SYSLOCK, port->membase + UART_SYSLOCK_REG); 155 return readl(port->membase + UART_SYSLOCK_REG); 156} 157 158static int pci1xxxx_acquire_sys_lock(struct pci1xxxx_8250 *port) 159{ 160 u32 regval; 161 162 return readx_poll_timeout(pci1xxxx_set_sys_lock, port, regval, 163 (regval & UART_SYSLOCK), 164 SYSLOCK_SLEEP_TIMEOUT, 165 SYSLOCK_RETRY_CNT * SYSLOCK_SLEEP_TIMEOUT); 166} 167 168static void pci1xxxx_release_sys_lock(struct pci1xxxx_8250 *port) 169{ 170 writel(0x0, port->membase + UART_SYSLOCK_REG); 171} 172 173static const int logical_to_physical_port_idx[][MAX_PORTS] = { 174 {0, 1, 2, 3}, /* PCI12000, PCI11010, PCI11101, PCI11400, PCI11414 */ 175 {0, 1, 2, 3}, /* PCI4p */ 176 {0, 1, 2, -1}, /* PCI3p012 */ 177 {0, 1, 3, -1}, /* PCI3p013 */ 178 {0, 2, 3, -1}, /* PCI3p023 */ 179 {1, 2, 3, -1}, /* PCI3p123 */ 180 {0, 1, -1, -1}, /* PCI2p01 */ 181 {0, 2, -1, -1}, /* PCI2p02 */ 182 {0, 3, -1, -1}, /* PCI2p03 */ 183 {1, 2, -1, -1}, /* PCI2p12 */ 184 {1, 3, -1, -1}, /* PCI2p13 */ 185 {2, 3, -1, -1}, /* PCI2p23 */ 186 {0, -1, -1, -1}, /* PCI1p0 */ 187 {1, -1, -1, -1}, /* PCI1p1 */ 188 {2, -1, -1, -1}, /* PCI1p2 */ 189 {3, -1, -1, -1}, /* PCI1p3 */ 190}; 191 192static int pci1xxxx_get_num_ports(struct pci_dev *dev) 193{ 194 switch (dev->subsystem_device) { 195 case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_1p0: 196 case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_1p1: 197 case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_1p2: 198 case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_1p3: 199 case PCI_SUBDEVICE_ID_EFAR_PCI12000: 200 case PCI_SUBDEVICE_ID_EFAR_PCI11010: 201 case PCI_SUBDEVICE_ID_EFAR_PCI11101: 202 case PCI_SUBDEVICE_ID_EFAR_PCI11400: 203 default: 204 return 1; 205 case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p01: 206 case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p02: 207 case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p03: 208 case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p12: 209 case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p13: 210 case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p23: 211 return 2; 212 case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_3p012: 213 case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_3p123: 214 case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_3p013: 215 case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_3p023: 216 return 3; 217 case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_4p: 218 case PCI_SUBDEVICE_ID_EFAR_PCI11414: 219 return 4; 220 } 221} 222 223static unsigned int pci1xxxx_get_divisor(struct uart_port *port, 224 unsigned int baud, unsigned int *frac) 225{ 226 unsigned int uart_sample_cnt; 227 unsigned int quot; 228 229 if (baud >= UART_BAUD_4MBPS) 230 uart_sample_cnt = UART_BIT_SAMPLE_CNT_8; 231 else 232 uart_sample_cnt = UART_BIT_SAMPLE_CNT_16; 233 234 /* 235 * Calculate baud rate sampling period in nanoseconds. 236 * Fractional part x denotes x/255 parts of a nanosecond. 237 */ 238 quot = NSEC_PER_SEC / (baud * uart_sample_cnt); 239 *frac = (NSEC_PER_SEC - quot * baud * uart_sample_cnt) * 240 255 / uart_sample_cnt / baud; 241 242 return quot; 243} 244 245static void pci1xxxx_set_divisor(struct uart_port *port, unsigned int baud, 246 unsigned int quot, unsigned int frac) 247{ 248 if (baud >= UART_BAUD_4MBPS) 249 writel(UART_BIT_DIVISOR_8, port->membase + FRAC_DIV_CFG_REG); 250 else 251 writel(UART_BIT_DIVISOR_16, port->membase + FRAC_DIV_CFG_REG); 252 253 writel(FIELD_PREP(BAUD_CLOCK_DIV_INT_MSK, quot) | frac, 254 port->membase + UART_BAUD_CLK_DIVISOR_REG); 255} 256 257static int pci1xxxx_rs485_config(struct uart_port *port, 258 struct ktermios *termios, 259 struct serial_rs485 *rs485) 260{ 261 u32 delay_in_baud_periods; 262 u32 baud_period_in_ns; 263 u32 mode_cfg = 0; 264 u32 sample_cnt; 265 u32 clock_div; 266 u32 frac_div; 267 268 frac_div = readl(port->membase + FRAC_DIV_CFG_REG); 269 270 if (frac_div == UART_BIT_DIVISOR_16) 271 sample_cnt = UART_BIT_SAMPLE_CNT_16; 272 else 273 sample_cnt = UART_BIT_SAMPLE_CNT_8; 274 275 /* 276 * pci1xxxx's uart hardware supports only RTS delay after 277 * Tx and in units of bit times to a maximum of 15 278 */ 279 if (rs485->flags & SER_RS485_ENABLED) { 280 mode_cfg = ADCL_CFG_EN | ADCL_CFG_PIN_SEL; 281 282 if (!(rs485->flags & SER_RS485_RTS_ON_SEND)) 283 mode_cfg |= ADCL_CFG_POL_SEL; 284 285 if (rs485->delay_rts_after_send) { 286 clock_div = readl(port->membase + UART_BAUD_CLK_DIVISOR_REG); 287 baud_period_in_ns = 288 FIELD_GET(BAUD_CLOCK_DIV_INT_MSK, clock_div) * 289 sample_cnt; 290 delay_in_baud_periods = 291 rs485->delay_rts_after_send * NSEC_PER_MSEC / 292 baud_period_in_ns; 293 delay_in_baud_periods = 294 min_t(u32, delay_in_baud_periods, 295 FIELD_MAX(ADCL_CFG_RTS_DELAY_MASK)); 296 mode_cfg |= FIELD_PREP(ADCL_CFG_RTS_DELAY_MASK, 297 delay_in_baud_periods); 298 rs485->delay_rts_after_send = 299 baud_period_in_ns * delay_in_baud_periods / 300 NSEC_PER_MSEC; 301 } 302 } 303 writel(mode_cfg, port->membase + ADCL_CFG_REG); 304 return 0; 305} 306 307static u32 pci1xxxx_read_burst_status(struct uart_port *port) 308{ 309 u32 status; 310 311 status = readl(port->membase + UART_BURST_STATUS_REG); 312 if (status & UART_BST_STAT_LSR_RX_ERR_MASK) { 313 if (status & UART_BST_STAT_LSR_OVERRUN_ERR) { 314 writeb(UART_LSR_OVERRUN_ERR_CLR, 315 port->membase + UART_FIFO_CTL); 316 port->icount.overrun++; 317 } 318 319 if (status & UART_BST_STAT_LSR_FRAME_ERR) 320 port->icount.frame++; 321 322 if (status & UART_BST_STAT_LSR_PARITY_ERR) 323 port->icount.parity++; 324 } 325 return status; 326} 327 328static void pci1xxxx_process_read_data(struct uart_port *port, 329 unsigned char *rx_buff, u32 *buff_index, 330 u32 *valid_byte_count) 331{ 332 u32 valid_burst_count = *valid_byte_count / UART_BURST_SIZE; 333 u32 *burst_buf; 334 335 /* 336 * Depending on the RX Trigger Level the number of bytes that can be 337 * stored in RX FIFO at a time varies. Each transaction reads data 338 * in DWORDs. If there are less than four remaining valid_byte_count 339 * to read, the data is received one byte at a time. 340 */ 341 while (valid_burst_count--) { 342 if (*buff_index > (RX_BUF_SIZE - UART_BURST_SIZE)) 343 break; 344 burst_buf = (u32 *)&rx_buff[*buff_index]; 345 *burst_buf = readl(port->membase + UART_RX_BURST_FIFO); 346 *buff_index += UART_BURST_SIZE; 347 *valid_byte_count -= UART_BURST_SIZE; 348 } 349 350 while (*valid_byte_count) { 351 if (*buff_index >= RX_BUF_SIZE) 352 break; 353 rx_buff[*buff_index] = readb(port->membase + 354 UART_RX_BYTE_FIFO); 355 *buff_index += UART_BYTE_SIZE; 356 *valid_byte_count -= UART_BYTE_SIZE; 357 } 358} 359 360static void pci1xxxx_rx_burst(struct uart_port *port, u32 uart_status) 361{ 362 u32 valid_byte_count = uart_status & UART_BST_STAT_RX_COUNT_MASK; 363 struct tty_port *tty_port = &port->state->port; 364 unsigned char rx_buff[RX_BUF_SIZE]; 365 u32 buff_index = 0; 366 u32 copied_len; 367 368 if (valid_byte_count != 0 && 369 valid_byte_count < RX_BUF_SIZE) { 370 pci1xxxx_process_read_data(port, rx_buff, &buff_index, 371 &valid_byte_count); 372 373 copied_len = (u32)tty_insert_flip_string(tty_port, rx_buff, 374 buff_index); 375 376 if (copied_len != buff_index) 377 port->icount.overrun += buff_index - copied_len; 378 379 port->icount.rx += buff_index; 380 tty_flip_buffer_push(tty_port); 381 } 382} 383 384static void pci1xxxx_process_write_data(struct uart_port *port, 385 struct circ_buf *xmit, 386 int *data_empty_count, 387 u32 *valid_byte_count) 388{ 389 u32 valid_burst_count = *valid_byte_count / UART_BURST_SIZE; 390 391 /* 392 * Each transaction transfers data in DWORDs. If there are less than 393 * four remaining valid_byte_count to transfer or if the circular 394 * buffer has insufficient space for a DWORD, the data is transferred 395 * one byte at a time. 396 */ 397 while (valid_burst_count) { 398 if (*data_empty_count - UART_BURST_SIZE < 0) 399 break; 400 if (xmit->tail > (UART_XMIT_SIZE - UART_BURST_SIZE)) 401 break; 402 writel(*(unsigned int *)&xmit->buf[xmit->tail], 403 port->membase + UART_TX_BURST_FIFO); 404 *valid_byte_count -= UART_BURST_SIZE; 405 *data_empty_count -= UART_BURST_SIZE; 406 valid_burst_count -= UART_BYTE_SIZE; 407 408 xmit->tail = (xmit->tail + UART_BURST_SIZE) & 409 (UART_XMIT_SIZE - 1); 410 } 411 412 while (*valid_byte_count) { 413 if (*data_empty_count - UART_BYTE_SIZE < 0) 414 break; 415 writeb(xmit->buf[xmit->tail], port->membase + 416 UART_TX_BYTE_FIFO); 417 *data_empty_count -= UART_BYTE_SIZE; 418 *valid_byte_count -= UART_BYTE_SIZE; 419 420 /* 421 * When the tail of the circular buffer is reached, the next 422 * byte is transferred to the beginning of the buffer. 423 */ 424 xmit->tail = (xmit->tail + UART_BYTE_SIZE) & 425 (UART_XMIT_SIZE - 1); 426 427 /* 428 * If there are any pending burst count, data is handled by 429 * transmitting DWORDs at a time. 430 */ 431 if (valid_burst_count && (xmit->tail < 432 (UART_XMIT_SIZE - UART_BURST_SIZE))) 433 break; 434 } 435} 436 437static void pci1xxxx_tx_burst(struct uart_port *port, u32 uart_status) 438{ 439 struct uart_8250_port *up = up_to_u8250p(port); 440 u32 valid_byte_count; 441 int data_empty_count; 442 struct circ_buf *xmit; 443 444 xmit = &port->state->xmit; 445 446 if (port->x_char) { 447 writeb(port->x_char, port->membase + UART_TX); 448 port->icount.tx++; 449 port->x_char = 0; 450 return; 451 } 452 453 if ((uart_tx_stopped(port)) || (uart_circ_empty(xmit))) { 454 port->ops->stop_tx(port); 455 } else { 456 data_empty_count = (pci1xxxx_read_burst_status(port) & 457 UART_BST_STAT_TX_COUNT_MASK) >> 8; 458 do { 459 valid_byte_count = uart_circ_chars_pending(xmit); 460 461 pci1xxxx_process_write_data(port, xmit, 462 &data_empty_count, 463 &valid_byte_count); 464 465 port->icount.tx++; 466 if (uart_circ_empty(xmit)) 467 break; 468 } while (data_empty_count && valid_byte_count); 469 } 470 471 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 472 uart_write_wakeup(port); 473 474 /* 475 * With RPM enabled, we have to wait until the FIFO is empty before 476 * the HW can go idle. So we get here once again with empty FIFO and 477 * disable the interrupt and RPM in __stop_tx() 478 */ 479 if (uart_circ_empty(xmit) && !(up->capabilities & UART_CAP_RPM)) 480 port->ops->stop_tx(port); 481} 482 483static int pci1xxxx_handle_irq(struct uart_port *port) 484{ 485 unsigned long flags; 486 u32 status; 487 488 status = pci1xxxx_read_burst_status(port); 489 490 if (status & UART_BST_STAT_IIR_INT_PEND) 491 return 0; 492 493 spin_lock_irqsave(&port->lock, flags); 494 495 if (status & UART_BST_STAT_LSR_RX_MASK) 496 pci1xxxx_rx_burst(port, status); 497 498 if (status & UART_BST_STAT_LSR_THRE) 499 pci1xxxx_tx_burst(port, status); 500 501 spin_unlock_irqrestore(&port->lock, flags); 502 503 return 1; 504} 505 506static bool pci1xxxx_port_suspend(int line) 507{ 508 struct uart_8250_port *up = serial8250_get_port(line); 509 struct uart_port *port = &up->port; 510 struct tty_port *tport = &port->state->port; 511 unsigned long flags; 512 bool ret = false; 513 u8 wakeup_mask; 514 515 mutex_lock(&tport->mutex); 516 if (port->suspended == 0 && port->dev) { 517 wakeup_mask = readb(up->port.membase + UART_WAKE_MASK_REG); 518 519 uart_port_lock_irqsave(port, &flags); 520 port->mctrl &= ~TIOCM_OUT2; 521 port->ops->set_mctrl(port, port->mctrl); 522 uart_port_unlock_irqrestore(port, flags); 523 524 ret = (wakeup_mask & UART_WAKE_SRCS) != UART_WAKE_SRCS; 525 } 526 527 writeb(UART_WAKE_SRCS, port->membase + UART_WAKE_REG); 528 mutex_unlock(&tport->mutex); 529 530 return ret; 531} 532 533static void pci1xxxx_port_resume(int line) 534{ 535 struct uart_8250_port *up = serial8250_get_port(line); 536 struct uart_port *port = &up->port; 537 struct tty_port *tport = &port->state->port; 538 unsigned long flags; 539 540 mutex_lock(&tport->mutex); 541 writeb(UART_BLOCK_SET_ACTIVE, port->membase + UART_ACTV_REG); 542 writeb(UART_WAKE_SRCS, port->membase + UART_WAKE_REG); 543 544 if (port->suspended == 0) { 545 uart_port_lock_irqsave(port, &flags); 546 port->mctrl |= TIOCM_OUT2; 547 port->ops->set_mctrl(port, port->mctrl); 548 uart_port_unlock_irqrestore(port, flags); 549 } 550 mutex_unlock(&tport->mutex); 551} 552 553static int pci1xxxx_suspend(struct device *dev) 554{ 555 struct pci1xxxx_8250 *priv = dev_get_drvdata(dev); 556 struct pci_dev *pcidev = to_pci_dev(dev); 557 bool wakeup = false; 558 unsigned int data; 559 void __iomem *p; 560 int i; 561 562 for (i = 0; i < priv->nr; i++) { 563 if (priv->line[i] >= 0) { 564 serial8250_suspend_port(priv->line[i]); 565 wakeup |= pci1xxxx_port_suspend(priv->line[i]); 566 } 567 } 568 569 p = pci_ioremap_bar(pcidev, 0); 570 if (!p) { 571 dev_err(dev, "remapping of bar 0 memory failed"); 572 return -ENOMEM; 573 } 574 575 data = readl(p + UART_RESET_REG); 576 writel(data | UART_RESET_D3_RESET_DISABLE, p + UART_RESET_REG); 577 578 if (wakeup) 579 writeb(UART_PCI_CTRL_D3_CLK_ENABLE, p + UART_PCI_CTRL_REG); 580 581 iounmap(p); 582 device_set_wakeup_enable(dev, true); 583 pci_wake_from_d3(pcidev, true); 584 585 return 0; 586} 587 588static int pci1xxxx_resume(struct device *dev) 589{ 590 struct pci1xxxx_8250 *priv = dev_get_drvdata(dev); 591 struct pci_dev *pcidev = to_pci_dev(dev); 592 unsigned int data; 593 void __iomem *p; 594 int i; 595 596 p = pci_ioremap_bar(pcidev, 0); 597 if (!p) { 598 dev_err(dev, "remapping of bar 0 memory failed"); 599 return -ENOMEM; 600 } 601 602 data = readl(p + UART_RESET_REG); 603 writel(data & ~UART_RESET_D3_RESET_DISABLE, p + UART_RESET_REG); 604 iounmap(p); 605 606 for (i = 0; i < priv->nr; i++) { 607 if (priv->line[i] >= 0) { 608 pci1xxxx_port_resume(priv->line[i]); 609 serial8250_resume_port(priv->line[i]); 610 } 611 } 612 613 return 0; 614} 615 616static int pci1xxxx_setup(struct pci_dev *pdev, 617 struct uart_8250_port *port, int port_idx, int rev) 618{ 619 int ret; 620 621 port->port.flags |= UPF_FIXED_TYPE | UPF_SKIP_TEST; 622 port->port.type = PORT_MCHP16550A; 623 /* 624 * 8250 core considers prescaller value to be always 16. 625 * The MCHP ports support downscaled mode and hence the 626 * functional UART clock can be lower, i.e. 62.5MHz, than 627 * software expects in order to support higher baud rates. 628 * Assign here 64MHz to support 4Mbps. 629 * 630 * The value itself is not really used anywhere except baud 631 * rate calculations, so we can mangle it as we wish. 632 */ 633 port->port.uartclk = 64 * HZ_PER_MHZ; 634 port->port.set_termios = serial8250_do_set_termios; 635 port->port.get_divisor = pci1xxxx_get_divisor; 636 port->port.set_divisor = pci1xxxx_set_divisor; 637 port->port.rs485_config = pci1xxxx_rs485_config; 638 port->port.rs485_supported = pci1xxxx_rs485_supported; 639 640 /* From C0 rev Burst operation is supported */ 641 if (rev >= 0xC0) 642 port->port.handle_irq = pci1xxxx_handle_irq; 643 644 ret = serial8250_pci_setup_port(pdev, port, 0, PORT_OFFSET * port_idx, 0); 645 if (ret < 0) 646 return ret; 647 648 writeb(UART_BLOCK_SET_ACTIVE, port->port.membase + UART_ACTV_REG); 649 writeb(UART_WAKE_SRCS, port->port.membase + UART_WAKE_REG); 650 writeb(UART_WAKE_N_PIN, port->port.membase + UART_WAKE_MASK_REG); 651 652 return 0; 653} 654 655static unsigned int pci1xxxx_get_max_port(int subsys_dev) 656{ 657 unsigned int i = MAX_PORTS; 658 659 if (subsys_dev < ARRAY_SIZE(logical_to_physical_port_idx)) 660 while (i--) { 661 if (logical_to_physical_port_idx[subsys_dev][i] != -1) 662 return logical_to_physical_port_idx[subsys_dev][i] + 1; 663 } 664 665 if (subsys_dev == PCI_SUBDEVICE_ID_EFAR_PCI11414) 666 return 4; 667 668 return 1; 669} 670 671static int pci1xxxx_logical_to_physical_port_translate(int subsys_dev, int port) 672{ 673 if (subsys_dev < ARRAY_SIZE(logical_to_physical_port_idx)) 674 return logical_to_physical_port_idx[subsys_dev][port]; 675 676 return logical_to_physical_port_idx[0][port]; 677} 678 679static int pci1xxxx_get_device_revision(struct pci1xxxx_8250 *priv) 680{ 681 u32 regval; 682 int ret; 683 684 /* 685 * DEV REV is a system register, HW Syslock bit 686 * should be acquired before accessing the register 687 */ 688 ret = pci1xxxx_acquire_sys_lock(priv); 689 if (ret) 690 return ret; 691 692 regval = readl(priv->membase + UART_DEV_REV_REG); 693 priv->dev_rev = regval & UART_DEV_REV_MASK; 694 695 pci1xxxx_release_sys_lock(priv); 696 697 return 0; 698} 699 700static int pci1xxxx_serial_probe(struct pci_dev *pdev, 701 const struct pci_device_id *id) 702{ 703 struct device *dev = &pdev->dev; 704 struct pci1xxxx_8250 *priv; 705 struct uart_8250_port uart; 706 unsigned int max_vec_reqd; 707 unsigned int nr_ports, i; 708 int num_vectors; 709 int subsys_dev; 710 int port_idx; 711 int ret; 712 int rc; 713 714 rc = pcim_enable_device(pdev); 715 if (rc) 716 return rc; 717 718 nr_ports = pci1xxxx_get_num_ports(pdev); 719 720 priv = devm_kzalloc(dev, struct_size(priv, line, nr_ports), GFP_KERNEL); 721 if (!priv) 722 return -ENOMEM; 723 724 priv->membase = pci_ioremap_bar(pdev, 0); 725 if (!priv->membase) 726 return -ENOMEM; 727 728 ret = pci1xxxx_get_device_revision(priv); 729 if (ret) 730 return ret; 731 732 pci_set_master(pdev); 733 734 priv->nr = nr_ports; 735 736 subsys_dev = pdev->subsystem_device; 737 max_vec_reqd = pci1xxxx_get_max_port(subsys_dev); 738 739 num_vectors = pci_alloc_irq_vectors(pdev, 1, max_vec_reqd, PCI_IRQ_ALL_TYPES); 740 if (num_vectors < 0) { 741 pci_iounmap(pdev, priv->membase); 742 return num_vectors; 743 } 744 745 memset(&uart, 0, sizeof(uart)); 746 uart.port.flags = UPF_SHARE_IRQ | UPF_FIXED_PORT; 747 uart.port.dev = dev; 748 749 if (num_vectors == max_vec_reqd) 750 writeb(UART_PCI_CTRL_SET_MULTIPLE_MSI, priv->membase + UART_PCI_CTRL_REG); 751 752 for (i = 0; i < nr_ports; i++) { 753 priv->line[i] = -ENODEV; 754 755 port_idx = pci1xxxx_logical_to_physical_port_translate(subsys_dev, i); 756 757 if (num_vectors == max_vec_reqd) 758 uart.port.irq = pci_irq_vector(pdev, port_idx); 759 else 760 uart.port.irq = pci_irq_vector(pdev, 0); 761 762 rc = pci1xxxx_setup(pdev, &uart, port_idx, priv->dev_rev); 763 if (rc) { 764 dev_warn(dev, "Failed to setup port %u\n", i); 765 continue; 766 } 767 768 priv->line[i] = serial8250_register_8250_port(&uart); 769 if (priv->line[i] < 0) { 770 dev_warn(dev, 771 "Couldn't register serial port %lx, irq %d, type %d, error %d\n", 772 uart.port.iobase, uart.port.irq, uart.port.iotype, 773 priv->line[i]); 774 } 775 } 776 777 pci_set_drvdata(pdev, priv); 778 779 return 0; 780} 781 782static void pci1xxxx_serial_remove(struct pci_dev *dev) 783{ 784 struct pci1xxxx_8250 *priv = pci_get_drvdata(dev); 785 unsigned int i; 786 787 for (i = 0; i < priv->nr; i++) { 788 if (priv->line[i] >= 0) 789 serial8250_unregister_port(priv->line[i]); 790 } 791 792 pci_free_irq_vectors(dev); 793 pci_iounmap(dev, priv->membase); 794} 795 796static DEFINE_SIMPLE_DEV_PM_OPS(pci1xxxx_pm_ops, pci1xxxx_suspend, pci1xxxx_resume); 797 798static const struct pci_device_id pci1xxxx_pci_tbl[] = { 799 { PCI_VDEVICE(EFAR, PCI_DEVICE_ID_EFAR_PCI11010) }, 800 { PCI_VDEVICE(EFAR, PCI_DEVICE_ID_EFAR_PCI11101) }, 801 { PCI_VDEVICE(EFAR, PCI_DEVICE_ID_EFAR_PCI11400) }, 802 { PCI_VDEVICE(EFAR, PCI_DEVICE_ID_EFAR_PCI11414) }, 803 { PCI_VDEVICE(EFAR, PCI_DEVICE_ID_EFAR_PCI12000) }, 804 {} 805}; 806MODULE_DEVICE_TABLE(pci, pci1xxxx_pci_tbl); 807 808static struct pci_driver pci1xxxx_pci_driver = { 809 .name = "pci1xxxx serial", 810 .probe = pci1xxxx_serial_probe, 811 .remove = pci1xxxx_serial_remove, 812 .driver = { 813 .pm = pm_sleep_ptr(&pci1xxxx_pm_ops), 814 }, 815 .id_table = pci1xxxx_pci_tbl, 816}; 817module_pci_driver(pci1xxxx_pci_driver); 818 819static_assert((ARRAY_SIZE(logical_to_physical_port_idx) == PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_1p3 + 1)); 820 821MODULE_IMPORT_NS(SERIAL_8250_PCI); 822MODULE_DESCRIPTION("Microchip Technology Inc. PCIe to UART module"); 823MODULE_AUTHOR("Kumaravel Thiagarajan <kumaravel.thiagarajan@microchip.com>"); 824MODULE_AUTHOR("Tharun Kumar P <tharunkumar.pasumarthi@microchip.com>"); 825MODULE_LICENSE("GPL"); 826