tty/serial/mvebu-uart.c

191 	st = readl(port->membase + UART_STAT);
213 	unsigned int ctl = readl(port->membase + UART_INTR(port));
216 	writel(ctl, port->membase + UART_INTR(port));
225 		writel(c, port->membase + UART_TSH(port));
227 	ctl = readl(port->membase + UART_INTR(port));
229 	writel(ctl, port->membase + UART_INTR(port));
236 	ctl = readl(port->membase + UART_CTRL(port));
238 	writel(ctl, port->membase + UART_CTRL(port));
240 	ctl = readl(port->membase + UART_INTR(port));
242 	writel(ctl, port->membase + UART_INTR(port));
251 	ctl = readl(port->membase + UART_CTRL(port));
256 	writel(ctl, port->membase + UART_CTRL(port));
269 			ch = readl(port->membase + UART_RBR(port));
283 			ret = readl(port->membase + UART_STAT);
285 			writel(ret, port->membase + UART_STAT);
327 		status = readl(port->membase + UART_STAT);
338 		!(readl(port->membase + UART_STAT) & STAT_TX_FIFO_FUL),
339 		writel(ch, port->membase + UART_TSH(port)),
346 	unsigned int st = readl(port->membase + UART_STAT);
361 	unsigned int st = readl(port->membase + UART_STAT);
373 	unsigned int st = readl(port->membase + UART_STAT);
388 	       port->membase + UART_CTRL(port));
392 	ret = readl(port->membase + UART_STAT);
394 	writel(ret, port->membase + UART_STAT);
396 	writel(CTRL_BRK_INT, port->membase + UART_CTRL(port));
398 	ctl = readl(port->membase + UART_INTR(port));
400 	writel(ctl, port->membase + UART_INTR(port));
443 	writel(0, port->membase + UART_INTR(port));
518 	brdv = readl(port->membase + UART_BRDV);
521 	writel(brdv, port->membase + UART_BRDV);
524 	osamp = readl(port->membase + UART_OSAMP);
529 	writel(osamp, port->membase + UART_OSAMP);
611 	unsigned int st = readl(port->membase + UART_STAT);
616 	return readl(port->membase + UART_RBR(port));
624 		st = readl(port->membase + UART_STAT);
632 	writel(c, port->membase + UART_TSH(port));
665 		st = readl(port->membase + UART_STAT);
671 	writel(c, port->membase + UART_STD_TSH);
674 		st = readl(port->membase + UART_STAT);
693 	if (!device->port.membase)
709 	readl_poll_timeout_atomic(port->membase + UART_STAT, val,
717 	readl_poll_timeout_atomic(port->membase + UART_STAT, val,
724 	writel(ch, port->membase + UART_TSH(port));
740 	ier = readl(port->membase + UART_CTRL(port)) & CTRL_BRK_INT;
741 	intr = readl(port->membase + UART_INTR(port)) &
743 	writel(0, port->membase + UART_CTRL(port));
744 	writel(0, port->membase + UART_INTR(port));
751 		writel(ier, port->membase + UART_CTRL(port));
754 		ctl = intr | readl(port->membase + UART_INTR(port));
755 		writel(ctl, port->membase + UART_INTR(port));
775 	if (!port->mapbase || !port->membase) {
828 	mvuart->pm_regs.rbr = readl(port->membase + UART_RBR(port));
829 	mvuart->pm_regs.tsh = readl(port->membase + UART_TSH(port));
830 	mvuart->pm_regs.ctrl = readl(port->membase + UART_CTRL(port));
831 	mvuart->pm_regs.intr = readl(port->membase + UART_INTR(port));
832 	mvuart->pm_regs.stat = readl(port->membase + UART_STAT);
834 	mvuart->pm_regs.brdv = readl(port->membase + UART_BRDV);
836 	mvuart->pm_regs.osamp = readl(port->membase + UART_OSAMP);
849 	writel(mvuart->pm_regs.rbr, port->membase + UART_RBR(port));
850 	writel(mvuart->pm_regs.tsh, port->membase + UART_TSH(port));
851 	writel(mvuart->pm_regs.ctrl, port->membase + UART_CTRL(port));
852 	writel(mvuart->pm_regs.intr, port->membase + UART_INTR(port));
853 	writel(mvuart->pm_regs.stat, port->membase + UART_STAT);
855 	writel(mvuart->pm_regs.brdv, port->membase + UART_BRDV);
857 	writel(mvuart->pm_regs.osamp, port->membase + UART_OSAMP);
919 	port->membase = devm_platform_get_and_ioremap_resource(pdev, 0, &reg);
920 	if (IS_ERR(port->membase))
921 		return PTR_ERR(port->membase);
979 	writel(CTRL_SOFT_RST, port->membase + UART_CTRL(port));
981 	writel(0, port->membase + UART_CTRL(port));