tty/serial/lantiq.c

144 	u32 fstat = __raw_readl(port->membase + LTQ_ASC_FSTAT);
159 		writeb(ch, port->membase + LTQ_ASC_TBUF));
167 	__raw_writel(ASCWHBSTATE_CLRREN, port->membase + LTQ_ASC_WHBSTATE);
176 	fifocnt = __raw_readl(port->membase + LTQ_ASC_FSTAT) &
180 		ch = readb(port->membase + LTQ_ASC_RBUF);
181 		rsr = (__raw_readl(port->membase + LTQ_ASC_STATE)
194 					port->membase + LTQ_ASC_WHBSTATE);
198 					port->membase + LTQ_ASC_WHBSTATE);
203 					port->membase + LTQ_ASC_WHBSTATE);
240 	__raw_writel(ASC_IRNCR_TIR, port->membase + LTQ_ASC_IRNCR);
254 	__raw_writel(ASC_IRNCR_EIR, port->membase + LTQ_ASC_IRNCR);
257 		ASCWHBSTATE_CLRROE, port->membase + LTQ_ASC_WHBSTATE);
270 	__raw_writel(ASC_IRNCR_RIR, port->membase + LTQ_ASC_IRNCR);
284 	stat = readl(port->membase + LTQ_ASC_IRNCR);
305 	status = __raw_readl(port->membase + LTQ_ASC_FSTAT) &
339 		port->membase + LTQ_ASC_CLC);
341 	__raw_writel(0, port->membase + LTQ_ASC_PISEL);
345 		port->membase + LTQ_ASC_TXFCON);
349 		port->membase + LTQ_ASC_RXFCON);
355 		ASCCON_ROEN, port->membase + LTQ_ASC_CON);
364 		port->membase + LTQ_ASC_IRNREN);
377 	__raw_writel(0, port->membase + LTQ_ASC_CON);
379 		port->membase + LTQ_ASC_RXFCON);
381 		port->membase + LTQ_ASC_TXFCON);
454 	asc_update_bits(0, con, port->membase + LTQ_ASC_CON);
462 	asc_update_bits(ASCCON_R, 0, port->membase + LTQ_ASC_CON);
465 	asc_update_bits(ASCCON_FDE, 0, port->membase + LTQ_ASC_CON);
468 	asc_update_bits(ASCCON_BRS, 0, port->membase + LTQ_ASC_CON);
471 	__raw_writel(divisor, port->membase + LTQ_ASC_BG);
474 	asc_update_bits(0, ASCCON_R, port->membase + LTQ_ASC_CON);
477 	__raw_writel(ASCWHBSTATE_SETREN, port->membase + LTQ_ASC_WHBSTATE);
503 		devm_iounmap(&pdev->dev, port->membase);
504 		port->membase = NULL;
530 		port->membase = devm_ioremap(&pdev->dev,
532 		if (port->membase == NULL)
583 	if (!port->membase)
589 	writeb(ch, port->membase + LTQ_ASC_TBUF);
676 	if (!device->port.membase)