tty/serial/meson_uart.c

102 	val = readl(port->membase + AML_UART_STATUS);
111 	val = readl(port->membase + AML_UART_CONTROL);
113 	writel(val, port->membase + AML_UART_CONTROL);
120 	val = readl(port->membase + AML_UART_CONTROL);
122 	writel(val, port->membase + AML_UART_CONTROL);
134 	val = readl(port->membase + AML_UART_CONTROL);
137 	writel(val, port->membase + AML_UART_CONTROL);
153 	while (!(readl(port->membase + AML_UART_STATUS) & AML_UART_TX_FULL)) {
155 			writel(port->x_char, port->membase + AML_UART_WFIFO);
164 		writel(ch, port->membase + AML_UART_WFIFO);
168 		val = readl(port->membase + AML_UART_CONTROL);
170 		writel(val, port->membase + AML_UART_CONTROL);
186 		ostatus = status = readl(port->membase + AML_UART_STATUS);
196 			mode = readl(port->membase + AML_UART_CONTROL);
198 			writel(mode, port->membase + AML_UART_CONTROL);
202 			writel(mode, port->membase + AML_UART_CONTROL);
211 		ch = readl(port->membase + AML_UART_RFIFO);
230 	} while (!(readl(port->membase + AML_UART_STATUS) & AML_UART_RX_EMPTY));
241 	if (!(readl(port->membase + AML_UART_STATUS) & AML_UART_RX_EMPTY))
244 	if (!(readl(port->membase + AML_UART_STATUS) & AML_UART_TX_FULL)) {
245 		if (readl(port->membase + AML_UART_CONTROL) & AML_UART_TX_INT_EN)
271 	val = readl(port->membase + AML_UART_CONTROL);
273 	writel(val, port->membase + AML_UART_CONTROL);
276 	writel(val, port->membase + AML_UART_CONTROL);
287 	val = readl(port->membase + AML_UART_CONTROL);
289 	writel(val, port->membase + AML_UART_CONTROL);
291 	writel(val, port->membase + AML_UART_CONTROL);
294 	writel(val, port->membase + AML_UART_CONTROL);
297 	writel(val, port->membase + AML_UART_CONTROL);
300 	writel(val, port->membase + AML_UART_MISC);
331 	writel(val, port->membase + AML_UART_REG5);
347 	val = readl(port->membase + AML_UART_CONTROL);
390 	writel(val, port->membase + AML_UART_CONTROL);
425 	devm_iounmap(port->dev, port->membase);
426 	port->membase = NULL;
438 	port->membase = devm_ioremap(port->dev, port->mapbase,
440 	if (!port->membase)
467 	if (readl(port->membase + AML_UART_STATUS) & AML_UART_RX_EMPTY)
470 		c = readl(port->membase + AML_UART_RFIFO);
486 	ret = readl_poll_timeout_atomic(port->membase + AML_UART_STATUS, reg,
496 	writel(c, port->membase + AML_UART_WFIFO);
499 	ret = readl_poll_timeout_atomic(port->membase + AML_UART_STATUS, reg,
538 	val = readl(port->membase + AML_UART_CONTROL);
540 	writel(val, port->membase + AML_UART_CONTROL);
545 	if (!port->membase)
548 	while (readl(port->membase + AML_UART_STATUS) & AML_UART_TX_FULL)
550 	writel(ch, port->membase + AML_UART_WFIFO);
565 	val = readl(port->membase + AML_UART_CONTROL);
567 	writel(tmp, port->membase + AML_UART_CONTROL);
570 	writel(val, port->membase + AML_UART_CONTROL);
600 	if (!port || !port->membase)
637 	if (!device->port.membase)