i2c/busses/i2c-uniphier-f.c

81 	void __iomem *membase;
109 		writel(*priv->buf++, priv->membase + UNIPHIER_FI2C_DTTX);
123 		*priv->buf++ = readl(priv->membase + UNIPHIER_FI2C_DTRX);
130 	writel(priv->enabled_irqs, priv->membase + UNIPHIER_FI2C_IE);
136 	writel(mask, priv->membase + UNIPHIER_FI2C_IC);
144 	       priv->membase + UNIPHIER_FI2C_CR);
154 	irq_status = readl(priv->membase + UNIPHIER_FI2C_INT);
213 				       priv->membase + UNIPHIER_FI2C_CR);
254 	writel(0, priv->membase + UNIPHIER_FI2C_TBC);
257 	       priv->membase + UNIPHIER_FI2C_DTTX);
275 		writel(priv->len, priv->membase + UNIPHIER_FI2C_RBC);
284 		writel(0, priv->membase + UNIPHIER_FI2C_RBC);
293 	       priv->membase + UNIPHIER_FI2C_DTTX);
298 	writel(UNIPHIER_FI2C_RST_RST, priv->membase + UNIPHIER_FI2C_RST);
304 	       priv->membase + UNIPHIER_FI2C_BRST);
333 	       priv->membase + UNIPHIER_FI2C_RST);	/* reset TX/RX FIFO */
349 		       priv->membase + UNIPHIER_FI2C_CR);
369 		ret = readl_poll_timeout(priv->membase + UNIPHIER_FI2C_SR,
389 	if (readl(priv->membase + UNIPHIER_FI2C_SR) & UNIPHIER_FI2C_SR_DB) {
445 	return !!(readl(priv->membase + UNIPHIER_FI2C_BM) &
454 	       priv->membase + UNIPHIER_FI2C_BRST);
461 	return !!(readl(priv->membase + UNIPHIER_FI2C_BM) &
483 	tmp = readl(priv->membase + UNIPHIER_FI2C_CR);
485 	writel(tmp, priv->membase + UNIPHIER_FI2C_CR);
493 	writel(cyc, priv->membase + UNIPHIER_FI2C_CYC);
499 	writel(cyc * 5 / 9, priv->membase + UNIPHIER_FI2C_LCTL);
504 	writel(cyc / 2, priv->membase + UNIPHIER_FI2C_SSUT);
509 	writel(cyc / 16, priv->membase + UNIPHIER_FI2C_DSUT);
526 	priv->membase = devm_platform_ioremap_resource(pdev, 0);
527 	if (IS_ERR(priv->membase))
528 		return PTR_ERR(priv->membase);