Searched refs:hwpwm (Results 26 - 49 of 49) sorted by relevance

12

/linux-master/drivers/pwm/
H A Dpwm-keembay.c102 highlow = readl(priv->base + KMB_PWM_LEADIN_OFFSET(pwm->hwpwm));
109 highlow = readl(priv->base + KMB_PWM_HIGHLOW_OFFSET(pwm->hwpwm));
137 KMB_PWM_LEADIN_OFFSET(pwm->hwpwm));
143 keembay_pwm_disable(priv, pwm->hwpwm);
171 writel(pwm_count, priv->base + KMB_PWM_HIGHLOW_OFFSET(pwm->hwpwm));
174 keembay_pwm_enable(priv, pwm->hwpwm);
H A Dpwm-fsl-ftm.c94 regmap_set_bits(fpc->regmap, FTM_SC, BIT(pwm->hwpwm + 16));
107 regmap_clear_bits(fpc->regmap, FTM_SC, BIT(pwm->hwpwm + 16));
217 if (~(val | BIT(pwm->hwpwm)) & 0xFF)
251 pwm->hwpwm);
281 regmap_write(fpc->regmap, FTM_CSC(pwm->hwpwm),
283 regmap_write(fpc->regmap, FTM_CV(pwm->hwpwm), duty);
287 reg_polarity = BIT(pwm->hwpwm);
289 regmap_update_bits(fpc->regmap, FTM_POL, BIT(pwm->hwpwm), reg_polarity);
317 BIT(pwm->hwpwm));
341 regmap_clear_bits(fpc->regmap, FTM_OUTMASK, BIT(pwm->hwpwm));
[all...]
H A Dpwm-stm32.c107 dma_id = pwm->hwpwm < 2 ? STM32_TIMERS_DMA_CH1 : STM32_TIMERS_DMA_CH3;
108 ccen = pwm->hwpwm < 2 ? TIM_CCER_CC12E : TIM_CCER_CC34E;
109 ccr = pwm->hwpwm < 2 ? TIM_CCR1 : TIM_CCR3;
201 pwm->hwpwm < 2 ? TIM_CCMR1 : TIM_CCMR2,
202 TIM_CCMR_CC1S | TIM_CCMR_CC2S, pwm->hwpwm & 0x1 ?
207 regmap_update_bits(priv->regmap, TIM_CCER, pwm->hwpwm < 2 ?
208 TIM_CCER_CC12P : TIM_CCER_CC34P, pwm->hwpwm < 2 ?
255 pwm->hwpwm < 2 ? TIM_CCMR1 : TIM_CCMR2,
301 regmap_write(priv->regmap, pwm->hwpwm < 2 ? TIM_CCMR1 : TIM_CCMR2, 0);
442 stm32_pwm_disable(priv, pwm->hwpwm);
[all...]
H A Dpwm-pca9685.c386 pca9685_pwm_set_duty(chip, pwm->hwpwm, 0);
392 if (!pca9685_prescaler_can_change(pca, pwm->hwpwm)) {
416 pca9685_pwm_set_duty(chip, pwm->hwpwm, duty);
430 set_bit(pwm->hwpwm, pca->pwms_enabled);
432 clear_bit(pwm->hwpwm, pca->pwms_enabled);
458 if (pwm->hwpwm >= PCA9685_MAXCHAN) {
469 duty = pca9685_pwm_get_duty(chip, pwm->hwpwm);
479 if (pca9685_pwm_test_and_set_inuse(pca, pwm->hwpwm))
482 if (pwm->hwpwm < PCA9685_MAXCHAN) {
485 set_bit(pwm->hwpwm, pc
[all...]
H A Dpwm-imx-tpm.c149 tmp = readl(tpm->base + PWM_IMX_TPM_CnV(pwm->hwpwm));
154 val = readl(tpm->base + PWM_IMX_TPM_CnSC(pwm->hwpwm));
232 writel(p->val, tpm->base + PWM_IMX_TPM_CnV(pwm->hwpwm));
241 || readl(tpm->base + PWM_IMX_TPM_CnV(pwm->hwpwm))
255 val = readl(tpm->base + PWM_IMX_TPM_CnSC(pwm->hwpwm));
271 writel(val, tpm->base + PWM_IMX_TPM_CnSC(pwm->hwpwm));
H A Dpwm-renesas-tpu.c217 if (pwm->hwpwm >= TPU_CHANNEL_MAX)
220 tpd = &tpu->tpd[pwm->hwpwm];
223 tpd->channel = pwm->hwpwm;
237 struct tpu_pwm_device *tpd = &tpu->tpd[pwm->hwpwm];
246 struct tpu_pwm_device *tpd = &tpu->tpd[pwm->hwpwm];
355 struct tpu_pwm_device *tpd = &tpu->tpd[pwm->hwpwm];
365 struct tpu_pwm_device *tpd = &tpu->tpd[pwm->hwpwm];
388 struct tpu_pwm_device *tpd = &tpu->tpd[pwm->hwpwm];
H A Dpwm-cros-ec.c138 struct cros_ec_pwm *channel = &ec_pwm->channel[pwm->hwpwm];
155 ret = cros_ec_pwm_set_duty(ec_pwm, pwm->hwpwm, duty_cycle);
168 struct cros_ec_pwm *channel = &ec_pwm->channel[pwm->hwpwm];
171 ret = cros_ec_pwm_get_duty(ec_pwm->ec, ec_pwm->use_pwm_type, pwm->hwpwm);
H A Dpwm-meson.c122 struct meson_pwm_channel *channel = &meson->channels[pwm->hwpwm];
139 struct meson_pwm_channel *channel = &meson->channels[pwm->hwpwm];
148 struct meson_pwm_channel *channel = &meson->channels[pwm->hwpwm];
208 struct meson_pwm_channel *channel = &meson->channels[pwm->hwpwm];
214 channel_data = &meson_pwm_per_channel_data[pwm->hwpwm];
242 value &= ~meson_pwm_per_channel_data[pwm->hwpwm].pwm_en_mask;
252 struct meson_pwm_channel *channel = &meson->channels[pwm->hwpwm];
296 channel = &meson->channels[pwm->hwpwm];
316 channel = &meson->channels[pwm->hwpwm];
317 channel_data = &meson_pwm_per_channel_data[pwm->hwpwm];
[all...]
H A Dpwm-atmel-tcb.c72 struct atmel_tcb_pwm_device *tcbpwm = &tcbpwmc->pwms[pwm->hwpwm];
91 if (pwm->hwpwm == 0)
126 struct atmel_tcb_pwm_device *tcbpwm = &tcbpwmc->pwms[pwm->hwpwm];
144 if (pwm->hwpwm == 0) {
183 struct atmel_tcb_pwm_device *tcbpwm = &tcbpwmc->pwms[pwm->hwpwm];
203 if (pwm->hwpwm == 0) {
226 if (pwm->hwpwm == 0) {
243 if (pwm->hwpwm == 0)
267 struct atmel_tcb_pwm_device *tcbpwm = &tcbpwmc->pwms[pwm->hwpwm];
313 if (pwm->hwpwm
[all...]
H A Dpwm-tegra.c200 pwm_writel(pc, pwm->hwpwm, val);
221 val = pwm_readl(pc, pwm->hwpwm);
223 pwm_writel(pc, pwm->hwpwm, val);
233 val = pwm_readl(pc, pwm->hwpwm);
235 pwm_writel(pc, pwm->hwpwm, val);
H A Dpwm-img.c133 val &= ~(PWM_CTRL_CFG_DIV_MASK << PWM_CTRL_CFG_DIV_SHIFT(pwm->hwpwm));
135 PWM_CTRL_CFG_DIV_SHIFT(pwm->hwpwm);
140 img_pwm_writel(imgchip, PWM_CH_CFG(pwm->hwpwm), val);
159 val |= BIT(pwm->hwpwm);
164 PERIP_PWM_PDM_CONTROL_CH_SHIFT(pwm->hwpwm));
175 val &= ~BIT(pwm->hwpwm);
H A Dpwm-tiehrpwm.c255 if (i == pwm->hwpwm)
265 pc->period_cycles[pwm->hwpwm] = period_cycles;
292 if (pwm->hwpwm == 1)
313 pc->polarity[pwm->hwpwm] = polarity;
328 if (pwm->hwpwm) {
343 configure_polarity(pc, pwm->hwpwm);
362 if (pwm->hwpwm) {
400 pc->period_cycles[pwm->hwpwm] = 0;
H A Dpwm-brcmstb.c100 unsigned int channel = pwm->hwpwm;
205 brcmstb_pwm_enable_set(p, pwm->hwpwm, false);
215 brcmstb_pwm_enable_set(p, pwm->hwpwm, true);
H A Dpwm-lpss.c78 return readl(lpwm->regs + pwm->hwpwm * PWM_SIZE + PWM);
85 writel(value, lpwm->regs + pwm->hwpwm * PWM_SIZE + PWM);
91 const void __iomem *addr = lpwm->regs + pwm->hwpwm * PWM_SIZE + PWM;
H A Dpwm-twl-led.c96 base = pwm->hwpwm * 2 + TWL4030_PWMA_REG;
120 val |= TWL4030_LED_TOGGLE(pwm->hwpwm, TWL4030_LED_PINS);
145 val &= ~TWL4030_LED_TOGGLE(pwm->hwpwm, TWL4030_LED_PINS);
H A Dpwm-bcm-kona.c106 unsigned int value, chan = pwm->hwpwm;
160 unsigned int chan = pwm->hwpwm;
205 unsigned int chan = pwm->hwpwm;
H A Dpwm-clps711x.c44 u32 shift = (pwm->hwpwm + 1) * 4;
H A Dpwm-pxa.c75 offset = pwm->hwpwm ? 0x10 : 0;
H A Dpwm-sifive.c115 duty = readl(ddata->regs + PWM_SIFIVE_PWMCMP(pwm->hwpwm));
193 writel(frac, ddata->regs + PWM_SIFIVE_PWMCMP(pwm->hwpwm));
H A Dcore.c588 pwm->hwpwm = i;
/linux-master/drivers/hwmon/
H A Daspeed-g6-pwm-tach.c154 u32 hwpwm = pwm->hwpwm; local
159 val = readl(priv->base + PWM_ASPEED_CTRL(hwpwm));
165 val = readl(priv->base + PWM_ASPEED_DUTY_CYCLE(hwpwm));
192 u32 hwpwm = pwm->hwpwm, duty_pt, val; local
234 val = readl(priv->base + PWM_ASPEED_DUTY_CYCLE(hwpwm));
238 writel(val, priv->base + PWM_ASPEED_DUTY_CYCLE(hwpwm));
247 val = readl(priv->base + PWM_ASPEED_DUTY_CYCLE(hwpwm));
251 writel(val, priv->base + PWM_ASPEED_DUTY_CYCLE(hwpwm));
[all...]
/linux-master/include/linux/
H A Dpwm.h71 * @hwpwm: per-chip relative index of the PWM device
80 unsigned int hwpwm; member in struct:pwm_device
/linux-master/drivers/gpio/
H A Dgpio-mvebu.c634 pwm->hwpwm, "mvebu-pwm",
745 mvebu_gpio_blink(&mvchip->chip, pwm->hwpwm, 1);
747 mvebu_gpio_blink(&mvchip->chip, pwm->hwpwm, 0);
/linux-master/drivers/leds/rgb/
H A Dleds-qcom-lpg.c1208 struct lpg_channel *chan = &lpg->channels[pwm->hwpwm];
1224 struct lpg_channel *chan = &lpg->channels[pwm->hwpwm];
1255 struct lpg_channel *chan = &lpg->channels[pwm->hwpwm];

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