1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) Overkiz SAS 2012
4 *
5 * Author: Boris BREZILLON <b.brezillon@overkiz.com>
6 */
7
8#include <linux/module.h>
9#include <linux/init.h>
10#include <linux/clocksource.h>
11#include <linux/clockchips.h>
12#include <linux/interrupt.h>
13#include <linux/irq.h>
14
15#include <linux/clk.h>
16#include <linux/err.h>
17#include <linux/ioport.h>
18#include <linux/io.h>
19#include <linux/mfd/syscon.h>
20#include <linux/platform_device.h>
21#include <linux/pwm.h>
22#include <linux/of.h>
23#include <linux/regmap.h>
24#include <linux/slab.h>
25#include <soc/at91/atmel_tcb.h>
26
27#define NPWM	2
28
29#define ATMEL_TC_ACMR_MASK	(ATMEL_TC_ACPA | ATMEL_TC_ACPC |	\
30				 ATMEL_TC_AEEVT | ATMEL_TC_ASWTRG)
31
32#define ATMEL_TC_BCMR_MASK	(ATMEL_TC_BCPB | ATMEL_TC_BCPC |	\
33				 ATMEL_TC_BEEVT | ATMEL_TC_BSWTRG)
34
35struct atmel_tcb_pwm_device {
36	unsigned div;			/* PWM clock divider */
37	unsigned duty;			/* PWM duty expressed in clk cycles */
38	unsigned period;		/* PWM period expressed in clk cycles */
39};
40
41struct atmel_tcb_channel {
42	u32 enabled;
43	u32 cmr;
44	u32 ra;
45	u32 rb;
46	u32 rc;
47};
48
49struct atmel_tcb_pwm_chip {
50	spinlock_t lock;
51	u8 channel;
52	u8 width;
53	struct regmap *regmap;
54	struct clk *clk;
55	struct clk *gclk;
56	struct clk *slow_clk;
57	struct atmel_tcb_pwm_device pwms[NPWM];
58	struct atmel_tcb_channel bkup;
59};
60
61static const u8 atmel_tcb_divisors[] = { 2, 8, 32, 128, 0, };
62
63static inline struct atmel_tcb_pwm_chip *to_tcb_chip(struct pwm_chip *chip)
64{
65	return pwmchip_get_drvdata(chip);
66}
67
68static int atmel_tcb_pwm_request(struct pwm_chip *chip,
69				 struct pwm_device *pwm)
70{
71	struct atmel_tcb_pwm_chip *tcbpwmc = to_tcb_chip(chip);
72	struct atmel_tcb_pwm_device *tcbpwm = &tcbpwmc->pwms[pwm->hwpwm];
73	unsigned cmr;
74	int ret;
75
76	ret = clk_prepare_enable(tcbpwmc->clk);
77	if (ret)
78		return ret;
79
80	tcbpwm->duty = 0;
81	tcbpwm->period = 0;
82	tcbpwm->div = 0;
83
84	spin_lock(&tcbpwmc->lock);
85	regmap_read(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, CMR), &cmr);
86	/*
87	 * Get init config from Timer Counter registers if
88	 * Timer Counter is already configured as a PWM generator.
89	 */
90	if (cmr & ATMEL_TC_WAVE) {
91		if (pwm->hwpwm == 0)
92			regmap_read(tcbpwmc->regmap,
93				    ATMEL_TC_REG(tcbpwmc->channel, RA),
94				    &tcbpwm->duty);
95		else
96			regmap_read(tcbpwmc->regmap,
97				    ATMEL_TC_REG(tcbpwmc->channel, RB),
98				    &tcbpwm->duty);
99
100		tcbpwm->div = cmr & ATMEL_TC_TCCLKS;
101		regmap_read(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, RC),
102			    &tcbpwm->period);
103		cmr &= (ATMEL_TC_TCCLKS | ATMEL_TC_ACMR_MASK |
104			ATMEL_TC_BCMR_MASK);
105	} else
106		cmr = 0;
107
108	cmr |= ATMEL_TC_WAVE | ATMEL_TC_WAVESEL_UP_AUTO | ATMEL_TC_EEVT_XC0;
109	regmap_write(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, CMR), cmr);
110	spin_unlock(&tcbpwmc->lock);
111
112	return 0;
113}
114
115static void atmel_tcb_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
116{
117	struct atmel_tcb_pwm_chip *tcbpwmc = to_tcb_chip(chip);
118
119	clk_disable_unprepare(tcbpwmc->clk);
120}
121
122static void atmel_tcb_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm,
123				  enum pwm_polarity polarity)
124{
125	struct atmel_tcb_pwm_chip *tcbpwmc = to_tcb_chip(chip);
126	struct atmel_tcb_pwm_device *tcbpwm = &tcbpwmc->pwms[pwm->hwpwm];
127	unsigned cmr;
128
129	/*
130	 * If duty is 0 the timer will be stopped and we have to
131	 * configure the output correctly on software trigger:
132	 *  - set output to high if PWM_POLARITY_INVERSED
133	 *  - set output to low if PWM_POLARITY_NORMAL
134	 *
135	 * This is why we're reverting polarity in this case.
136	 */
137	if (tcbpwm->duty == 0)
138		polarity = !polarity;
139
140	spin_lock(&tcbpwmc->lock);
141	regmap_read(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, CMR), &cmr);
142
143	/* flush old setting and set the new one */
144	if (pwm->hwpwm == 0) {
145		cmr &= ~ATMEL_TC_ACMR_MASK;
146		if (polarity == PWM_POLARITY_INVERSED)
147			cmr |= ATMEL_TC_ASWTRG_CLEAR;
148		else
149			cmr |= ATMEL_TC_ASWTRG_SET;
150	} else {
151		cmr &= ~ATMEL_TC_BCMR_MASK;
152		if (polarity == PWM_POLARITY_INVERSED)
153			cmr |= ATMEL_TC_BSWTRG_CLEAR;
154		else
155			cmr |= ATMEL_TC_BSWTRG_SET;
156	}
157
158	regmap_write(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, CMR), cmr);
159
160	/*
161	 * Use software trigger to apply the new setting.
162	 * If both PWM devices in this group are disabled we stop the clock.
163	 */
164	if (!(cmr & (ATMEL_TC_ACPC | ATMEL_TC_BCPC))) {
165		regmap_write(tcbpwmc->regmap,
166			     ATMEL_TC_REG(tcbpwmc->channel, CCR),
167			     ATMEL_TC_SWTRG | ATMEL_TC_CLKDIS);
168		tcbpwmc->bkup.enabled = 1;
169	} else {
170		regmap_write(tcbpwmc->regmap,
171			     ATMEL_TC_REG(tcbpwmc->channel, CCR),
172			     ATMEL_TC_SWTRG);
173		tcbpwmc->bkup.enabled = 0;
174	}
175
176	spin_unlock(&tcbpwmc->lock);
177}
178
179static int atmel_tcb_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm,
180				enum pwm_polarity polarity)
181{
182	struct atmel_tcb_pwm_chip *tcbpwmc = to_tcb_chip(chip);
183	struct atmel_tcb_pwm_device *tcbpwm = &tcbpwmc->pwms[pwm->hwpwm];
184	u32 cmr;
185
186	/*
187	 * If duty is 0 the timer will be stopped and we have to
188	 * configure the output correctly on software trigger:
189	 *  - set output to high if PWM_POLARITY_INVERSED
190	 *  - set output to low if PWM_POLARITY_NORMAL
191	 *
192	 * This is why we're reverting polarity in this case.
193	 */
194	if (tcbpwm->duty == 0)
195		polarity = !polarity;
196
197	spin_lock(&tcbpwmc->lock);
198	regmap_read(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, CMR), &cmr);
199
200	/* flush old setting and set the new one */
201	cmr &= ~ATMEL_TC_TCCLKS;
202
203	if (pwm->hwpwm == 0) {
204		cmr &= ~ATMEL_TC_ACMR_MASK;
205
206		/* Set CMR flags according to given polarity */
207		if (polarity == PWM_POLARITY_INVERSED)
208			cmr |= ATMEL_TC_ASWTRG_CLEAR;
209		else
210			cmr |= ATMEL_TC_ASWTRG_SET;
211	} else {
212		cmr &= ~ATMEL_TC_BCMR_MASK;
213		if (polarity == PWM_POLARITY_INVERSED)
214			cmr |= ATMEL_TC_BSWTRG_CLEAR;
215		else
216			cmr |= ATMEL_TC_BSWTRG_SET;
217	}
218
219	/*
220	 * If duty is 0 or equal to period there's no need to register
221	 * a specific action on RA/RB and RC compare.
222	 * The output will be configured on software trigger and keep
223	 * this config till next config call.
224	 */
225	if (tcbpwm->duty != tcbpwm->period && tcbpwm->duty > 0) {
226		if (pwm->hwpwm == 0) {
227			if (polarity == PWM_POLARITY_INVERSED)
228				cmr |= ATMEL_TC_ACPA_SET | ATMEL_TC_ACPC_CLEAR;
229			else
230				cmr |= ATMEL_TC_ACPA_CLEAR | ATMEL_TC_ACPC_SET;
231		} else {
232			if (polarity == PWM_POLARITY_INVERSED)
233				cmr |= ATMEL_TC_BCPB_SET | ATMEL_TC_BCPC_CLEAR;
234			else
235				cmr |= ATMEL_TC_BCPB_CLEAR | ATMEL_TC_BCPC_SET;
236		}
237	}
238
239	cmr |= (tcbpwm->div & ATMEL_TC_TCCLKS);
240
241	regmap_write(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, CMR), cmr);
242
243	if (pwm->hwpwm == 0)
244		regmap_write(tcbpwmc->regmap,
245			     ATMEL_TC_REG(tcbpwmc->channel, RA),
246			     tcbpwm->duty);
247	else
248		regmap_write(tcbpwmc->regmap,
249			     ATMEL_TC_REG(tcbpwmc->channel, RB),
250			     tcbpwm->duty);
251
252	regmap_write(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, RC),
253		     tcbpwm->period);
254
255	/* Use software trigger to apply the new setting */
256	regmap_write(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, CCR),
257		     ATMEL_TC_SWTRG | ATMEL_TC_CLKEN);
258	tcbpwmc->bkup.enabled = 1;
259	spin_unlock(&tcbpwmc->lock);
260	return 0;
261}
262
263static int atmel_tcb_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
264				int duty_ns, int period_ns)
265{
266	struct atmel_tcb_pwm_chip *tcbpwmc = to_tcb_chip(chip);
267	struct atmel_tcb_pwm_device *tcbpwm = &tcbpwmc->pwms[pwm->hwpwm];
268	struct atmel_tcb_pwm_device *atcbpwm = NULL;
269	int i = 0;
270	int slowclk = 0;
271	unsigned period;
272	unsigned duty;
273	unsigned rate = clk_get_rate(tcbpwmc->clk);
274	unsigned long long min;
275	unsigned long long max;
276
277	/*
278	 * Find best clk divisor:
279	 * the smallest divisor which can fulfill the period_ns requirements.
280	 * If there is a gclk, the first divisor is actually the gclk selector
281	 */
282	if (tcbpwmc->gclk)
283		i = 1;
284	for (; i < ARRAY_SIZE(atmel_tcb_divisors); ++i) {
285		if (atmel_tcb_divisors[i] == 0) {
286			slowclk = i;
287			continue;
288		}
289		min = div_u64((u64)NSEC_PER_SEC * atmel_tcb_divisors[i], rate);
290		max = min << tcbpwmc->width;
291		if (max >= period_ns)
292			break;
293	}
294
295	/*
296	 * If none of the divisor are small enough to represent period_ns
297	 * take slow clock (32KHz).
298	 */
299	if (i == ARRAY_SIZE(atmel_tcb_divisors)) {
300		i = slowclk;
301		rate = clk_get_rate(tcbpwmc->slow_clk);
302		min = div_u64(NSEC_PER_SEC, rate);
303		max = min << tcbpwmc->width;
304
305		/* If period is too big return ERANGE error */
306		if (max < period_ns)
307			return -ERANGE;
308	}
309
310	duty = div_u64(duty_ns, min);
311	period = div_u64(period_ns, min);
312
313	if (pwm->hwpwm == 0)
314		atcbpwm = &tcbpwmc->pwms[1];
315	else
316		atcbpwm = &tcbpwmc->pwms[0];
317
318	/*
319	 * PWM devices provided by the TCB driver are grouped by 2.
320	 * PWM devices in a given group must be configured with the
321	 * same period_ns.
322	 *
323	 * We're checking the period value of the second PWM device
324	 * in this group before applying the new config.
325	 */
326	if ((atcbpwm && atcbpwm->duty > 0 &&
327			atcbpwm->duty != atcbpwm->period) &&
328		(atcbpwm->div != i || atcbpwm->period != period)) {
329		dev_err(pwmchip_parent(chip),
330			"failed to configure period_ns: PWM group already configured with a different value\n");
331		return -EINVAL;
332	}
333
334	tcbpwm->period = period;
335	tcbpwm->div = i;
336	tcbpwm->duty = duty;
337
338	return 0;
339}
340
341static int atmel_tcb_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
342			       const struct pwm_state *state)
343{
344	int duty_cycle, period;
345	int ret;
346
347	if (!state->enabled) {
348		atmel_tcb_pwm_disable(chip, pwm, state->polarity);
349		return 0;
350	}
351
352	period = state->period < INT_MAX ? state->period : INT_MAX;
353	duty_cycle = state->duty_cycle < INT_MAX ? state->duty_cycle : INT_MAX;
354
355	ret = atmel_tcb_pwm_config(chip, pwm, duty_cycle, period);
356	if (ret)
357		return ret;
358
359	return atmel_tcb_pwm_enable(chip, pwm, state->polarity);
360}
361
362static const struct pwm_ops atmel_tcb_pwm_ops = {
363	.request = atmel_tcb_pwm_request,
364	.free = atmel_tcb_pwm_free,
365	.apply = atmel_tcb_pwm_apply,
366};
367
368static struct atmel_tcb_config tcb_rm9200_config = {
369	.counter_width = 16,
370};
371
372static struct atmel_tcb_config tcb_sam9x5_config = {
373	.counter_width = 32,
374};
375
376static struct atmel_tcb_config tcb_sama5d2_config = {
377	.counter_width = 32,
378	.has_gclk = 1,
379};
380
381static const struct of_device_id atmel_tcb_of_match[] = {
382	{ .compatible = "atmel,at91rm9200-tcb", .data = &tcb_rm9200_config, },
383	{ .compatible = "atmel,at91sam9x5-tcb", .data = &tcb_sam9x5_config, },
384	{ .compatible = "atmel,sama5d2-tcb", .data = &tcb_sama5d2_config, },
385	{ /* sentinel */ }
386};
387
388static int atmel_tcb_pwm_probe(struct platform_device *pdev)
389{
390	struct pwm_chip *chip;
391	const struct of_device_id *match;
392	struct atmel_tcb_pwm_chip *tcbpwm;
393	const struct atmel_tcb_config *config;
394	struct device_node *np = pdev->dev.of_node;
395	char clk_name[] = "t0_clk";
396	int err;
397	int channel;
398
399	chip = devm_pwmchip_alloc(&pdev->dev, NPWM, sizeof(*tcbpwm));
400	if (IS_ERR(chip))
401		return PTR_ERR(chip);
402	tcbpwm = to_tcb_chip(chip);
403
404	err = of_property_read_u32(np, "reg", &channel);
405	if (err < 0) {
406		dev_err(&pdev->dev,
407			"failed to get Timer Counter Block channel from device tree (error: %d)\n",
408			err);
409		return err;
410	}
411
412	tcbpwm->regmap = syscon_node_to_regmap(np->parent);
413	if (IS_ERR(tcbpwm->regmap))
414		return PTR_ERR(tcbpwm->regmap);
415
416	tcbpwm->slow_clk = of_clk_get_by_name(np->parent, "slow_clk");
417	if (IS_ERR(tcbpwm->slow_clk))
418		return PTR_ERR(tcbpwm->slow_clk);
419
420	clk_name[1] += channel;
421	tcbpwm->clk = of_clk_get_by_name(np->parent, clk_name);
422	if (IS_ERR(tcbpwm->clk))
423		tcbpwm->clk = of_clk_get_by_name(np->parent, "t0_clk");
424	if (IS_ERR(tcbpwm->clk)) {
425		err = PTR_ERR(tcbpwm->clk);
426		goto err_slow_clk;
427	}
428
429	match = of_match_node(atmel_tcb_of_match, np->parent);
430	config = match->data;
431
432	if (config->has_gclk) {
433		tcbpwm->gclk = of_clk_get_by_name(np->parent, "gclk");
434		if (IS_ERR(tcbpwm->gclk)) {
435			err = PTR_ERR(tcbpwm->gclk);
436			goto err_clk;
437		}
438	}
439
440	chip->ops = &atmel_tcb_pwm_ops;
441	tcbpwm->channel = channel;
442	tcbpwm->width = config->counter_width;
443
444	err = clk_prepare_enable(tcbpwm->slow_clk);
445	if (err)
446		goto err_gclk;
447
448	spin_lock_init(&tcbpwm->lock);
449
450	err = pwmchip_add(chip);
451	if (err < 0)
452		goto err_disable_clk;
453
454	platform_set_drvdata(pdev, chip);
455
456	return 0;
457
458err_disable_clk:
459	clk_disable_unprepare(tcbpwm->slow_clk);
460
461err_gclk:
462	clk_put(tcbpwm->gclk);
463
464err_clk:
465	clk_put(tcbpwm->clk);
466
467err_slow_clk:
468	clk_put(tcbpwm->slow_clk);
469
470	return err;
471}
472
473static void atmel_tcb_pwm_remove(struct platform_device *pdev)
474{
475	struct pwm_chip *chip = platform_get_drvdata(pdev);
476	struct atmel_tcb_pwm_chip *tcbpwm = to_tcb_chip(chip);
477
478	pwmchip_remove(chip);
479
480	clk_disable_unprepare(tcbpwm->slow_clk);
481	clk_put(tcbpwm->gclk);
482	clk_put(tcbpwm->clk);
483	clk_put(tcbpwm->slow_clk);
484}
485
486static const struct of_device_id atmel_tcb_pwm_dt_ids[] = {
487	{ .compatible = "atmel,tcb-pwm", },
488	{ /* sentinel */ }
489};
490MODULE_DEVICE_TABLE(of, atmel_tcb_pwm_dt_ids);
491
492static int atmel_tcb_pwm_suspend(struct device *dev)
493{
494	struct pwm_chip *chip = dev_get_drvdata(dev);
495	struct atmel_tcb_pwm_chip *tcbpwm = to_tcb_chip(chip);
496	struct atmel_tcb_channel *chan = &tcbpwm->bkup;
497	unsigned int channel = tcbpwm->channel;
498
499	regmap_read(tcbpwm->regmap, ATMEL_TC_REG(channel, CMR), &chan->cmr);
500	regmap_read(tcbpwm->regmap, ATMEL_TC_REG(channel, RA), &chan->ra);
501	regmap_read(tcbpwm->regmap, ATMEL_TC_REG(channel, RB), &chan->rb);
502	regmap_read(tcbpwm->regmap, ATMEL_TC_REG(channel, RC), &chan->rc);
503
504	return 0;
505}
506
507static int atmel_tcb_pwm_resume(struct device *dev)
508{
509	struct pwm_chip *chip = dev_get_drvdata(dev);
510	struct atmel_tcb_pwm_chip *tcbpwm = to_tcb_chip(chip);
511	struct atmel_tcb_channel *chan = &tcbpwm->bkup;
512	unsigned int channel = tcbpwm->channel;
513
514	regmap_write(tcbpwm->regmap, ATMEL_TC_REG(channel, CMR), chan->cmr);
515	regmap_write(tcbpwm->regmap, ATMEL_TC_REG(channel, RA), chan->ra);
516	regmap_write(tcbpwm->regmap, ATMEL_TC_REG(channel, RB), chan->rb);
517	regmap_write(tcbpwm->regmap, ATMEL_TC_REG(channel, RC), chan->rc);
518
519	if (chan->enabled)
520		regmap_write(tcbpwm->regmap,
521			     ATMEL_TC_CLKEN | ATMEL_TC_SWTRG,
522			     ATMEL_TC_REG(channel, CCR));
523
524	return 0;
525}
526
527static DEFINE_SIMPLE_DEV_PM_OPS(atmel_tcb_pwm_pm_ops, atmel_tcb_pwm_suspend,
528				atmel_tcb_pwm_resume);
529
530static struct platform_driver atmel_tcb_pwm_driver = {
531	.driver = {
532		.name = "atmel-tcb-pwm",
533		.of_match_table = atmel_tcb_pwm_dt_ids,
534		.pm = pm_ptr(&atmel_tcb_pwm_pm_ops),
535	},
536	.probe = atmel_tcb_pwm_probe,
537	.remove_new = atmel_tcb_pwm_remove,
538};
539module_platform_driver(atmel_tcb_pwm_driver);
540
541MODULE_AUTHOR("Boris BREZILLON <b.brezillon@overkiz.com>");
542MODULE_DESCRIPTION("Atmel Timer Counter Pulse Width Modulation Driver");
543MODULE_LICENSE("GPL v2");
544