1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2017-2018 SiFive
4 * For SiFive's PWM IP block documentation please refer Chapter 14 of
5 * Reference Manual : https://static.dev.sifive.com/FU540-C000-v1.0.pdf
6 *
7 * Limitations:
8 * - When changing both duty cycle and period, we cannot prevent in
9 *   software that the output might produce a period with mixed
10 *   settings (new period length and old duty cycle).
11 * - The hardware cannot generate a 100% duty cycle.
12 * - The hardware generates only inverted output.
13 */
14#include <linux/clk.h>
15#include <linux/io.h>
16#include <linux/mod_devicetable.h>
17#include <linux/module.h>
18#include <linux/platform_device.h>
19#include <linux/pwm.h>
20#include <linux/slab.h>
21#include <linux/bitfield.h>
22
23/* Register offsets */
24#define PWM_SIFIVE_PWMCFG		0x0
25#define PWM_SIFIVE_PWMCOUNT		0x8
26#define PWM_SIFIVE_PWMS			0x10
27#define PWM_SIFIVE_PWMCMP(i)		(0x20 + 4 * (i))
28
29/* PWMCFG fields */
30#define PWM_SIFIVE_PWMCFG_SCALE		GENMASK(3, 0)
31#define PWM_SIFIVE_PWMCFG_STICKY	BIT(8)
32#define PWM_SIFIVE_PWMCFG_ZERO_CMP	BIT(9)
33#define PWM_SIFIVE_PWMCFG_DEGLITCH	BIT(10)
34#define PWM_SIFIVE_PWMCFG_EN_ALWAYS	BIT(12)
35#define PWM_SIFIVE_PWMCFG_EN_ONCE	BIT(13)
36#define PWM_SIFIVE_PWMCFG_CENTER	BIT(16)
37#define PWM_SIFIVE_PWMCFG_GANG		BIT(24)
38#define PWM_SIFIVE_PWMCFG_IP		BIT(28)
39
40#define PWM_SIFIVE_CMPWIDTH		16
41#define PWM_SIFIVE_DEFAULT_PERIOD	10000000
42
43struct pwm_sifive_ddata {
44	struct device *parent;
45	struct mutex lock; /* lock to protect user_count and approx_period */
46	struct notifier_block notifier;
47	struct clk *clk;
48	void __iomem *regs;
49	unsigned int real_period;
50	unsigned int approx_period;
51	int user_count;
52};
53
54static inline
55struct pwm_sifive_ddata *pwm_sifive_chip_to_ddata(struct pwm_chip *chip)
56{
57	return pwmchip_get_drvdata(chip);
58}
59
60static int pwm_sifive_request(struct pwm_chip *chip, struct pwm_device *pwm)
61{
62	struct pwm_sifive_ddata *ddata = pwm_sifive_chip_to_ddata(chip);
63
64	mutex_lock(&ddata->lock);
65	ddata->user_count++;
66	mutex_unlock(&ddata->lock);
67
68	return 0;
69}
70
71static void pwm_sifive_free(struct pwm_chip *chip, struct pwm_device *pwm)
72{
73	struct pwm_sifive_ddata *ddata = pwm_sifive_chip_to_ddata(chip);
74
75	mutex_lock(&ddata->lock);
76	ddata->user_count--;
77	mutex_unlock(&ddata->lock);
78}
79
80/* Called holding ddata->lock */
81static void pwm_sifive_update_clock(struct pwm_sifive_ddata *ddata,
82				    unsigned long rate)
83{
84	unsigned long long num;
85	unsigned long scale_pow;
86	int scale;
87	u32 val;
88	/*
89	 * The PWM unit is used with pwmzerocmp=0, so the only way to modify the
90	 * period length is using pwmscale which provides the number of bits the
91	 * counter is shifted before being feed to the comparators. A period
92	 * lasts (1 << (PWM_SIFIVE_CMPWIDTH + pwmscale)) clock ticks.
93	 * (1 << (PWM_SIFIVE_CMPWIDTH + scale)) * 10^9/rate = period
94	 */
95	scale_pow = div64_ul(ddata->approx_period * (u64)rate, NSEC_PER_SEC);
96	scale = clamp(ilog2(scale_pow) - PWM_SIFIVE_CMPWIDTH, 0, 0xf);
97
98	val = PWM_SIFIVE_PWMCFG_EN_ALWAYS |
99	      FIELD_PREP(PWM_SIFIVE_PWMCFG_SCALE, scale);
100	writel(val, ddata->regs + PWM_SIFIVE_PWMCFG);
101
102	/* As scale <= 15 the shift operation cannot overflow. */
103	num = (unsigned long long)NSEC_PER_SEC << (PWM_SIFIVE_CMPWIDTH + scale);
104	ddata->real_period = div64_ul(num, rate);
105	dev_dbg(ddata->parent,
106		"New real_period = %u ns\n", ddata->real_period);
107}
108
109static int pwm_sifive_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
110				struct pwm_state *state)
111{
112	struct pwm_sifive_ddata *ddata = pwm_sifive_chip_to_ddata(chip);
113	u32 duty, val;
114
115	duty = readl(ddata->regs + PWM_SIFIVE_PWMCMP(pwm->hwpwm));
116
117	state->enabled = duty > 0;
118
119	val = readl(ddata->regs + PWM_SIFIVE_PWMCFG);
120	if (!(val & PWM_SIFIVE_PWMCFG_EN_ALWAYS))
121		state->enabled = false;
122
123	state->period = ddata->real_period;
124	state->duty_cycle =
125		(u64)duty * ddata->real_period >> PWM_SIFIVE_CMPWIDTH;
126	state->polarity = PWM_POLARITY_INVERSED;
127
128	return 0;
129}
130
131static int pwm_sifive_apply(struct pwm_chip *chip, struct pwm_device *pwm,
132			    const struct pwm_state *state)
133{
134	struct pwm_sifive_ddata *ddata = pwm_sifive_chip_to_ddata(chip);
135	struct pwm_state cur_state;
136	unsigned int duty_cycle;
137	unsigned long long num;
138	bool enabled;
139	int ret = 0;
140	u32 frac;
141
142	if (state->polarity != PWM_POLARITY_INVERSED)
143		return -EINVAL;
144
145	cur_state = pwm->state;
146	enabled = cur_state.enabled;
147
148	duty_cycle = state->duty_cycle;
149	if (!state->enabled)
150		duty_cycle = 0;
151
152	/*
153	 * The problem of output producing mixed setting as mentioned at top,
154	 * occurs here. To minimize the window for this problem, we are
155	 * calculating the register values first and then writing them
156	 * consecutively
157	 */
158	num = (u64)duty_cycle * (1U << PWM_SIFIVE_CMPWIDTH);
159	frac = DIV64_U64_ROUND_CLOSEST(num, state->period);
160	/* The hardware cannot generate a 100% duty cycle */
161	frac = min(frac, (1U << PWM_SIFIVE_CMPWIDTH) - 1);
162
163	mutex_lock(&ddata->lock);
164	if (state->period != ddata->approx_period) {
165		/*
166		 * Don't let a 2nd user change the period underneath the 1st user.
167		 * However if ddate->approx_period == 0 this is the first time we set
168		 * any period, so let whoever gets here first set the period so other
169		 * users who agree on the period won't fail.
170		 */
171		if (ddata->user_count != 1 && ddata->approx_period) {
172			mutex_unlock(&ddata->lock);
173			return -EBUSY;
174		}
175		ddata->approx_period = state->period;
176		pwm_sifive_update_clock(ddata, clk_get_rate(ddata->clk));
177	}
178	mutex_unlock(&ddata->lock);
179
180	/*
181	 * If the PWM is enabled the clk is already on. So only enable it
182	 * conditionally to have it on exactly once afterwards independent of
183	 * the PWM state.
184	 */
185	if (!enabled) {
186		ret = clk_enable(ddata->clk);
187		if (ret) {
188			dev_err(pwmchip_parent(chip), "Enable clk failed\n");
189			return ret;
190		}
191	}
192
193	writel(frac, ddata->regs + PWM_SIFIVE_PWMCMP(pwm->hwpwm));
194
195	if (!state->enabled)
196		clk_disable(ddata->clk);
197
198	return 0;
199}
200
201static const struct pwm_ops pwm_sifive_ops = {
202	.request = pwm_sifive_request,
203	.free = pwm_sifive_free,
204	.get_state = pwm_sifive_get_state,
205	.apply = pwm_sifive_apply,
206};
207
208static int pwm_sifive_clock_notifier(struct notifier_block *nb,
209				     unsigned long event, void *data)
210{
211	struct clk_notifier_data *ndata = data;
212	struct pwm_sifive_ddata *ddata =
213		container_of(nb, struct pwm_sifive_ddata, notifier);
214
215	if (event == POST_RATE_CHANGE) {
216		mutex_lock(&ddata->lock);
217		pwm_sifive_update_clock(ddata, ndata->new_rate);
218		mutex_unlock(&ddata->lock);
219	}
220
221	return NOTIFY_OK;
222}
223
224static int pwm_sifive_probe(struct platform_device *pdev)
225{
226	struct device *dev = &pdev->dev;
227	struct pwm_sifive_ddata *ddata;
228	struct pwm_chip *chip;
229	int ret;
230	u32 val;
231	unsigned int enabled_pwms = 0, enabled_clks = 1;
232
233	chip = devm_pwmchip_alloc(dev, 4, sizeof(*ddata));
234	if (IS_ERR(chip))
235		return PTR_ERR(chip);
236
237	ddata = pwm_sifive_chip_to_ddata(chip);
238	ddata->parent = dev;
239	mutex_init(&ddata->lock);
240	chip->ops = &pwm_sifive_ops;
241
242	ddata->regs = devm_platform_ioremap_resource(pdev, 0);
243	if (IS_ERR(ddata->regs))
244		return PTR_ERR(ddata->regs);
245
246	ddata->clk = devm_clk_get_prepared(dev, NULL);
247	if (IS_ERR(ddata->clk))
248		return dev_err_probe(dev, PTR_ERR(ddata->clk),
249				     "Unable to find controller clock\n");
250
251	ret = clk_enable(ddata->clk);
252	if (ret) {
253		dev_err(dev, "failed to enable clock for pwm: %d\n", ret);
254		return ret;
255	}
256
257	val = readl(ddata->regs + PWM_SIFIVE_PWMCFG);
258	if (val & PWM_SIFIVE_PWMCFG_EN_ALWAYS) {
259		unsigned int i;
260
261		for (i = 0; i < chip->npwm; ++i) {
262			val = readl(ddata->regs + PWM_SIFIVE_PWMCMP(i));
263			if (val > 0)
264				++enabled_pwms;
265		}
266	}
267
268	/* The clk should be on once for each running PWM. */
269	if (enabled_pwms) {
270		while (enabled_clks < enabled_pwms) {
271			/* This is not expected to fail as the clk is already on */
272			ret = clk_enable(ddata->clk);
273			if (unlikely(ret)) {
274				dev_err_probe(dev, ret, "Failed to enable clk\n");
275				goto disable_clk;
276			}
277			++enabled_clks;
278		}
279	} else {
280		clk_disable(ddata->clk);
281		enabled_clks = 0;
282	}
283
284	/* Watch for changes to underlying clock frequency */
285	ddata->notifier.notifier_call = pwm_sifive_clock_notifier;
286	ret = clk_notifier_register(ddata->clk, &ddata->notifier);
287	if (ret) {
288		dev_err(dev, "failed to register clock notifier: %d\n", ret);
289		goto disable_clk;
290	}
291
292	ret = pwmchip_add(chip);
293	if (ret < 0) {
294		dev_err(dev, "cannot register PWM: %d\n", ret);
295		goto unregister_clk;
296	}
297
298	platform_set_drvdata(pdev, chip);
299	dev_dbg(dev, "SiFive PWM chip registered %d PWMs\n", chip->npwm);
300
301	return 0;
302
303unregister_clk:
304	clk_notifier_unregister(ddata->clk, &ddata->notifier);
305disable_clk:
306	while (enabled_clks) {
307		clk_disable(ddata->clk);
308		--enabled_clks;
309	}
310
311	return ret;
312}
313
314static void pwm_sifive_remove(struct platform_device *dev)
315{
316	struct pwm_chip *chip = platform_get_drvdata(dev);
317	struct pwm_sifive_ddata *ddata = pwm_sifive_chip_to_ddata(chip);
318	struct pwm_device *pwm;
319	int ch;
320
321	pwmchip_remove(chip);
322	clk_notifier_unregister(ddata->clk, &ddata->notifier);
323
324	for (ch = 0; ch < chip->npwm; ch++) {
325		pwm = &chip->pwms[ch];
326		if (pwm->state.enabled)
327			clk_disable(ddata->clk);
328	}
329}
330
331static const struct of_device_id pwm_sifive_of_match[] = {
332	{ .compatible = "sifive,pwm0" },
333	{},
334};
335MODULE_DEVICE_TABLE(of, pwm_sifive_of_match);
336
337static struct platform_driver pwm_sifive_driver = {
338	.probe = pwm_sifive_probe,
339	.remove_new = pwm_sifive_remove,
340	.driver = {
341		.name = "pwm-sifive",
342		.of_match_table = pwm_sifive_of_match,
343	},
344};
345module_platform_driver(pwm_sifive_driver);
346
347MODULE_DESCRIPTION("SiFive PWM driver");
348MODULE_LICENSE("GPL v2");
349