1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Broadcom BCM7038 PWM driver
4 * Author: Florian Fainelli
5 *
6 * Copyright (C) 2015 Broadcom Corporation
7 */
8
9#define pr_fmt(fmt)	KBUILD_MODNAME ": " fmt
10
11#include <linux/clk.h>
12#include <linux/export.h>
13#include <linux/init.h>
14#include <linux/io.h>
15#include <linux/kernel.h>
16#include <linux/module.h>
17#include <linux/of.h>
18#include <linux/platform_device.h>
19#include <linux/pwm.h>
20#include <linux/spinlock.h>
21
22#define PWM_CTRL		0x00
23#define  CTRL_START		BIT(0)
24#define  CTRL_OEB		BIT(1)
25#define  CTRL_FORCE_HIGH	BIT(2)
26#define  CTRL_OPENDRAIN		BIT(3)
27#define  CTRL_CHAN_OFFS		4
28
29#define PWM_CTRL2		0x04
30#define  CTRL2_OUT_SELECT	BIT(0)
31
32#define PWM_CH_SIZE		0x8
33
34#define PWM_CWORD_MSB(ch)	(0x08 + ((ch) * PWM_CH_SIZE))
35#define PWM_CWORD_LSB(ch)	(0x0c + ((ch) * PWM_CH_SIZE))
36
37/* Number of bits for the CWORD value */
38#define CWORD_BIT_SIZE		16
39
40/*
41 * Maximum control word value allowed when variable-frequency PWM is used as a
42 * clock for the constant-frequency PMW.
43 */
44#define CONST_VAR_F_MAX		32768
45#define CONST_VAR_F_MIN		1
46
47#define PWM_ON(ch)		(0x18 + ((ch) * PWM_CH_SIZE))
48#define  PWM_ON_MIN		1
49#define PWM_PERIOD(ch)		(0x1c + ((ch) * PWM_CH_SIZE))
50#define  PWM_PERIOD_MIN		0
51
52#define PWM_ON_PERIOD_MAX	0xff
53
54struct brcmstb_pwm {
55	void __iomem *base;
56	struct clk *clk;
57};
58
59static inline u32 brcmstb_pwm_readl(struct brcmstb_pwm *p,
60				    unsigned int offset)
61{
62	if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
63		return __raw_readl(p->base + offset);
64	else
65		return readl_relaxed(p->base + offset);
66}
67
68static inline void brcmstb_pwm_writel(struct brcmstb_pwm *p, u32 value,
69				      unsigned int offset)
70{
71	if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
72		__raw_writel(value, p->base + offset);
73	else
74		writel_relaxed(value, p->base + offset);
75}
76
77static inline struct brcmstb_pwm *to_brcmstb_pwm(struct pwm_chip *chip)
78{
79	return pwmchip_get_drvdata(chip);
80}
81
82/*
83 * Fv is derived from the variable frequency output. The variable frequency
84 * output is configured using this formula:
85 *
86 * W = cword, if cword < 2 ^ 15 else 16-bit 2's complement of cword
87 *
88 * Fv = W x 2 ^ -16 x 27Mhz (reference clock)
89 *
90 * The period is: (period + 1) / Fv and "on" time is on / (period + 1)
91 *
92 * The PWM core framework specifies that the "duty_ns" parameter is in fact the
93 * "on" time, so this translates directly into our HW programming here.
94 */
95static int brcmstb_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
96			      u64 duty_ns, u64 period_ns)
97{
98	struct brcmstb_pwm *p = to_brcmstb_pwm(chip);
99	unsigned long pc, dc, cword = CONST_VAR_F_MAX;
100	unsigned int channel = pwm->hwpwm;
101	u32 value;
102
103	/*
104	 * If asking for a duty_ns equal to period_ns, we need to substract
105	 * the period value by 1 to make it shorter than the "on" time and
106	 * produce a flat 100% duty cycle signal, and max out the "on" time
107	 */
108	if (duty_ns == period_ns) {
109		dc = PWM_ON_PERIOD_MAX;
110		pc = PWM_ON_PERIOD_MAX - 1;
111		goto done;
112	}
113
114	while (1) {
115		u64 rate;
116
117		/*
118		 * Calculate the base rate from base frequency and current
119		 * cword
120		 */
121		rate = (u64)clk_get_rate(p->clk) * (u64)cword;
122		rate >>= CWORD_BIT_SIZE;
123
124		pc = mul_u64_u64_div_u64(period_ns, rate, NSEC_PER_SEC);
125		dc = mul_u64_u64_div_u64(duty_ns + 1, rate, NSEC_PER_SEC);
126
127		/*
128		 * We can be called with separate duty and period updates,
129		 * so do not reject dc == 0 right away
130		 */
131		if (pc == PWM_PERIOD_MIN || (dc < PWM_ON_MIN && duty_ns))
132			return -EINVAL;
133
134		/* We converged on a calculation */
135		if (pc <= PWM_ON_PERIOD_MAX && dc <= PWM_ON_PERIOD_MAX)
136			break;
137
138		/*
139		 * The cword needs to be a power of 2 for the variable
140		 * frequency generator to output a 50% duty cycle variable
141		 * frequency which is used as input clock to the fixed
142		 * frequency generator.
143		 */
144		cword >>= 1;
145
146		/*
147		 * Desired periods are too large, we do not have a divider
148		 * for them
149		 */
150		if (cword < CONST_VAR_F_MIN)
151			return -EINVAL;
152	}
153
154done:
155	/*
156	 * Configure the defined "cword" value to have the variable frequency
157	 * generator output a base frequency for the constant frequency
158	 * generator to derive from.
159	 */
160	brcmstb_pwm_writel(p, cword >> 8, PWM_CWORD_MSB(channel));
161	brcmstb_pwm_writel(p, cword & 0xff, PWM_CWORD_LSB(channel));
162
163	/* Select constant frequency signal output */
164	value = brcmstb_pwm_readl(p, PWM_CTRL2);
165	value |= CTRL2_OUT_SELECT << (channel * CTRL_CHAN_OFFS);
166	brcmstb_pwm_writel(p, value, PWM_CTRL2);
167
168	/* Configure on and period value */
169	brcmstb_pwm_writel(p, pc, PWM_PERIOD(channel));
170	brcmstb_pwm_writel(p, dc, PWM_ON(channel));
171
172	return 0;
173}
174
175static inline void brcmstb_pwm_enable_set(struct brcmstb_pwm *p,
176					  unsigned int channel, bool enable)
177{
178	unsigned int shift = channel * CTRL_CHAN_OFFS;
179	u32 value;
180
181	value = brcmstb_pwm_readl(p, PWM_CTRL);
182
183	if (enable) {
184		value &= ~(CTRL_OEB << shift);
185		value |= (CTRL_START | CTRL_OPENDRAIN) << shift;
186	} else {
187		value &= ~((CTRL_START | CTRL_OPENDRAIN) << shift);
188		value |= CTRL_OEB << shift;
189	}
190
191	brcmstb_pwm_writel(p, value, PWM_CTRL);
192}
193
194static int brcmstb_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
195			     const struct pwm_state *state)
196{
197	struct brcmstb_pwm *p = to_brcmstb_pwm(chip);
198	int err;
199
200	if (state->polarity != PWM_POLARITY_NORMAL)
201		return -EINVAL;
202
203	if (!state->enabled) {
204		if (pwm->state.enabled)
205			brcmstb_pwm_enable_set(p, pwm->hwpwm, false);
206
207		return 0;
208	}
209
210	err = brcmstb_pwm_config(chip, pwm, state->duty_cycle, state->period);
211	if (err)
212		return err;
213
214	if (!pwm->state.enabled)
215		brcmstb_pwm_enable_set(p, pwm->hwpwm, true);
216
217	return 0;
218}
219
220static const struct pwm_ops brcmstb_pwm_ops = {
221	.apply = brcmstb_pwm_apply,
222};
223
224static const struct of_device_id brcmstb_pwm_of_match[] = {
225	{ .compatible = "brcm,bcm7038-pwm", },
226	{ /* sentinel */ }
227};
228MODULE_DEVICE_TABLE(of, brcmstb_pwm_of_match);
229
230static int brcmstb_pwm_probe(struct platform_device *pdev)
231{
232	struct pwm_chip *chip;
233	struct brcmstb_pwm *p;
234	int ret;
235
236	chip = devm_pwmchip_alloc(&pdev->dev, 2, sizeof(*p));
237	if (IS_ERR(chip))
238		return PTR_ERR(chip);
239	p = to_brcmstb_pwm(chip);
240
241	p->clk = devm_clk_get_enabled(&pdev->dev, NULL);
242	if (IS_ERR(p->clk))
243		return dev_err_probe(&pdev->dev, PTR_ERR(p->clk),
244				     "failed to obtain clock\n");
245
246	platform_set_drvdata(pdev, p);
247
248	chip->ops = &brcmstb_pwm_ops;
249
250	p->base = devm_platform_ioremap_resource(pdev, 0);
251	if (IS_ERR(p->base))
252		return PTR_ERR(p->base);
253
254	ret = devm_pwmchip_add(&pdev->dev, chip);
255	if (ret)
256		return dev_err_probe(&pdev->dev, ret, "failed to add PWM chip\n");
257
258	return 0;
259}
260
261static int brcmstb_pwm_suspend(struct device *dev)
262{
263	struct brcmstb_pwm *p = dev_get_drvdata(dev);
264
265	clk_disable_unprepare(p->clk);
266
267	return 0;
268}
269
270static int brcmstb_pwm_resume(struct device *dev)
271{
272	struct brcmstb_pwm *p = dev_get_drvdata(dev);
273
274	return clk_prepare_enable(p->clk);
275}
276
277static DEFINE_SIMPLE_DEV_PM_OPS(brcmstb_pwm_pm_ops, brcmstb_pwm_suspend,
278				brcmstb_pwm_resume);
279
280static struct platform_driver brcmstb_pwm_driver = {
281	.probe = brcmstb_pwm_probe,
282	.driver = {
283		.name = "pwm-brcmstb",
284		.of_match_table = brcmstb_pwm_of_match,
285		.pm = pm_ptr(&brcmstb_pwm_pm_ops),
286	},
287};
288module_platform_driver(brcmstb_pwm_driver);
289
290MODULE_AUTHOR("Florian Fainelli <f.fainelli@gmail.com>");
291MODULE_DESCRIPTION("Broadcom STB PWM driver");
292MODULE_ALIAS("platform:pwm-brcmstb");
293MODULE_LICENSE("GPL");
294