1// SPDX-License-Identifier: GPL-2.0-only
2// Copyright (C) 2014 Broadcom Corporation
3
4#include <linux/clk.h>
5#include <linux/delay.h>
6#include <linux/err.h>
7#include <linux/io.h>
8#include <linux/ioport.h>
9#include <linux/math64.h>
10#include <linux/module.h>
11#include <linux/of.h>
12#include <linux/platform_device.h>
13#include <linux/pwm.h>
14#include <linux/slab.h>
15#include <linux/types.h>
16
17/*
18 * The Kona PWM has some unusual characteristics.  Here are the main points.
19 *
20 * 1) There is no disable bit and the hardware docs advise programming a zero
21 *    duty to achieve output equivalent to that of a normal disable operation.
22 *
23 * 2) Changes to prescale, duty, period, and polarity do not take effect until
24 *    a subsequent rising edge of the trigger bit.
25 *
26 * 3) If the smooth bit and trigger bit are both low, the output is a constant
27 *    high signal.  Otherwise, the earlier waveform continues to be output.
28 *
29 * 4) If the smooth bit is set on the rising edge of the trigger bit, output
30 *    will transition to the new settings on a period boundary (which could be
31 *    seconds away).  If the smooth bit is clear, new settings will be applied
32 *    as soon as possible (the hardware always has a 400ns delay).
33 *
34 * 5) When the external clock that feeds the PWM is disabled, output is pegged
35 *    high or low depending on its state at that exact instant.
36 */
37
38#define PWM_CONTROL_OFFSET			0x00000000
39#define PWM_CONTROL_SMOOTH_SHIFT(chan)		(24 + (chan))
40#define PWM_CONTROL_TYPE_SHIFT(chan)		(16 + (chan))
41#define PWM_CONTROL_POLARITY_SHIFT(chan)	(8 + (chan))
42#define PWM_CONTROL_TRIGGER_SHIFT(chan)		(chan)
43
44#define PRESCALE_OFFSET				0x00000004
45#define PRESCALE_SHIFT(chan)			((chan) << 2)
46#define PRESCALE_MASK(chan)			(0x7 << PRESCALE_SHIFT(chan))
47#define PRESCALE_MIN				0x00000000
48#define PRESCALE_MAX				0x00000007
49
50#define PERIOD_COUNT_OFFSET(chan)		(0x00000008 + ((chan) << 3))
51#define PERIOD_COUNT_MIN			0x00000002
52#define PERIOD_COUNT_MAX			0x00ffffff
53
54#define DUTY_CYCLE_HIGH_OFFSET(chan)		(0x0000000c + ((chan) << 3))
55#define DUTY_CYCLE_HIGH_MIN			0x00000000
56#define DUTY_CYCLE_HIGH_MAX			0x00ffffff
57
58struct kona_pwmc {
59	void __iomem *base;
60	struct clk *clk;
61};
62
63static inline struct kona_pwmc *to_kona_pwmc(struct pwm_chip *chip)
64{
65	return pwmchip_get_drvdata(chip);
66}
67
68/*
69 * Clear trigger bit but set smooth bit to maintain old output.
70 */
71static void kona_pwmc_prepare_for_settings(struct kona_pwmc *kp,
72	unsigned int chan)
73{
74	unsigned int value = readl(kp->base + PWM_CONTROL_OFFSET);
75
76	value |= 1 << PWM_CONTROL_SMOOTH_SHIFT(chan);
77	value &= ~(1 << PWM_CONTROL_TRIGGER_SHIFT(chan));
78	writel(value, kp->base + PWM_CONTROL_OFFSET);
79
80	/*
81	 * There must be a min 400ns delay between clearing trigger and setting
82	 * it. Failing to do this may result in no PWM signal.
83	 */
84	ndelay(400);
85}
86
87static void kona_pwmc_apply_settings(struct kona_pwmc *kp, unsigned int chan)
88{
89	unsigned int value = readl(kp->base + PWM_CONTROL_OFFSET);
90
91	/* Set trigger bit and clear smooth bit to apply new settings */
92	value &= ~(1 << PWM_CONTROL_SMOOTH_SHIFT(chan));
93	value |= 1 << PWM_CONTROL_TRIGGER_SHIFT(chan);
94	writel(value, kp->base + PWM_CONTROL_OFFSET);
95
96	/* Trigger bit must be held high for at least 400 ns. */
97	ndelay(400);
98}
99
100static int kona_pwmc_config(struct pwm_chip *chip, struct pwm_device *pwm,
101			    u64 duty_ns, u64 period_ns)
102{
103	struct kona_pwmc *kp = to_kona_pwmc(chip);
104	u64 div, rate;
105	unsigned long prescale = PRESCALE_MIN, pc, dc;
106	unsigned int value, chan = pwm->hwpwm;
107
108	/*
109	 * Find period count, duty count and prescale to suit duty_ns and
110	 * period_ns. This is done according to formulas described below:
111	 *
112	 * period_ns = 10^9 * (PRESCALE + 1) * PC / PWM_CLK_RATE
113	 * duty_ns = 10^9 * (PRESCALE + 1) * DC / PWM_CLK_RATE
114	 *
115	 * PC = (PWM_CLK_RATE * period_ns) / (10^9 * (PRESCALE + 1))
116	 * DC = (PWM_CLK_RATE * duty_ns) / (10^9 * (PRESCALE + 1))
117	 */
118
119	rate = clk_get_rate(kp->clk);
120
121	while (1) {
122		div = 1000000000;
123		div *= 1 + prescale;
124		pc = mul_u64_u64_div_u64(rate, period_ns, div);
125		dc = mul_u64_u64_div_u64(rate, duty_ns, div);
126
127		/* If duty_ns or period_ns are not achievable then return */
128		if (pc < PERIOD_COUNT_MIN)
129			return -EINVAL;
130
131		/* If pc and dc are in bounds, the calculation is done */
132		if (pc <= PERIOD_COUNT_MAX && dc <= DUTY_CYCLE_HIGH_MAX)
133			break;
134
135		/* Otherwise, increase prescale and recalculate pc and dc */
136		if (++prescale > PRESCALE_MAX)
137			return -EINVAL;
138	}
139
140	kona_pwmc_prepare_for_settings(kp, chan);
141
142	value = readl(kp->base + PRESCALE_OFFSET);
143	value &= ~PRESCALE_MASK(chan);
144	value |= prescale << PRESCALE_SHIFT(chan);
145	writel(value, kp->base + PRESCALE_OFFSET);
146
147	writel(pc, kp->base + PERIOD_COUNT_OFFSET(chan));
148
149	writel(dc, kp->base + DUTY_CYCLE_HIGH_OFFSET(chan));
150
151	kona_pwmc_apply_settings(kp, chan);
152
153	return 0;
154}
155
156static int kona_pwmc_set_polarity(struct pwm_chip *chip, struct pwm_device *pwm,
157				  enum pwm_polarity polarity)
158{
159	struct kona_pwmc *kp = to_kona_pwmc(chip);
160	unsigned int chan = pwm->hwpwm;
161	unsigned int value;
162	int ret;
163
164	ret = clk_prepare_enable(kp->clk);
165	if (ret < 0) {
166		dev_err(pwmchip_parent(chip), "failed to enable clock: %d\n", ret);
167		return ret;
168	}
169
170	kona_pwmc_prepare_for_settings(kp, chan);
171
172	value = readl(kp->base + PWM_CONTROL_OFFSET);
173
174	if (polarity == PWM_POLARITY_NORMAL)
175		value |= 1 << PWM_CONTROL_POLARITY_SHIFT(chan);
176	else
177		value &= ~(1 << PWM_CONTROL_POLARITY_SHIFT(chan));
178
179	writel(value, kp->base + PWM_CONTROL_OFFSET);
180
181	kona_pwmc_apply_settings(kp, chan);
182
183	clk_disable_unprepare(kp->clk);
184
185	return 0;
186}
187
188static int kona_pwmc_enable(struct pwm_chip *chip, struct pwm_device *pwm)
189{
190	struct kona_pwmc *kp = to_kona_pwmc(chip);
191	int ret;
192
193	ret = clk_prepare_enable(kp->clk);
194	if (ret < 0) {
195		dev_err(pwmchip_parent(chip), "failed to enable clock: %d\n", ret);
196		return ret;
197	}
198
199	return 0;
200}
201
202static void kona_pwmc_disable(struct pwm_chip *chip, struct pwm_device *pwm)
203{
204	struct kona_pwmc *kp = to_kona_pwmc(chip);
205	unsigned int chan = pwm->hwpwm;
206	unsigned int value;
207
208	kona_pwmc_prepare_for_settings(kp, chan);
209
210	/* Simulate a disable by configuring for zero duty */
211	writel(0, kp->base + DUTY_CYCLE_HIGH_OFFSET(chan));
212	writel(0, kp->base + PERIOD_COUNT_OFFSET(chan));
213
214	/* Set prescale to 0 for this channel */
215	value = readl(kp->base + PRESCALE_OFFSET);
216	value &= ~PRESCALE_MASK(chan);
217	writel(value, kp->base + PRESCALE_OFFSET);
218
219	kona_pwmc_apply_settings(kp, chan);
220
221	clk_disable_unprepare(kp->clk);
222}
223
224static int kona_pwmc_apply(struct pwm_chip *chip, struct pwm_device *pwm,
225			   const struct pwm_state *state)
226{
227	int err;
228	struct kona_pwmc *kp = to_kona_pwmc(chip);
229	bool enabled = pwm->state.enabled;
230
231	if (state->polarity != pwm->state.polarity) {
232		if (enabled) {
233			kona_pwmc_disable(chip, pwm);
234			enabled = false;
235		}
236
237		err = kona_pwmc_set_polarity(chip, pwm, state->polarity);
238		if (err)
239			return err;
240
241		pwm->state.polarity = state->polarity;
242	}
243
244	if (!state->enabled) {
245		if (enabled)
246			kona_pwmc_disable(chip, pwm);
247		return 0;
248	} else if (!enabled) {
249		/*
250		 * This is a bit special here, usually the PWM should only be
251		 * enabled when duty and period are setup. But before this
252		 * driver was converted to .apply it was done the other way
253		 * around and so this behaviour was kept even though this might
254		 * result in a glitch. This might be improvable by someone with
255		 * hardware and/or documentation.
256		 */
257		err = kona_pwmc_enable(chip, pwm);
258		if (err)
259			return err;
260	}
261
262	err = kona_pwmc_config(chip, pwm, state->duty_cycle, state->period);
263	if (err && !pwm->state.enabled)
264		clk_disable_unprepare(kp->clk);
265
266	return err;
267}
268
269static const struct pwm_ops kona_pwm_ops = {
270	.apply = kona_pwmc_apply,
271};
272
273static int kona_pwmc_probe(struct platform_device *pdev)
274{
275	struct pwm_chip *chip;
276	struct kona_pwmc *kp;
277	unsigned int chan;
278	unsigned int value = 0;
279	int ret = 0;
280
281	chip = devm_pwmchip_alloc(&pdev->dev, 6, sizeof(*kp));
282	if (IS_ERR(chip))
283		return PTR_ERR(chip);
284	kp = to_kona_pwmc(chip);
285
286	chip->ops = &kona_pwm_ops;
287
288	kp->base = devm_platform_ioremap_resource(pdev, 0);
289	if (IS_ERR(kp->base))
290		return PTR_ERR(kp->base);
291
292	kp->clk = devm_clk_get(&pdev->dev, NULL);
293	if (IS_ERR(kp->clk)) {
294		dev_err(&pdev->dev, "failed to get clock: %ld\n",
295			PTR_ERR(kp->clk));
296		return PTR_ERR(kp->clk);
297	}
298
299	ret = clk_prepare_enable(kp->clk);
300	if (ret < 0) {
301		dev_err(&pdev->dev, "failed to enable clock: %d\n", ret);
302		return ret;
303	}
304
305	/* Set push/pull for all channels */
306	for (chan = 0; chan < chip->npwm; chan++)
307		value |= (1 << PWM_CONTROL_TYPE_SHIFT(chan));
308
309	writel(value, kp->base + PWM_CONTROL_OFFSET);
310
311	clk_disable_unprepare(kp->clk);
312
313	ret = devm_pwmchip_add(&pdev->dev, chip);
314	if (ret < 0)
315		dev_err(&pdev->dev, "failed to add PWM chip: %d\n", ret);
316
317	return ret;
318}
319
320static const struct of_device_id bcm_kona_pwmc_dt[] = {
321	{ .compatible = "brcm,kona-pwm" },
322	{ },
323};
324MODULE_DEVICE_TABLE(of, bcm_kona_pwmc_dt);
325
326static struct platform_driver kona_pwmc_driver = {
327	.driver = {
328		.name = "bcm-kona-pwm",
329		.of_match_table = bcm_kona_pwmc_dt,
330	},
331	.probe = kona_pwmc_probe,
332};
333module_platform_driver(kona_pwmc_driver);
334
335MODULE_AUTHOR("Broadcom Corporation <bcm-kernel-feedback-list@broadcom.com>");
336MODULE_AUTHOR("Tim Kryger <tkryger@broadcom.com>");
337MODULE_DESCRIPTION("Broadcom Kona PWM driver");
338MODULE_LICENSE("GPL v2");
339