1// SPDX-License-Identifier: GPL-2.0-or-later 2/* 3 * drivers/pwm/pwm-tegra.c 4 * 5 * Tegra pulse-width-modulation controller driver 6 * 7 * Copyright (c) 2010-2020, NVIDIA Corporation. 8 * Based on arch/arm/plat-mxc/pwm.c by Sascha Hauer <s.hauer@pengutronix.de> 9 * 10 * Overview of Tegra Pulse Width Modulator Register: 11 * 1. 13-bit: Frequency division (SCALE) 12 * 2. 8-bit : Pulse division (DUTY) 13 * 3. 1-bit : Enable bit 14 * 15 * The PWM clock frequency is divided by 256 before subdividing it based 16 * on the programmable frequency division value to generate the required 17 * frequency for PWM output. The maximum output frequency that can be 18 * achieved is (max rate of source clock) / 256. 19 * e.g. if source clock rate is 408 MHz, maximum output frequency can be: 20 * 408 MHz/256 = 1.6 MHz. 21 * This 1.6 MHz frequency can further be divided using SCALE value in PWM. 22 * 23 * PWM pulse width: 8 bits are usable [23:16] for varying pulse width. 24 * To achieve 100% duty cycle, program Bit [24] of this register to 25 * 1���b1. In which case the other bits [23:16] are set to don't care. 26 * 27 * Limitations: 28 * - When PWM is disabled, the output is driven to inactive. 29 * - It does not allow the current PWM period to complete and 30 * stops abruptly. 31 * 32 * - If the register is reconfigured while PWM is running, 33 * it does not complete the currently running period. 34 * 35 * - If the user input duty is beyond acceptible limits, 36 * -EINVAL is returned. 37 */ 38 39#include <linux/clk.h> 40#include <linux/err.h> 41#include <linux/io.h> 42#include <linux/module.h> 43#include <linux/of.h> 44#include <linux/pm_opp.h> 45#include <linux/pwm.h> 46#include <linux/platform_device.h> 47#include <linux/pinctrl/consumer.h> 48#include <linux/pm_runtime.h> 49#include <linux/slab.h> 50#include <linux/reset.h> 51 52#include <soc/tegra/common.h> 53 54#define PWM_ENABLE (1 << 31) 55#define PWM_DUTY_WIDTH 8 56#define PWM_DUTY_SHIFT 16 57#define PWM_SCALE_WIDTH 13 58#define PWM_SCALE_SHIFT 0 59 60struct tegra_pwm_soc { 61 unsigned int num_channels; 62 63 /* Maximum IP frequency for given SoCs */ 64 unsigned long max_frequency; 65}; 66 67struct tegra_pwm_chip { 68 struct clk *clk; 69 struct reset_control*rst; 70 71 unsigned long clk_rate; 72 unsigned long min_period_ns; 73 74 void __iomem *regs; 75 76 const struct tegra_pwm_soc *soc; 77}; 78 79static inline struct tegra_pwm_chip *to_tegra_pwm_chip(struct pwm_chip *chip) 80{ 81 return pwmchip_get_drvdata(chip); 82} 83 84static inline u32 pwm_readl(struct tegra_pwm_chip *pc, unsigned int offset) 85{ 86 return readl(pc->regs + (offset << 4)); 87} 88 89static inline void pwm_writel(struct tegra_pwm_chip *pc, unsigned int offset, u32 value) 90{ 91 writel(value, pc->regs + (offset << 4)); 92} 93 94static int tegra_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, 95 int duty_ns, int period_ns) 96{ 97 struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip); 98 unsigned long long c = duty_ns; 99 unsigned long rate, required_clk_rate; 100 u32 val = 0; 101 int err; 102 103 /* 104 * Convert from duty_ns / period_ns to a fixed number of duty ticks 105 * per (1 << PWM_DUTY_WIDTH) cycles and make sure to round to the 106 * nearest integer during division. 107 */ 108 c *= (1 << PWM_DUTY_WIDTH); 109 c = DIV_ROUND_CLOSEST_ULL(c, period_ns); 110 111 val = (u32)c << PWM_DUTY_SHIFT; 112 113 /* 114 * min period = max clock limit >> PWM_DUTY_WIDTH 115 */ 116 if (period_ns < pc->min_period_ns) 117 return -EINVAL; 118 119 /* 120 * Compute the prescaler value for which (1 << PWM_DUTY_WIDTH) 121 * cycles at the PWM clock rate will take period_ns nanoseconds. 122 * 123 * num_channels: If single instance of PWM controller has multiple 124 * channels (e.g. Tegra210 or older) then it is not possible to 125 * configure separate clock rates to each of the channels, in such 126 * case the value stored during probe will be referred. 127 * 128 * If every PWM controller instance has one channel respectively, i.e. 129 * nums_channels == 1 then only the clock rate can be modified 130 * dynamically (e.g. Tegra186 or Tegra194). 131 */ 132 if (pc->soc->num_channels == 1) { 133 /* 134 * Rate is multiplied with 2^PWM_DUTY_WIDTH so that it matches 135 * with the maximum possible rate that the controller can 136 * provide. Any further lower value can be derived by setting 137 * PFM bits[0:12]. 138 * 139 * required_clk_rate is a reference rate for source clock and 140 * it is derived based on user requested period. By setting the 141 * source clock rate as required_clk_rate, PWM controller will 142 * be able to configure the requested period. 143 */ 144 required_clk_rate = DIV_ROUND_UP_ULL((u64)NSEC_PER_SEC << PWM_DUTY_WIDTH, 145 period_ns); 146 147 if (required_clk_rate > clk_round_rate(pc->clk, required_clk_rate)) 148 /* 149 * required_clk_rate is a lower bound for the input 150 * rate; for lower rates there is no value for PWM_SCALE 151 * that yields a period less than or equal to the 152 * requested period. Hence, for lower rates, double the 153 * required_clk_rate to get a clock rate that can meet 154 * the requested period. 155 */ 156 required_clk_rate *= 2; 157 158 err = dev_pm_opp_set_rate(pwmchip_parent(chip), required_clk_rate); 159 if (err < 0) 160 return -EINVAL; 161 162 /* Store the new rate for further references */ 163 pc->clk_rate = clk_get_rate(pc->clk); 164 } 165 166 /* Consider precision in PWM_SCALE_WIDTH rate calculation */ 167 rate = mul_u64_u64_div_u64(pc->clk_rate, period_ns, 168 (u64)NSEC_PER_SEC << PWM_DUTY_WIDTH); 169 170 /* 171 * Since the actual PWM divider is the register's frequency divider 172 * field plus 1, we need to decrement to get the correct value to 173 * write to the register. 174 */ 175 if (rate > 0) 176 rate--; 177 else 178 return -EINVAL; 179 180 /* 181 * Make sure that the rate will fit in the register's frequency 182 * divider field. 183 */ 184 if (rate >> PWM_SCALE_WIDTH) 185 return -EINVAL; 186 187 val |= rate << PWM_SCALE_SHIFT; 188 189 /* 190 * If the PWM channel is disabled, make sure to turn on the clock 191 * before writing the register. Otherwise, keep it enabled. 192 */ 193 if (!pwm_is_enabled(pwm)) { 194 err = pm_runtime_resume_and_get(pwmchip_parent(chip)); 195 if (err) 196 return err; 197 } else 198 val |= PWM_ENABLE; 199 200 pwm_writel(pc, pwm->hwpwm, val); 201 202 /* 203 * If the PWM is not enabled, turn the clock off again to save power. 204 */ 205 if (!pwm_is_enabled(pwm)) 206 pm_runtime_put(pwmchip_parent(chip)); 207 208 return 0; 209} 210 211static int tegra_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) 212{ 213 struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip); 214 int rc = 0; 215 u32 val; 216 217 rc = pm_runtime_resume_and_get(pwmchip_parent(chip)); 218 if (rc) 219 return rc; 220 221 val = pwm_readl(pc, pwm->hwpwm); 222 val |= PWM_ENABLE; 223 pwm_writel(pc, pwm->hwpwm, val); 224 225 return 0; 226} 227 228static void tegra_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) 229{ 230 struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip); 231 u32 val; 232 233 val = pwm_readl(pc, pwm->hwpwm); 234 val &= ~PWM_ENABLE; 235 pwm_writel(pc, pwm->hwpwm, val); 236 237 pm_runtime_put_sync(pwmchip_parent(chip)); 238} 239 240static int tegra_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, 241 const struct pwm_state *state) 242{ 243 int err; 244 bool enabled = pwm->state.enabled; 245 246 if (state->polarity != PWM_POLARITY_NORMAL) 247 return -EINVAL; 248 249 if (!state->enabled) { 250 if (enabled) 251 tegra_pwm_disable(chip, pwm); 252 253 return 0; 254 } 255 256 err = tegra_pwm_config(chip, pwm, state->duty_cycle, state->period); 257 if (err) 258 return err; 259 260 if (!enabled) 261 err = tegra_pwm_enable(chip, pwm); 262 263 return err; 264} 265 266static const struct pwm_ops tegra_pwm_ops = { 267 .apply = tegra_pwm_apply, 268}; 269 270static int tegra_pwm_probe(struct platform_device *pdev) 271{ 272 struct pwm_chip *chip; 273 struct tegra_pwm_chip *pc; 274 const struct tegra_pwm_soc *soc; 275 int ret; 276 277 soc = of_device_get_match_data(&pdev->dev); 278 279 chip = devm_pwmchip_alloc(&pdev->dev, soc->num_channels, sizeof(*pc)); 280 if (IS_ERR(chip)) 281 return PTR_ERR(chip); 282 pc = to_tegra_pwm_chip(chip); 283 284 pc->soc = soc; 285 286 pc->regs = devm_platform_ioremap_resource(pdev, 0); 287 if (IS_ERR(pc->regs)) 288 return PTR_ERR(pc->regs); 289 290 platform_set_drvdata(pdev, chip); 291 292 pc->clk = devm_clk_get(&pdev->dev, NULL); 293 if (IS_ERR(pc->clk)) 294 return PTR_ERR(pc->clk); 295 296 ret = devm_tegra_core_dev_init_opp_table_common(&pdev->dev); 297 if (ret) 298 return ret; 299 300 pm_runtime_enable(&pdev->dev); 301 ret = pm_runtime_resume_and_get(&pdev->dev); 302 if (ret) 303 return ret; 304 305 /* Set maximum frequency of the IP */ 306 ret = dev_pm_opp_set_rate(&pdev->dev, pc->soc->max_frequency); 307 if (ret < 0) { 308 dev_err(&pdev->dev, "Failed to set max frequency: %d\n", ret); 309 goto put_pm; 310 } 311 312 /* 313 * The requested and configured frequency may differ due to 314 * clock register resolutions. Get the configured frequency 315 * so that PWM period can be calculated more accurately. 316 */ 317 pc->clk_rate = clk_get_rate(pc->clk); 318 319 /* Set minimum limit of PWM period for the IP */ 320 pc->min_period_ns = 321 (NSEC_PER_SEC / (pc->soc->max_frequency >> PWM_DUTY_WIDTH)) + 1; 322 323 pc->rst = devm_reset_control_get_exclusive(&pdev->dev, "pwm"); 324 if (IS_ERR(pc->rst)) { 325 ret = PTR_ERR(pc->rst); 326 dev_err(&pdev->dev, "Reset control is not found: %d\n", ret); 327 goto put_pm; 328 } 329 330 reset_control_deassert(pc->rst); 331 332 chip->ops = &tegra_pwm_ops; 333 334 ret = pwmchip_add(chip); 335 if (ret < 0) { 336 dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret); 337 reset_control_assert(pc->rst); 338 goto put_pm; 339 } 340 341 pm_runtime_put(&pdev->dev); 342 343 return 0; 344put_pm: 345 pm_runtime_put_sync_suspend(&pdev->dev); 346 pm_runtime_force_suspend(&pdev->dev); 347 return ret; 348} 349 350static void tegra_pwm_remove(struct platform_device *pdev) 351{ 352 struct pwm_chip *chip = platform_get_drvdata(pdev); 353 struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip); 354 355 pwmchip_remove(chip); 356 357 reset_control_assert(pc->rst); 358 359 pm_runtime_force_suspend(&pdev->dev); 360} 361 362static int __maybe_unused tegra_pwm_runtime_suspend(struct device *dev) 363{ 364 struct pwm_chip *chip = dev_get_drvdata(dev); 365 struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip); 366 int err; 367 368 clk_disable_unprepare(pc->clk); 369 370 err = pinctrl_pm_select_sleep_state(dev); 371 if (err) { 372 clk_prepare_enable(pc->clk); 373 return err; 374 } 375 376 return 0; 377} 378 379static int __maybe_unused tegra_pwm_runtime_resume(struct device *dev) 380{ 381 struct pwm_chip *chip = dev_get_drvdata(dev); 382 struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip); 383 int err; 384 385 err = pinctrl_pm_select_default_state(dev); 386 if (err) 387 return err; 388 389 err = clk_prepare_enable(pc->clk); 390 if (err) { 391 pinctrl_pm_select_sleep_state(dev); 392 return err; 393 } 394 395 return 0; 396} 397 398static const struct tegra_pwm_soc tegra20_pwm_soc = { 399 .num_channels = 4, 400 .max_frequency = 48000000UL, 401}; 402 403static const struct tegra_pwm_soc tegra186_pwm_soc = { 404 .num_channels = 1, 405 .max_frequency = 102000000UL, 406}; 407 408static const struct tegra_pwm_soc tegra194_pwm_soc = { 409 .num_channels = 1, 410 .max_frequency = 408000000UL, 411}; 412 413static const struct of_device_id tegra_pwm_of_match[] = { 414 { .compatible = "nvidia,tegra20-pwm", .data = &tegra20_pwm_soc }, 415 { .compatible = "nvidia,tegra186-pwm", .data = &tegra186_pwm_soc }, 416 { .compatible = "nvidia,tegra194-pwm", .data = &tegra194_pwm_soc }, 417 { } 418}; 419MODULE_DEVICE_TABLE(of, tegra_pwm_of_match); 420 421static const struct dev_pm_ops tegra_pwm_pm_ops = { 422 SET_RUNTIME_PM_OPS(tegra_pwm_runtime_suspend, tegra_pwm_runtime_resume, 423 NULL) 424 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 425 pm_runtime_force_resume) 426}; 427 428static struct platform_driver tegra_pwm_driver = { 429 .driver = { 430 .name = "tegra-pwm", 431 .of_match_table = tegra_pwm_of_match, 432 .pm = &tegra_pwm_pm_ops, 433 }, 434 .probe = tegra_pwm_probe, 435 .remove_new = tegra_pwm_remove, 436}; 437 438module_platform_driver(tegra_pwm_driver); 439 440MODULE_LICENSE("GPL"); 441MODULE_AUTHOR("Sandipan Patra <spatra@nvidia.com>"); 442MODULE_DESCRIPTION("Tegra PWM controller driver"); 443MODULE_ALIAS("platform:tegra-pwm"); 444