Searched refs:xa (Results 101 - 125 of 959) sorted by relevance

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/linux-master/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_10_1_0_sh_mask.h50 #define SDMA0_POWER_CNTL__MEM_POWER_DS_EN__SHIFT 0xa
121 #define SDMA0_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE__SHIFT 0xa
203 #define SDMA0_STATUS_REG__EX_IDLE__SHIFT 0xa
260 #define SDMA0_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa
338 #define SDMA_PGFSM_CONFIG__P1_SELECT__SHIFT 0xa
390 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED__SHIFT 0xa
456 #define SDMA0_UTCL1_WATERMK__REQPG_WATERMK__SHIFT 0xa
474 #define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0xa
529 #define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0xa
643 #define SDMA0_UTCL1_PAGE__USE_PT_SNOOP__SHIFT 0xa
[all...]
H A Dgc_9_1_sh_mask.h44 #define GRBM_STATUS2__ME2PIPE0_RQ_PENDING__SHIFT 0xa
484 #define CP_CPC_STATUS__TCIU_BUSY__SHIFT 0xa
519 #define CP_CPC_BUSY_STAT__MEC1_PIPE0_BUSY__SHIFT 0xa
571 #define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_READ__SHIFT 0xa
603 #define CP_CPF_STATUS__ROQ_CE_INDIRECT1_BUSY__SHIFT 0xa
710 #define CP_CPF_STALLED_STAT1__CMP_UTCL1_WAITING_ON_TRANS__SHIFT 0xa
778 #define CP_PRT_LOD_STATS_CNTL3__RESET_CNT__SHIFT 0xa
813 #define CP_STALLED_STAT3__CE_WAITING_ON_BUFFER_DATA__SHIFT 0xa
847 #define CP_STALLED_STAT1__ME_HAS_ACTIVE_CE_BUFFER_FLAG__SHIFT 0xa
884 #define CP_STALLED_STAT2__ME_WAIT_ON_AVAIL_BUFFER__SHIFT 0xa
[all...]
H A Dgc_9_2_1_sh_mask.h44 #define GRBM_STATUS2__ME2PIPE0_RQ_PENDING__SHIFT 0xa
473 #define CP_CPC_STATUS__TCIU_BUSY__SHIFT 0xa
508 #define CP_CPC_BUSY_STAT__MEC1_PIPE0_BUSY__SHIFT 0xa
560 #define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_READ__SHIFT 0xa
592 #define CP_CPF_STATUS__ROQ_CE_INDIRECT1_BUSY__SHIFT 0xa
699 #define CP_CPF_STALLED_STAT1__CMP_UTCL1_WAITING_ON_TRANS__SHIFT 0xa
780 #define CP_STALLED_STAT3__CE_WAITING_ON_BUFFER_DATA__SHIFT 0xa
814 #define CP_STALLED_STAT1__ME_HAS_ACTIVE_CE_BUFFER_FLAG__SHIFT 0xa
851 #define CP_STALLED_STAT2__ME_WAIT_ON_AVAIL_BUFFER__SHIFT 0xa
908 #define CP_BUSY_STAT__RCIU_ME_BUSY__SHIFT 0xa
[all...]
H A Dgc_11_0_3_sh_mask.h52 #define SDMA0_CNTL__CP_MES_INT_ENABLE__SHIFT 0xa
89 #define SDMA0_CHICKEN_BITS__COMBINE_256B_WAIT_CYCLE__SHIFT 0xa
177 #define SDMA0_STATUS_REG__EX_IDLE__SHIFT 0xa
240 #define SDMA0_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa
361 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED__SHIFT 0xa
429 #define SDMA0_UTCL1_WATERMK__RD_REQ_FIFO_DEPTH_STEP__SHIFT 0xa
450 #define SDMA0_UTCL1_PAGE__USE_PT_SNOOP__SHIFT 0xa
481 #define SDMA0_UTCL1_RD_STATUS__RD_PAGE_FIFO_FULL__SHIFT 0xa
544 #define SDMA0_UTCL1_WR_STATUS__WR_PAGE_FIFO_FULL__SHIFT 0xa
632 #define SDMA0_UTCL1_RD_XNACK1__XNACK_NULL_VECTOR__SHIFT 0xa
[all...]
H A Dgc_9_0_sh_mask.h30 #define GCEA_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT__SHIFT 0xa
61 #define GCEA_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT__SHIFT 0xa
143 #define GRBM_STATUS2__ME2PIPE0_RQ_PENDING__SHIFT 0xa
585 #define CP_CPC_STATUS__TCIU_BUSY__SHIFT 0xa
620 #define CP_CPC_BUSY_STAT__MEC1_PIPE0_BUSY__SHIFT 0xa
672 #define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_READ__SHIFT 0xa
704 #define CP_CPF_STATUS__ROQ_CE_INDIRECT1_BUSY__SHIFT 0xa
811 #define CP_CPF_STALLED_STAT1__CMP_UTCL1_WAITING_ON_TRANS__SHIFT 0xa
879 #define CP_PRT_LOD_STATS_CNTL3__RESET_CNT__SHIFT 0xa
914 #define CP_STALLED_STAT3__CE_WAITING_ON_BUFFER_DATA__SHIFT 0xa
[all...]
H A Dgc_11_0_0_sh_mask.h52 #define SDMA0_CNTL__CP_MES_INT_ENABLE__SHIFT 0xa
86 #define SDMA0_CHICKEN_BITS__COMBINE_256B_WAIT_CYCLE__SHIFT 0xa
171 #define SDMA0_STATUS_REG__EX_IDLE__SHIFT 0xa
228 #define SDMA0_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa
343 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED__SHIFT 0xa
411 #define SDMA0_UTCL1_WATERMK__RD_REQ_FIFO_DEPTH_STEP__SHIFT 0xa
431 #define SDMA0_UTCL1_PAGE__USE_PT_SNOOP__SHIFT 0xa
461 #define SDMA0_UTCL1_RD_STATUS__RD_PAGE_FIFO_FULL__SHIFT 0xa
524 #define SDMA0_UTCL1_WR_STATUS__WR_PAGE_FIFO_FULL__SHIFT 0xa
612 #define SDMA0_UTCL1_RD_XNACK1__XNACK_NULL_VECTOR__SHIFT 0xa
[all...]
/linux-master/drivers/gpu/drm/amd/include/asic_reg/bif/
H A Dbif_5_1_enum.h38 DBG_BLOCK_ID_IH = 0xa,
295 DBG_BLOCK_ID_VC0_BY2 = 0xa,
417 DBG_BLOCK_ID_TCAA_BY4 = 0xa,
479 DBG_BLOCK_ID_SXS_BY8 = 0xa,
511 DBG_BLOCK_ID_TA10_BY16 = 0xa,
534 ARRAY_PRT_2D_TILED_THICK = 0xa,
672 CMASK_ALPHA1_FRAG4 = 0xa,
708 COLOR_8_8_8_8 = 0xa,
734 FMT_8_8_8_8 = 0xa,
800 BUF_DATA_FORMAT_8_8_8_8 = 0xa,
[all...]
H A Dbif_5_0_sh_mask.h60 #define BUS_CNTL__SET_AZ_TC__SHIFT 0xa
152 #define HW_DEBUG__HW_10_DEBUG__SHIFT 0xa
204 #define SLAVE_REQ_CREDIT_CNTL__BIF_HDP_REQ_CREDIT__SHIFT 0xa
284 #define CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE__SHIFT 0xa
322 #define BIF_FEATURES_CONTROL_MISC__AZ_BIF_REQ_ID_ROUTING_DIS__SHIFT 0xa
446 #define GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa
470 #define GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa
570 #define BACO_CNTL__PWRGOOD_GPIO__SHIFT 0xa
734 #define GARLIC_FLUSH_CNTL__VCE_OUT_RB_WPTR__SHIFT 0xa
842 #define GPU_GARLIC_FLUSH_REQ__SDMA0__SHIFT 0xa
[all...]
/linux-master/drivers/gpu/drm/amd/include/asic_reg/gmc/
H A Dgmc_8_2_enum.h38 DBG_BLOCK_ID_IH = 0xa,
295 DBG_BLOCK_ID_VC0_BY2 = 0xa,
417 DBG_BLOCK_ID_TCAA_BY4 = 0xa,
479 DBG_BLOCK_ID_SXS_BY8 = 0xa,
511 DBG_BLOCK_ID_TA10_BY16 = 0xa,
534 ARRAY_PRT_2D_TILED_THICK = 0xa,
672 CMASK_ALPHA1_FRAG4 = 0xa,
708 COLOR_8_8_8_8 = 0xa,
734 FMT_8_8_8_8 = 0xa,
800 BUF_DATA_FORMAT_8_8_8_8 = 0xa,
[all...]
/linux-master/drivers/gpu/drm/amd/include/asic_reg/smu/
H A Dsmu_8_0_enum.h38 DBG_BLOCK_ID_IH = 0xa,
295 DBG_BLOCK_ID_VC0_BY2 = 0xa,
417 DBG_BLOCK_ID_TCAA_BY4 = 0xa,
479 DBG_BLOCK_ID_SXS_BY8 = 0xa,
511 DBG_BLOCK_ID_TA10_BY16 = 0xa,
534 ARRAY_PRT_2D_TILED_THICK = 0xa,
672 CMASK_ALPHA1_FRAG4 = 0xa,
708 COLOR_8_8_8_8 = 0xa,
734 FMT_8_8_8_8 = 0xa,
800 BUF_DATA_FORMAT_8_8_8_8 = 0xa,
[all...]
/linux-master/sound/soc/amd/include/
H A Dacp_2_2_enum.h38 DBG_BLOCK_ID_IH = 0xa,
295 DBG_BLOCK_ID_VC0_BY2 = 0xa,
417 DBG_BLOCK_ID_TCAA_BY4 = 0xa,
479 DBG_BLOCK_ID_SXS_BY8 = 0xa,
511 DBG_BLOCK_ID_TA10_BY16 = 0xa,
534 ARRAY_PRT_2D_TILED_THICK = 0xa,
672 CMASK_ALPHA1_FRAG4 = 0xa,
708 COLOR_8_8_8_8 = 0xa,
734 FMT_8_8_8_8 = 0xa,
800 BUF_DATA_FORMAT_8_8_8_8 = 0xa,
[all...]
/linux-master/drivers/gpu/drm/amd/include/asic_reg/dpcs/
H A Ddpcs_2_0_3_sh_mask.h62 #define DPCSTX0_DPCSTX_INTERRUPT_CNTL__DPCS_TX2_FIFO_ERROR__SHIFT 0xa
133 #define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_CLOCK_ON__SHIFT 0xa
160 #define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_CLR__SHIFT 0xa
256 #define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_TX2RX_SER_LB_EN__SHIFT 0xa
279 #define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY__SHIFT 0xa
357 #define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_MPLL_EN__SHIFT 0xa
386 #define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN__SHIFT 0xa
560 #define DPCSTX1_DPCSTX_INTERRUPT_CNTL__DPCS_TX2_FIFO_ERROR__SHIFT 0xa
611 #define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_CLOCK_ON__SHIFT 0xa
638 #define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_CLR__SHIFT 0xa
[all...]
/linux-master/drivers/gpu/drm/amd/include/asic_reg/athub/
H A Dathub_1_0_sh_mask.h54 #define ATC_ATS_FAULT_CNTL__FAULT_INTERRUPT_TABLE__SHIFT 0xa
61 #define ATC_ATS_FAULT_STATUS_INFO__VMID__SHIFT 0xa
93 #define ATC_TRANS_FAULT_RSPCNTRL__VMID10__SHIFT 0xa
180 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID10_REMAPPING_FINISHED__SHIFT 0xa
357 #define ATC_ATS_VMID_STATUS__VMID10_OUTSTANDING__SHIFT 0xa
740 #define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID10__SHIFT 0xa
773 #define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID10__SHIFT 0xa
997 #define XPB_CLG_CFG0__HOST_FLUSH__SHIFT 0xa
1004 #define XPB_CLG_CFG1__HOST_FLUSH__SHIFT 0xa
1011 #define XPB_CLG_CFG2__HOST_FLUSH__SHIFT 0xa
[all...]
H A Dathub_1_8_0_sh_mask.h151 #define ATC_ATS_FAULT_CNTL__FAULT_INTERRUPT_TABLE__SHIFT 0xa
159 #define ATC_ATS_FAULT_STATUS_INFO__VMID__SHIFT 0xa
302 #define ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_QUICK_COMACK__SHIFT 0xa
353 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID10_REMAPPING_FINISHED__SHIFT 0xa
498 #define ATC_TRANS_FAULT_RSPCNTRL__VMID10__SHIFT 0xa
531 #define ATC_ATS_VMID_STATUS__VMID10_OUTSTANDING__SHIFT 0xa
815 #define XPB_CLG_CFG0__HOST_FLUSH__SHIFT 0xa
826 #define XPB_CLG_CFG1__HOST_FLUSH__SHIFT 0xa
837 #define XPB_CLG_CFG2__HOST_FLUSH__SHIFT 0xa
848 #define XPB_CLG_CFG3__HOST_FLUSH__SHIFT 0xa
[all...]
/linux-master/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_5_0_0_sh_mask.h44 #define UVD_CGC_GATE__LBSI__SHIFT 0xa
144 #define AVM_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa
209 #define EFC_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa
274 #define ENT_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa
339 #define IME_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa
404 #define PPU_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa
469 #define SAOE_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa
534 #define SCM_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa
599 #define SDB_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa
664 #define SIT0_NXT_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa
[all...]
H A Dvcn_4_0_3_sh_mask.h44 #define UVD_CGC_GATE__LBSI__SHIFT 0xa
144 #define AVM_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa
209 #define CDEFE_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa
274 #define EFC_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa
339 #define ENT_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa
404 #define IME_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa
469 #define PPU_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa
534 #define SAOE_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa
599 #define SCM_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa
664 #define SDB_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa
[all...]
/linux-master/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_2_0_sh_mask.h257 #define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK2_ROOT_GATE_DISABLE__SHIFT 0xa
296 #define OTG_PIXEL_RATE_DIV__OTG3_PIXEL_RATE_DIVK2__SHIFT 0xa
339 #define DCCG_GATE_DISABLE_CNTL__DPPCLK_R_DCCG_GATE_DISABLE__SHIFT 0xa
405 #define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK2_GATE_DISABLE__SHIFT 0xa
693 #define DSCCLK_DTO_CTRL__DSCCLK2_DTO_DB_EN__SHIFT 0xa
827 #define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG2_LATCH_MASK__SHIFT 0xa
945 #define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_SE1_GATE_DISABLE__SHIFT 0xa
1036 #define RBBMIF_TIMEOUT_DIS__CLIENT10_TIMEOUT_DIS__SHIFT 0xa
1174 #define DISP_INTERRUPT_STATUS__OTG1_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa
1211 #define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa
[all...]
/linux-master/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_5_0_sh_mask.h156 #define UVD_CGC_GATE__LBSI__SHIFT 0xa
200 #define UVD_CGC_STATUS__REGS_VCLK__SHIFT 0xa
312 #define UVD_CGC_UDEC_STATUS__DB_DCLK__SHIFT 0xa
434 #define UVD_LMI_STATUS__UMC_UVD_IDLE__SHIFT 0xa
452 #define UVD_LMI_SWAP_CNTL__CM_MC_SWAP__SHIFT 0xa
482 #define UVD_MP_SWAP_CNTL__MP_REF5_MC_SWAP__SHIFT 0xa
582 #define UVD_VCPU_CNTL__TRCE_EN__SHIFT 0xa
624 #define UVD_SOFT_RESET__IH_SOFT_RESET__SHIFT 0xa
744 #define UVD_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa
774 #define UVD_SUVD_CGC_STATUS__SCM_H264_DCLK__SHIFT 0xa
[all...]
H A Duvd_6_0_sh_mask.h158 #define UVD_CGC_GATE__LBSI__SHIFT 0xa
202 #define UVD_CGC_STATUS__REGS_VCLK__SHIFT 0xa
314 #define UVD_CGC_UDEC_STATUS__DB_DCLK__SHIFT 0xa
436 #define UVD_LMI_STATUS__UMC_UVD_IDLE__SHIFT 0xa
454 #define UVD_LMI_SWAP_CNTL__CM_MC_SWAP__SHIFT 0xa
484 #define UVD_MP_SWAP_CNTL__MP_REF5_MC_SWAP__SHIFT 0xa
584 #define UVD_VCPU_CNTL__TRCE_EN__SHIFT 0xa
626 #define UVD_SOFT_RESET__IH_SOFT_RESET__SHIFT 0xa
746 #define UVD_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa
772 #define UVD_SUVD_CGC_STATUS__SCM_H264_DCLK__SHIFT 0xa
[all...]
/linux-master/drivers/gpu/drm/amd/include/asic_reg/smuio/
H A Dsmuio_11_0_0_sh_mask.h61 #define CKSVII2C_IC_TAR__GC_OR_START__SHIFT 0xa
78 #define CKSVII2C_IC_DATA_CMD__RESTART__SHIFT 0xa
112 #define CKSVII2C_IC_INTR_STAT__R_START_DET__SHIFT 0xa
141 #define CKSVII2C_IC_INTR_MASK__M_START_DET__SHIFT 0xa
170 #define CKSVII2C_IC_RAW_INTR_STAT__R_START_DET__SHIFT 0xa
292 #define CKSVII2C1_IC_TAR__GC1_OR_START__SHIFT 0xa
309 #define CKSVII2C1_IC_DATA_CMD__RESTART1__SHIFT 0xa
343 #define CKSVII2C1_IC_INTR_STAT__R1_START_DET__SHIFT 0xa
372 #define CKSVII2C1_IC_INTR_MASK__M1_START_DET__SHIFT 0xa
756 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_10__SHIFT 0xa
[all...]
H A Dsmuio_13_0_2_sh_mask.h42 #define SMUIO_MCM_CONFIG__TOPOLOGY_ID__SHIFT 0xa
69 #define CKSVII2C_IC_TAR__GC_OR_START__SHIFT 0xa
86 #define CKSVII2C_IC_DATA_CMD__RESTART__SHIFT 0xa
120 #define CKSVII2C_IC_INTR_STAT__R_START_DET__SHIFT 0xa
149 #define CKSVII2C_IC_INTR_MASK__M_START_DET__SHIFT 0xa
287 #define CKSVII2C1_IC_TAR__GC1_OR_START__SHIFT 0xa
304 #define CKSVII2C1_IC_DATA_CMD__RESTART1__SHIFT 0xa
338 #define CKSVII2C1_IC_INTR_STAT__R1_START_DET__SHIFT 0xa
367 #define CKSVII2C1_IC_INTR_MASK__M1_START_DET__SHIFT 0xa
810 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_10__SHIFT 0xa
[all...]
H A Dsmuio_13_0_6_sh_mask.h118 #define PWR_DISP_TIMER_GLOBAL_CONTROL__DISP_TIMER_PULSE_EN__SHIFT 0xa
199 #define CKSVII2C_IC_TAR__GC_OR_START__SHIFT 0xa
216 #define CKSVII2C_IC_DATA_CMD__RESTART__SHIFT 0xa
252 #define CKSVII2C_IC_INTR_STAT__R_START_DET__SHIFT 0xa
283 #define CKSVII2C_IC_INTR_MASK__M_START_DET__SHIFT 0xa
341 #define CKSVII2C_IC_STATUS__SLV_HOLD_RX_FIFO_FULL__SHIFT 0xa
437 #define CKSVII2C1_IC_TAR__GC1_OR_START__SHIFT 0xa
454 #define CKSVII2C1_IC_DATA_CMD__RESTART1__SHIFT 0xa
490 #define CKSVII2C1_IC_INTR_STAT__R1_START_DET__SHIFT 0xa
521 #define CKSVII2C1_IC_INTR_MASK__M1_START_DET__SHIFT 0xa
[all...]
/linux-master/drivers/video/
H A Dvgastate.c59 vga_r(state->vgabase, iobase + 0xa);
62 vga_r(state->vgabase, iobase + 0xa);
241 vga_r(state->vgabase, iobase + 0xa);
244 vga_r(state->vgabase, iobase + 0xa);
247 vga_r(state->vgabase, iobase + 0xa);
278 vga_r(state->vgabase, iobase + 0xa);
294 vga_r(state->vgabase, iobase + 0xa);
305 vga_r(state->vgabase, iobase + 0xa);
/linux-master/include/video/
H A Dsh_mobile_lcdc.h59 #define LDMT1R_MIFTYP_RGB18 (0xa << 0)
71 #define LDMT1R_MIFTYP_SYS18 (0xa << 0)
/linux-master/include/linux/mfd/
H A Dwl1273-core.h167 #define WL1273_IS2_WIDTH_128 0xa
196 #define WL1273_IS2_RATE_8K (0xa << 12)

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