Lines Matching refs:xa
50 #define SDMA0_POWER_CNTL__MEM_POWER_DS_EN__SHIFT 0xa
121 #define SDMA0_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE__SHIFT 0xa
203 #define SDMA0_STATUS_REG__EX_IDLE__SHIFT 0xa
260 #define SDMA0_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa
338 #define SDMA_PGFSM_CONFIG__P1_SELECT__SHIFT 0xa
390 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED__SHIFT 0xa
456 #define SDMA0_UTCL1_WATERMK__REQPG_WATERMK__SHIFT 0xa
474 #define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0xa
529 #define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0xa
643 #define SDMA0_UTCL1_PAGE__USE_PT_SNOOP__SHIFT 0xa
677 #define SDMA0_RELAX_ORDERING_LUT__ATOMIC__SHIFT 0xa
756 #define SDMA0_PERFMON_CNTL__PERF_ENABLE1__SHIFT 0xa
824 #define SDMA0_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
835 #define SDMA0_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
850 #define SDMA0_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
861 #define SDMA0_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
975 #define SDMA0_GFX_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
1168 #define SDMA0_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
1358 #define SDMA0_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
1548 #define SDMA0_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
1738 #define SDMA0_RLC2_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
1928 #define SDMA0_RLC3_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
2118 #define SDMA0_RLC4_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
2308 #define SDMA0_RLC5_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
2498 #define SDMA0_RLC6_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
2688 #define SDMA0_RLC7_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
2816 #define SDMA1_POWER_CNTL__MEM_POWER_DS_EN__SHIFT 0xa
2887 #define SDMA1_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE__SHIFT 0xa
2969 #define SDMA1_STATUS_REG__EX_IDLE__SHIFT 0xa
3026 #define SDMA1_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa
3120 #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED__SHIFT 0xa
3186 #define SDMA1_UTCL1_WATERMK__REQPG_WATERMK__SHIFT 0xa
3204 #define SDMA1_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0xa
3259 #define SDMA1_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0xa
3373 #define SDMA1_UTCL1_PAGE__USE_PT_SNOOP__SHIFT 0xa
3407 #define SDMA1_RELAX_ORDERING_LUT__ATOMIC__SHIFT 0xa
3486 #define SDMA1_PERFMON_CNTL__PERF_ENABLE1__SHIFT 0xa
3554 #define SDMA1_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
3565 #define SDMA1_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
3580 #define SDMA1_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
3591 #define SDMA1_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
3705 #define SDMA1_GFX_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
3898 #define SDMA1_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
4088 #define SDMA1_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
4278 #define SDMA1_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
4468 #define SDMA1_RLC2_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
4658 #define SDMA1_RLC3_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
4848 #define SDMA1_RLC4_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
5038 #define SDMA1_RLC5_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
5228 #define SDMA1_RLC6_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
5418 #define SDMA1_RLC7_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
5540 #define GRBM_STATUS2__ME2PIPE0_RQ_PENDING__SHIFT 0xa
5707 #define GRBM_STATUS3__MESPIPE2_RQ_PENDING__SHIFT 0xa
6009 #define CP_CPC_STATUS__TCIU_BUSY__SHIFT 0xa
6054 #define CP_CPC_BUSY_STAT__MEC1_PIPE0_BUSY__SHIFT 0xa
6106 #define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_READ__SHIFT 0xa
6140 #define CP_CPF_STATUS__ROQ_CE_INDIRECT1_BUSY__SHIFT 0xa
6199 #define CP_CPF_BUSY_STAT__CSF_CE_DATA_BUSY__SHIFT 0xa
6263 #define CP_CPF_STALLED_STAT1__CMP_UTCL1_WAITING_ON_TRANS__SHIFT 0xa
6286 #define CP_CPC_BUSY_STAT2__MES_PIPE0_BUSY__SHIFT 0xa
6392 #define CP_STALLED_STAT3__CE_WAITING_ON_BUFFER_DATA__SHIFT 0xa
6428 #define CP_STALLED_STAT1__ME_HAS_ACTIVE_CE_BUFFER_FLAG__SHIFT 0xa
6466 #define CP_STALLED_STAT2__ME_WAIT_ON_AVAIL_BUFFER__SHIFT 0xa
6524 #define CP_BUSY_STAT__RCIU_ME_BUSY__SHIFT 0xa
6555 #define CP_STAT__ROQ_INDIRECT1_BUSY__SHIFT 0xa
6711 #define CP_ROQ1_THRESHOLDS__R0_IB1_START__SHIFT 0xa
6718 #define CP_ROQ2_THRESHOLDS__R1_IB2_START__SHIFT 0xa
6822 #define CP_ROQ3_THRESHOLDS__R1_DB_START__SHIFT 0xa
6940 #define VGT_CNTL_STATUS__VGT_PRIMGEN_BUSY__SHIFT 0xa
7059 #define GE_PRIV_CONTROL__RESET_ON_PIPELINE_CHANGE__SHIFT 0xa
7219 #define PA_SC_BINNER_EVENT_CNTL_0__CONTEXT_DONE__SHIFT 0xa
7252 #define PA_SC_BINNER_EVENT_CNTL_1__ZPASS_DONE__SHIFT 0xa
7285 #define PA_SC_BINNER_EVENT_CNTL_2__TGID_ROLLOVER__SHIFT 0xa
7318 #define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_MARKER__SHIFT 0xa
7350 #define PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_PRIMS_THRESHOLD__SHIFT 0xa
7360 #define PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_TRIV_REJECTED_PRIMS_THRESHOLD__SHIFT 0xa
7383 #define PA_SC_ENHANCE_2__ENABLE_VPZ_INJECTION_BEFORE_NULL_PRIMS__SHIFT 0xa
7434 #define PA_SC_BINNER_CNTL_OVERRIDE__CONTEXT_STATES_PER_BIN__SHIFT 0xa
7465 #define PA_PH_ENHANCE__ENABLE_PH_INTF_CLKEN_STRETCH__SHIFT 0xa
7518 #define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_TILE__SHIFT 0xa
7578 #define PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_OPT__SHIFT 0xa
7673 #define SQC_CONFIG__IDENTITY_HASH_SET__SHIFT 0xa
7698 #define SQ_RANDOM_WAVE_PRI__RNG__SHIFT 0xa
7725 #define SQ_DSM_CNTL__SGPR_ENABLE_SINGLE_WRITE__SHIFT 0xa
7878 #define SQG_UTCL0_CNTL2__LINE_VALID__SHIFT 0xa
8030 #define SQ_THREAD_TRACE_MASK__WTYPE_INCLUDE__SHIFT 0xa
8052 #define SQ_THREAD_TRACE_CTRL__SPI_STALL_EN__SHIFT 0xa
8183 #define SQ_EDC_CNT__SGPR_DED_COUNT__SHIFT 0xa
8260 #define SQC_ICACHE_UTCL0_CNTL2__LINE_VALID__SHIFT 0xa
8330 #define SQC_DCACHE_UTCL0_CNTL2__LINE_VALID__SHIFT 0xa
8389 #define SX_DEBUG_1__DISABLE_BLEND_OPT_DISCARD_PIXEL__SHIFT 0xa
8485 #define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_CNT__SHIFT 0xa
8901 #define TA_CNTL_AUX__ANISO_HALF_THRESH__SHIFT 0xa
9013 #define GDS_CNTL_STATUS__ORD_FIFO_BUSY__SHIFT 0xa
9050 #define GDS_PROTECTION_FAULT__SIMD_ID__SHIFT 0xa
9107 #define GDS_EDC_OA_DED__ME2_PIPE2_DED__SHIFT 0xa
9134 #define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_DATA_RAM_IRRITATOR_DATA_1__SHIFT 0xa
9162 #define GDS_EDC_OA_PHY_CNT__UNUSED1__SHIFT 0xa
9175 #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE2_PIPE_MEM_DED__SHIFT 0xa
9230 #define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE0__SHIFT 0xa
9334 #define DB_DEBUG3__DISABLE_RECOMP_TO_1ZPLANE_WITHOUT_FASTOP__SHIFT 0xa
9399 #define DB_DEBUG4__DISABLE_UNMAPPED_S_INDICATOR__SHIFT 0xa
9472 #define DB_CREDIT_LIMIT__DB_CB_LQUAD_CREDITS__SHIFT 0xa
9493 #define DB_SUBTILE_CONTROL__MSAA4_Y__SHIFT 0xa
9674 #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE10__SHIFT 0xa
10294 #define CB_HW_CONTROL_4__DISABLE_QSB_WAIT_FOR_SCORE__SHIFT 0xa
10333 #define CB_HW_CONTROL_3__DISABLE_SHADER_BLEND_OPTS__SHIFT 0xa
10454 #define CB_HW_MEM_ARBITER_RD__WEIGHT_CC__SHIFT 0xa
10481 #define CB_HW_MEM_ARBITER_WR__WEIGHT_CC__SHIFT 0xa
10593 #define GCEA_MISC__EARLYWRRET_ENABLE_VC4__SHIFT 0xa
10644 #define GCEA_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT 0xa
10715 #define GCEA_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT__SHIFT 0xa
10746 #define GCEA_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT__SHIFT 0xa
10935 #define GCEA_PROBE_MAP__CHADDR10_TO_RIGHTGL2C__SHIFT 0xa
10963 #define GCEA_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT 0xa
10990 #define SPI_PQEV_CTRL__QUEUE_DURATION__SHIFT 0xa
11040 #define GCEA_SDP_BACKDOOR_CMDCREDITS1__VC6_CREDITS_RECEIVED__SHIFT 0xa
11062 #define GCEA_SDP_BACKDOOR_DATACREDITS1__VC6_CREDITS_RECEIVED__SHIFT 0xa
11104 #define GCEA_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_START__SHIFT 0xa
11181 #define RMI_GENERAL_STATUS__TCIW_RTN_FRMTR0_BUSY__SHIFT 0xa
11238 #define RMI_SUBBLOCK_STATUS1__SKID_FIFO_1_FREE_SPACE__SHIFT 0xa
11250 #define RMI_SUBBLOCK_STATUS3__SKID_FIFO_1_FREE_SPACE_TOTAL__SHIFT 0xa
11274 #define RMI_PROBE_POP_LOGIC_CNTL__EXT_LAT_FIFO_1_MAX_DEPTH__SHIFT 0xa
11353 #define RMI_UTCL1_CNTL2__LINE_VALID__SHIFT 0xa
11544 #define RMI_CLOCK_CNTRL__DYN_CLK_RB0_WAKEUP_MASK__SHIFT 0xa
11589 #define RMI_SPARE__NOFILL_RMI_CID_CM__SHIFT 0xa
11713 #define GCR_GENERAL_CNTL__UTCL2_REQ_PERM__SHIFT 0xa
11743 #define GCR_TARGET_DISABLE__DISABLE_GL2A2_PHY__SHIFT 0xa
11805 #define UTCL1_CTRL__UTCL1_FORCE_INV_ALL__SHIFT 0xa
11854 #define UTCL1_ALOG__UTCL1_ALOG_MODE2_INTR_THRESHOLD__SHIFT 0xa
11997 #define GCVM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0xa
12101 #define GCVM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
12219 #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS__SHIFT 0xa
12275 #define GCVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID__SHIFT 0xa
12288 #define GCVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID__SHIFT 0xa
12361 #define GCVM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
12400 #define GCVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
12439 #define GCVM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
12478 #define GCVM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
12517 #define GCVM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
12556 #define GCVM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
12595 #define GCVM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
12634 #define GCVM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
12673 #define GCVM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
12712 #define GCVM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
12751 #define GCVM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
12790 #define GCVM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
12829 #define GCVM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
12868 #define GCVM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
12907 #define GCVM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
12946 #define GCVM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
12989 #define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10__SHIFT 0xa
14046 #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa
14079 #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa
14112 #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa
14145 #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa
14483 #define GCEA_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM__SHIFT 0xa
15070 #define GCEA_IO_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa
15103 #define GCEA_IO_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa
15136 #define GCEA_IO_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa
15169 #define GCEA_IO_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa
15338 #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa
15403 #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa
15533 #define GCEA_SDP_ARB_FINAL__IO_BURST_LIMIT__SHIFT 0xa
15668 #define TCP_STATUS__MEMIF_BUSY__SHIFT 0xa
15762 #define SPI_SHADER_PGM_RSRC1_PS__PRIORITY__SHIFT 0xa
15904 #define SPI_SHADER_REQ_CTRL_PS__HARD_LOCK_LOW_THRESHOLD__SHIFT 0xa
15930 #define SPI_SHADER_PREF_PRI_ACCUM_PS_0__CONTRIBUTION_HIER_SELECT__SHIFT 0xa
15946 #define SPI_SHADER_PREF_PRI_ACCUM_PS_1__CONTRIBUTION_HIER_SELECT__SHIFT 0xa
15962 #define SPI_SHADER_PREF_PRI_ACCUM_PS_2__CONTRIBUTION_HIER_SELECT__SHIFT 0xa
15978 #define SPI_SHADER_PREF_PRI_ACCUM_PS_3__CONTRIBUTION_HIER_SELECT__SHIFT 0xa
16016 #define SPI_SHADER_PGM_RSRC1_VS__PRIORITY__SHIFT 0xa
16045 #define SPI_SHADER_PGM_RSRC2_VS__SO_BASE2_EN__SHIFT 0xa
16168 #define SPI_SHADER_REQ_CTRL_VS__HARD_LOCK_LOW_THRESHOLD__SHIFT 0xa
16194 #define SPI_SHADER_PREF_PRI_ACCUM_VS_0__CONTRIBUTION_HIER_SELECT__SHIFT 0xa
16210 #define SPI_SHADER_PREF_PRI_ACCUM_VS_1__CONTRIBUTION_HIER_SELECT__SHIFT 0xa
16226 #define SPI_SHADER_PREF_PRI_ACCUM_VS_2__CONTRIBUTION_HIER_SELECT__SHIFT 0xa
16242 #define SPI_SHADER_PREF_PRI_ACCUM_VS_3__CONTRIBUTION_HIER_SELECT__SHIFT 0xa
16336 #define SPI_SHADER_PGM_RSRC1_GS__PRIORITY__SHIFT 0xa
16480 #define SPI_SHADER_REQ_CTRL_ESGS__HARD_LOCK_LOW_THRESHOLD__SHIFT 0xa
16506 #define SPI_SHADER_PREF_PRI_ACCUM_ESGS_0__CONTRIBUTION_HIER_SELECT__SHIFT 0xa
16522 #define SPI_SHADER_PREF_PRI_ACCUM_ESGS_1__CONTRIBUTION_HIER_SELECT__SHIFT 0xa
16538 #define SPI_SHADER_PREF_PRI_ACCUM_ESGS_2__CONTRIBUTION_HIER_SELECT__SHIFT 0xa
16554 #define SPI_SHADER_PREF_PRI_ACCUM_ESGS_3__CONTRIBUTION_HIER_SELECT__SHIFT 0xa
16598 #define SPI_SHADER_PGM_RSRC1_ES__PRIORITY__SHIFT 0xa
16709 #define SPI_SHADER_PGM_RSRC3_HS__GROUP_FIFO_DEPTH__SHIFT 0xa
16724 #define SPI_SHADER_PGM_RSRC1_HS__PRIORITY__SHIFT 0xa
16866 #define SPI_SHADER_REQ_CTRL_LSHS__HARD_LOCK_LOW_THRESHOLD__SHIFT 0xa
16892 #define SPI_SHADER_PREF_PRI_ACCUM_LSHS_0__CONTRIBUTION_HIER_SELECT__SHIFT 0xa
16908 #define SPI_SHADER_PREF_PRI_ACCUM_LSHS_1__CONTRIBUTION_HIER_SELECT__SHIFT 0xa
16924 #define SPI_SHADER_PREF_PRI_ACCUM_LSHS_2__CONTRIBUTION_HIER_SELECT__SHIFT 0xa
16940 #define SPI_SHADER_PREF_PRI_ACCUM_LSHS_3__CONTRIBUTION_HIER_SELECT__SHIFT 0xa
16982 #define SPI_SHADER_PGM_RSRC1_LS__PRIORITY__SHIFT 0xa
17065 #define COMPUTE_DISPATCH_INITIATOR__SCALAR_L1_INV_VOL__SHIFT 0xa
17144 #define COMPUTE_PGM_RSRC1__PRIORITY__SHIFT 0xa
17173 #define COMPUTE_PGM_RSRC2__TG_SIZE_EN__SHIFT 0xa
17276 #define COMPUTE_REQ_CTRL__HARD_LOCK_LOW_THRESHOLD__SHIFT 0xa
17293 #define COMPUTE_PREF_PRI_ACCUM_0__CONTRIBUTION_HIER_SELECT__SHIFT 0xa
17309 #define COMPUTE_PREF_PRI_ACCUM_1__CONTRIBUTION_HIER_SELECT__SHIFT 0xa
17325 #define COMPUTE_PREF_PRI_ACCUM_2__CONTRIBUTION_HIER_SELECT__SHIFT 0xa
17341 #define COMPUTE_PREF_PRI_ACCUM_3__CONTRIBUTION_HIER_SELECT__SHIFT 0xa
17433 #define COMPUTE_DISPATCH_TUNNEL__IMMEDIATE__SHIFT 0xa
17447 #define CP_EOPQ_WAIT_TIME__SCALE_COUNT__SHIFT 0xa
17483 #define CP_GFX_ERROR__QU_PIPE_UTCL1_ERROR__SHIFT 0xa
17666 #define CP_INT_CNTL__DMA_WATCH_INT_ENABLE__SHIFT 0xa
17705 #define CP_INT_STATUS__DMA_WATCH_INT_STAT__SHIFT 0xa
17922 #define CP_INT_CNTL_RING0__DMA_WATCH_INT_ENABLE__SHIFT 0xa
17959 #define CP_INT_CNTL_RING1__DMA_WATCH_INT_ENABLE__SHIFT 0xa
17994 #define CP_INT_CNTL_RING2__DMA_WATCH_INT_ENABLE__SHIFT 0xa
18031 #define CP_INT_STATUS_RING0__DMA_WATCH_INT_STAT__SHIFT 0xa
18068 #define CP_INT_STATUS_RING1__DMA_WATCH_INT_STAT__SHIFT 0xa
18103 #define CP_INT_STATUS_RING2__DMA_WATCH_INT_STAT__SHIFT 0xa
18148 #define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE2__SHIFT 0xa
18191 #define CP_ECC_FIRSTOCCURRENCE__PIPE__SHIFT 0xa
18937 #define CP_MEC1_F32_INT_DIS__GPF_INT_CPF__SHIFT 0xa
18970 #define CP_MEC2_F32_INT_DIS__GPF_INT_CPF__SHIFT 0xa
19232 #define CP_GFX_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_EN__SHIFT 0xa
19366 #define CP_DMA_WATCH0_CNTL__ANY_VMID__SHIFT 0xa
19394 #define CP_DMA_WATCH1_CNTL__ANY_VMID__SHIFT 0xa
19422 #define CP_DMA_WATCH2_CNTL__ANY_VMID__SHIFT 0xa
19450 #define CP_DMA_WATCH3_CNTL__ANY_VMID__SHIFT 0xa
19496 #define CP_RB_DOORBELL_CLEAR__MASTER_DOORBELL_EN_CLEAR__SHIFT 0xa
19594 #define CP_SD_CNTL__SDMA_EN__SHIFT 0xa
19746 #define SPI_GDBG_WAVE_CNTL3__STALL_CS5__SHIFT 0xa
20396 #define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_EN__SHIFT 0xa
20454 #define CP_HQD_HQ_STATUS0__RSVR_29_10__SHIFT 0xa
20585 #define CP_HQD_ERROR__EOP_UTCL1_ERROR__SHIFT 0xa
20653 #define CP_HQD_DEQUEUE_STATUS__DEQUEUE_STAT_EN__SHIFT 0xa
20749 #define GC_THROTTLE_CTRL__GC_EDC_PERF_COUNTER_EN__SHIFT 0xa
20780 #define GC_EDC_CTRL__EDC_THROTTLE_PATTERN_BIT_NUMS__SHIFT 0xa
20810 #define GC_THROTTLE_CTRL1__PCC_PROGRAM_UPWARDS_STEP_SIZE__SHIFT 0xa
20916 #define TCP_CNTL2__TCPI_WRITE_DATA_MGCG_DISABLE__SHIFT 0xa
20961 #define TCP_UTCL0_CNTL2__ANY_LINE_VALID__SHIFT 0xa
21022 #define TCP_PERFCOUNTER_FILTER_EN__GLC__SHIFT 0xa
21439 #define GDS_GWS_RESET0__RESOURCE10_RESET__SHIFT 0xa
21504 #define GDS_GWS_RESET1__RESOURCE42_RESET__SHIFT 0xa
21581 #define GDS_OA_RESET_MASK__ME2_PIPE2_RESET__SHIFT 0xa
21801 #define DB_RENDER_OVERRIDE__FORCE_COLOR_KILL__SHIFT 0xa
21848 #define DB_RENDER_OVERRIDE2__DEPTH_BOUNDS_HIER_DEPTH_DISABLE__SHIFT 0xa
22480 #define PA_SC_RASTER_CONFIG__PKR_XSEL__SHIFT 0xa
22620 #define CB_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT 0xa
23038 #define SPI_PS_INPUT_CNTL_0__FLAT_SHADE__SHIFT 0xa
23063 #define SPI_PS_INPUT_CNTL_1__FLAT_SHADE__SHIFT 0xa
23088 #define SPI_PS_INPUT_CNTL_2__FLAT_SHADE__SHIFT 0xa
23113 #define SPI_PS_INPUT_CNTL_3__FLAT_SHADE__SHIFT 0xa
23138 #define SPI_PS_INPUT_CNTL_4__FLAT_SHADE__SHIFT 0xa
23163 #define SPI_PS_INPUT_CNTL_5__FLAT_SHADE__SHIFT 0xa
23188 #define SPI_PS_INPUT_CNTL_6__FLAT_SHADE__SHIFT 0xa
23213 #define SPI_PS_INPUT_CNTL_7__FLAT_SHADE__SHIFT 0xa
23238 #define SPI_PS_INPUT_CNTL_8__FLAT_SHADE__SHIFT 0xa
23263 #define SPI_PS_INPUT_CNTL_9__FLAT_SHADE__SHIFT 0xa
23288 #define SPI_PS_INPUT_CNTL_10__FLAT_SHADE__SHIFT 0xa
23313 #define SPI_PS_INPUT_CNTL_11__FLAT_SHADE__SHIFT 0xa
23338 #define SPI_PS_INPUT_CNTL_12__FLAT_SHADE__SHIFT 0xa
23363 #define SPI_PS_INPUT_CNTL_13__FLAT_SHADE__SHIFT 0xa
23388 #define SPI_PS_INPUT_CNTL_14__FLAT_SHADE__SHIFT 0xa
23413 #define SPI_PS_INPUT_CNTL_15__FLAT_SHADE__SHIFT 0xa
23438 #define SPI_PS_INPUT_CNTL_16__FLAT_SHADE__SHIFT 0xa
23463 #define SPI_PS_INPUT_CNTL_17__FLAT_SHADE__SHIFT 0xa
23488 #define SPI_PS_INPUT_CNTL_18__FLAT_SHADE__SHIFT 0xa
23513 #define SPI_PS_INPUT_CNTL_19__FLAT_SHADE__SHIFT 0xa
23538 #define SPI_PS_INPUT_CNTL_20__FLAT_SHADE__SHIFT 0xa
23557 #define SPI_PS_INPUT_CNTL_21__FLAT_SHADE__SHIFT 0xa
23576 #define SPI_PS_INPUT_CNTL_22__FLAT_SHADE__SHIFT 0xa
23595 #define SPI_PS_INPUT_CNTL_23__FLAT_SHADE__SHIFT 0xa
23614 #define SPI_PS_INPUT_CNTL_24__FLAT_SHADE__SHIFT 0xa
23633 #define SPI_PS_INPUT_CNTL_25__FLAT_SHADE__SHIFT 0xa
23652 #define SPI_PS_INPUT_CNTL_26__FLAT_SHADE__SHIFT 0xa
23671 #define SPI_PS_INPUT_CNTL_27__FLAT_SHADE__SHIFT 0xa
23690 #define SPI_PS_INPUT_CNTL_28__FLAT_SHADE__SHIFT 0xa
23709 #define SPI_PS_INPUT_CNTL_29__FLAT_SHADE__SHIFT 0xa
23728 #define SPI_PS_INPUT_CNTL_30__FLAT_SHADE__SHIFT 0xa
23747 #define SPI_PS_INPUT_CNTL_31__FLAT_SHADE__SHIFT 0xa
23781 #define SPI_PS_INPUT_ENA__POS_Z_FLOAT_ENA__SHIFT 0xa
23814 #define SPI_PS_INPUT_ADDR__POS_Z_FLOAT_ENA__SHIFT 0xa
24357 #define DB_SHADER_CONTROL__EXEC_ON_NOOP__SHIFT 0xa
24466 #define PA_CL_VTE_CNTL__VTX_W0_FMT__SHIFT 0xa
24489 #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_2__SHIFT 0xa
24546 #define PA_CL_NANINF_CNTL__VS_Z_NAN_TO_INF__SHIFT 0xa
24827 #define PA_SC_MODE_CNTL_1__TILE_COVER_NO_SCISSOR__SHIFT 0xa
24915 #define VGT_DMA_INDEX_TYPE__REQ_PATH__SHIFT 0xa
24943 #define VGT_EVENT_INITIATOR__ADDRESS_HI__SHIFT 0xa
25001 #define DB_HTILE_SURFACE__RESERVED_FIELD_5__SHIFT 0xa
25113 #define VGT_SHADER_STAGES_EN__DIS_DEALLOC_ACCUM_0__SHIFT 0xa
25169 #define VGT_TF_PARAM__NUM_DS_WAVES_PER_SIMD__SHIFT 0xa
25191 #define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET1__SHIFT 0xa
25259 #define VGT_DMA_EVENT_INITIATOR__ADDRESS_HI__SHIFT 0xa
25300 #define PA_SC_LINE_CNTL__LAST_PIXEL__SHIFT 0xa
25638 #define PA_SC_BINNER_CNTL_0__CONTEXT_STATES_PER_BIN__SHIFT 0xa
25667 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__PBB_UNCERTAINTY_REGION_ENABLE__SHIFT 0xa
25774 #define CB_COLOR0_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa
25796 #define CB_COLOR0_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
25894 #define CB_COLOR1_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa
25916 #define CB_COLOR1_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
26014 #define CB_COLOR2_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa
26036 #define CB_COLOR2_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
26134 #define CB_COLOR3_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa
26156 #define CB_COLOR3_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
26254 #define CB_COLOR4_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa
26276 #define CB_COLOR4_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
26374 #define CB_COLOR5_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa
26396 #define CB_COLOR5_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
26494 #define CB_COLOR6_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa
26516 #define CB_COLOR6_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
26614 #define CB_COLOR7_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa
26636 #define CB_COLOR7_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
27325 #define CP_DMA_PFP_CONTROL__MEMLOG_CLEAR__SHIFT 0xa
27340 #define CP_DMA_ME_CONTROL__MEMLOG_CLEAR__SHIFT 0xa
27742 #define CP_ME_COHER_CNTL__CB4_DEST_BASE_ENA__SHIFT 0xa
28157 #define GDS_ATOM_CNTL__UNUSED2__SHIFT 0xa
28980 #define GUS_DRAM_COMBINE_RD_WR_EN__GROUP5_TIMER__SHIFT 0xa
29152 #define GUS_SDP_ARB_FINAL__IO_BURST_LIMIT__SHIFT 0xa
29255 #define GUS_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT 0xa
29277 #define GUS_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT 0xa
29342 #define GUS_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT 0xa
29364 #define GUS_MISC2__SA3_L1_PERF_MASK__SHIFT 0xa
29531 #define GL1_PIPE_STEER__PIPE5__SHIFT 0xa
29566 #define GL1C_CTRL__HIT_QUEUE_DISABLE__SHIFT 0xa
29586 #define GL1C_STATUS__NUM_REQ_PENDING_FROM_L2__SHIFT 0xa
29647 #define CH_PIPE_STEER__PIPE5__SHIFT 0xa
29691 #define CHC_STATUS__NUM_REQ_PENDING_FROM_L2__SHIFT 0xa
29727 #define CHCG_STATUS__NUM_REQ_PENDING_FROM_L2__SHIFT 0xa
29793 #define GL2C_CTRL2__GCR_ARB_CTRL__SHIFT 0xa
29896 #define GL2C_CTRL3__DCC_CMASK_TO_HI_PRIORITY__SHIFT 0xa
30848 #define CPG_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
30859 #define CPG_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
30868 #define CPG_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
30879 #define CPC_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
30890 #define CPC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
30899 #define CPF_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
30910 #define CPF_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
30919 #define CPF_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
30932 #define CP_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT 0xa
30939 #define CPC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
31011 #define GRBM_PERFCOUNTER0_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa
31052 #define GRBM_PERFCOUNTER1_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa
31093 #define GRBM_SE0_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa
31124 #define GRBM_SE1_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa
31155 #define GRBM_SE2_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa
31186 #define GRBM_SE3_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa
31251 #define GE_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
31262 #define GE_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
31271 #define GE_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
31282 #define GE_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
31291 #define GE_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa
31302 #define GE_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa
31311 #define GE_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa
31322 #define GE_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT 0xa
31371 #define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
31382 #define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
31391 #define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
31402 #define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
31411 #define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa
31422 #define PA_SU_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa
31431 #define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa
31442 #define PA_SU_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT 0xa
31451 #define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
31462 #define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
31492 #define SPI_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
31503 #define SPI_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
31514 #define SPI_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa
31525 #define SPI_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa
31536 #define SPI_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
31545 #define SPI_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
31554 #define SPI_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa
31563 #define SPI_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT 0xa
31761 #define GCEA_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa
31772 #define GCEA_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa
31798 #define SX_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa
31805 #define SX_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa
31812 #define SX_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa
31819 #define SX_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa
31826 #define SX_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT3__SHIFT 0xa
31831 #define SX_PERFCOUNTER1_SELECT1__PERFCOUNTER_SELECT3__SHIFT 0xa
31836 #define GDS_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
31847 #define GDS_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
31858 #define GDS_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa
31869 #define GDS_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa
31880 #define GDS_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
31889 #define TA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
31900 #define TA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
31916 #define TD_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
31927 #define TD_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
31943 #define TCP_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
31954 #define TCP_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
31963 #define TCP_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
31974 #define TCP_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
31997 #define GL2C_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
32008 #define GL2C_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
32017 #define GL2C_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
32028 #define GL2C_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
32051 #define GL2A_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
32062 #define GL2A_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
32071 #define GL2A_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
32082 #define GL2A_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
32105 #define GL1C_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
32116 #define GL1C_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
32146 #define CHC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
32157 #define CHC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
32187 #define CHCG_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
32198 #define CHCG_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
32231 #define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_ENABLE__SHIFT 0xa
32253 #define CB_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
32264 #define CB_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
32288 #define DB_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
32299 #define DB_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
32308 #define DB_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
32319 #define DB_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
32328 #define DB_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa
32339 #define DB_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa
32475 #define RLC_SPM_ACCUM_STATUS__AccumOverflow__SHIFT 0xa
32500 #define RLC_SPM_ACCUM_CTRL__RESERVED__SHIFT 0xa
32565 #define RLC_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT 0xa
32611 #define RMI_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
32622 #define RMI_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
32636 #define RMI_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa
32647 #define RMI_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa
32665 #define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_CID__SHIFT 0xa
32682 #define GCR_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
32693 #define GCR_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
32719 #define PA_PH_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
32730 #define PA_PH_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
32739 #define PA_PH_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
32750 #define PA_PH_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa
32761 #define PA_PH_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa
32784 #define PA_PH_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
32793 #define PA_PH_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa
32802 #define PA_PH_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT 0xa
32811 #define GL1A_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
32822 #define GL1A_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
32852 #define CHA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
32863 #define CHA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
32893 #define GUS_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa
32904 #define GUS_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa
33075 #define GCVML2_PERFCOUNTER2_0_SELECT__PERF_SEL1__SHIFT 0xa
33086 #define GCVML2_PERFCOUNTER2_1_SELECT__PERF_SEL1__SHIFT 0xa
33097 #define GCVML2_PERFCOUNTER2_0_SELECT1__PERF_SEL3__SHIFT 0xa
33106 #define GCVML2_PERFCOUNTER2_1_SELECT1__PERF_SEL3__SHIFT 0xa
33152 #define GC_ATC_L2_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa
33163 #define GC_ATC_L2_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa
33203 #define RLC_F32_UCODE_VERSION__THREAD1_VERSION__SHIFT 0xa
33309 #define RLC_GPM_TIMER_CTRL__TIMER_2_INT_CLEAR__SHIFT 0xa
33335 #define RLC_GPM_TIMER_STAT__TIMER_2_ENABLE_SYNC__SHIFT 0xa
34077 #define RLC_UTCL1_STATUS_2__RESERVED__SHIFT 0xa
34418 #define RLC_SPP_SHADER_PROFILE_EN__CSG_STOP_CONDITION__SHIFT 0xa
34744 #define RLC_GPM_STAT__RESTORING_REGISTERS__SHIFT 0xa
34795 #define RLC_RLCS_GPM_STAT__RESTORING_REGISTERS__SHIFT 0xa
35050 #define RLC_RLCS_POWER_BRAKE_CNTL__HYSTERESIS_CNT__SHIFT 0xa
35116 #define RLC_RLCS_POWER_BRAKE_CNTL_TH1__HYSTERESIS_CNT__SHIFT 0xa
35180 #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_10_LOADED__SHIFT 0xa
35245 #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_42_LOADED__SHIFT 0xa
35333 #define CGTS_SA0_QUAD0_CLK_MONITOR_DELAY_REG__ON_MONITOR_DELAY__SHIFT 0xa
35363 #define CGTS_SA0_QUAD1_CLK_MONITOR_DELAY_REG__ON_MONITOR_DELAY__SHIFT 0xa
35393 #define CGTS_SA1_QUAD0_CLK_MONITOR_DELAY_REG__ON_MONITOR_DELAY__SHIFT 0xa
35423 #define CGTS_SA1_QUAD1_CLK_MONITOR_DELAY_REG__ON_MONITOR_DELAY__SHIFT 0xa
35476 #define CGTS_SA0_WGP00_CU0_SIMD0_CTRL_REG__SQ0__SHIFT 0xa
35507 #define CGTS_SA0_WGP00_CU0_SIMD1_CTRL_REG__SQ1__SHIFT 0xa
35538 #define CGTS_SA0_WGP00_CU0_TATD_CTRL_REG__TD__SHIFT 0xa
35559 #define CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPI__SHIFT 0xa
35580 #define CGTS_SA0_WGP00_CU1_SIMD0_CTRL_REG__SQ0__SHIFT 0xa
35601 #define CGTS_SA0_WGP00_CU1_SIMD1_CTRL_REG__SQ1__SHIFT 0xa
35622 #define CGTS_SA0_WGP00_CU1_TATD_CTRL_REG__TD__SHIFT 0xa
35643 #define CGTS_SA0_WGP00_CU1_TCP_CTRL_REG__TCPI__SHIFT 0xa
35664 #define CGTS_SA0_WGP01_CU0_SIMD0_CTRL_REG__SQ0__SHIFT 0xa
35695 #define CGTS_SA0_WGP01_CU0_SIMD1_CTRL_REG__SQ1__SHIFT 0xa
35726 #define CGTS_SA0_WGP01_CU0_TATD_CTRL_REG__TD__SHIFT 0xa
35747 #define CGTS_SA0_WGP01_CU0_TCP_CTRL_REG__TCPI__SHIFT 0xa
35768 #define CGTS_SA0_WGP01_CU1_SIMD0_CTRL_REG__SQ0__SHIFT 0xa
35789 #define CGTS_SA0_WGP01_CU1_SIMD1_CTRL_REG__SQ1__SHIFT 0xa
35810 #define CGTS_SA0_WGP01_CU1_TATD_CTRL_REG__TD__SHIFT 0xa
35831 #define CGTS_SA0_WGP01_CU1_TCP_CTRL_REG__TCPI__SHIFT 0xa
35852 #define CGTS_SA0_WGP02_CU0_SIMD0_CTRL_REG__SQ0__SHIFT 0xa
35883 #define CGTS_SA0_WGP02_CU0_SIMD1_CTRL_REG__SQ1__SHIFT 0xa
35914 #define CGTS_SA0_WGP02_CU0_TATD_CTRL_REG__TD__SHIFT 0xa
35935 #define CGTS_SA0_WGP02_CU0_TCP_CTRL_REG__TCPI__SHIFT 0xa
35956 #define CGTS_SA0_WGP02_CU1_SIMD0_CTRL_REG__SQ0__SHIFT 0xa
35977 #define CGTS_SA0_WGP02_CU1_SIMD1_CTRL_REG__SQ1__SHIFT 0xa
35998 #define CGTS_SA0_WGP02_CU1_TATD_CTRL_REG__TD__SHIFT 0xa
36019 #define CGTS_SA0_WGP02_CU1_TCP_CTRL_REG__TCPI__SHIFT 0xa
36040 #define CGTS_SA0_WGP10_CU0_SIMD0_CTRL_REG__SQ0__SHIFT 0xa
36071 #define CGTS_SA0_WGP10_CU0_SIMD1_CTRL_REG__SQ1__SHIFT 0xa
36102 #define CGTS_SA0_WGP10_CU0_TATD_CTRL_REG__TD__SHIFT 0xa
36123 #define CGTS_SA0_WGP10_CU0_TCP_CTRL_REG__TCPI__SHIFT 0xa
36144 #define CGTS_SA0_WGP10_CU1_SIMD0_CTRL_REG__SQ0__SHIFT 0xa
36165 #define CGTS_SA0_WGP10_CU1_SIMD1_CTRL_REG__SQ1__SHIFT 0xa
36186 #define CGTS_SA0_WGP10_CU1_TATD_CTRL_REG__TD__SHIFT 0xa
36207 #define CGTS_SA0_WGP10_CU1_TCP_CTRL_REG__TCPI__SHIFT 0xa
36228 #define CGTS_SA0_WGP11_CU0_SIMD0_CTRL_REG__SQ0__SHIFT 0xa
36259 #define CGTS_SA0_WGP11_CU0_SIMD1_CTRL_REG__SQ1__SHIFT 0xa
36290 #define CGTS_SA0_WGP11_CU0_TATD_CTRL_REG__TD__SHIFT 0xa
36311 #define CGTS_SA0_WGP11_CU0_TCP_CTRL_REG__TCPI__SHIFT 0xa
36332 #define CGTS_SA0_WGP11_CU1_SIMD0_CTRL_REG__SQ0__SHIFT 0xa
36353 #define CGTS_SA0_WGP11_CU1_SIMD1_CTRL_REG__SQ1__SHIFT 0xa
36374 #define CGTS_SA0_WGP11_CU1_TATD_CTRL_REG__TD__SHIFT 0xa
36395 #define CGTS_SA0_WGP11_CU1_TCP_CTRL_REG__TCPI__SHIFT 0xa
36416 #define CGTS_SA1_WGP00_CU0_SIMD0_CTRL_REG__SQ0__SHIFT 0xa
36447 #define CGTS_SA1_WGP00_CU0_SIMD1_CTRL_REG__SQ1__SHIFT 0xa
36478 #define CGTS_SA1_WGP00_CU0_TATD_CTRL_REG__TD__SHIFT 0xa
36499 #define CGTS_SA1_WGP00_CU0_TCP_CTRL_REG__TCPI__SHIFT 0xa
36520 #define CGTS_SA1_WGP00_CU1_SIMD0_CTRL_REG__SQ0__SHIFT 0xa
36541 #define CGTS_SA1_WGP00_CU1_SIMD1_CTRL_REG__SQ1__SHIFT 0xa
36562 #define CGTS_SA1_WGP00_CU1_TATD_CTRL_REG__TD__SHIFT 0xa
36583 #define CGTS_SA1_WGP00_CU1_TCP_CTRL_REG__TCPI__SHIFT 0xa
36604 #define CGTS_SA1_WGP01_CU0_SIMD0_CTRL_REG__SQ0__SHIFT 0xa
36635 #define CGTS_SA1_WGP01_CU0_SIMD1_CTRL_REG__SQ1__SHIFT 0xa
36666 #define CGTS_SA1_WGP01_CU0_TATD_CTRL_REG__TD__SHIFT 0xa
36687 #define CGTS_SA1_WGP01_CU0_TCP_CTRL_REG__TCPI__SHIFT 0xa
36708 #define CGTS_SA1_WGP01_CU1_SIMD0_CTRL_REG__SQ0__SHIFT 0xa
36729 #define CGTS_SA1_WGP01_CU1_SIMD1_CTRL_REG__SQ1__SHIFT 0xa
36750 #define CGTS_SA1_WGP01_CU1_TATD_CTRL_REG__TD__SHIFT 0xa
36771 #define CGTS_SA1_WGP01_CU1_TCP_CTRL_REG__TCPI__SHIFT 0xa
36792 #define CGTS_SA1_WGP02_CU0_SIMD0_CTRL_REG__SQ0__SHIFT 0xa
36823 #define CGTS_SA1_WGP02_CU0_SIMD1_CTRL_REG__SQ1__SHIFT 0xa
36854 #define CGTS_SA1_WGP02_CU0_TATD_CTRL_REG__TD__SHIFT 0xa
36875 #define CGTS_SA1_WGP02_CU0_TCP_CTRL_REG__TCPI__SHIFT 0xa
36896 #define CGTS_SA1_WGP02_CU1_SIMD0_CTRL_REG__SQ0__SHIFT 0xa
36917 #define CGTS_SA1_WGP02_CU1_SIMD1_CTRL_REG__SQ1__SHIFT 0xa
36938 #define CGTS_SA1_WGP02_CU1_TATD_CTRL_REG__TD__SHIFT 0xa
36959 #define CGTS_SA1_WGP02_CU1_TCP_CTRL_REG__TCPI__SHIFT 0xa
36980 #define CGTS_SA1_WGP10_CU0_SIMD0_CTRL_REG__SQ0__SHIFT 0xa
37011 #define CGTS_SA1_WGP10_CU0_SIMD1_CTRL_REG__SQ1__SHIFT 0xa
37042 #define CGTS_SA1_WGP10_CU0_TATD_CTRL_REG__TD__SHIFT 0xa
37063 #define CGTS_SA1_WGP10_CU0_TCP_CTRL_REG__TCPI__SHIFT 0xa
37084 #define CGTS_SA1_WGP10_CU1_SIMD0_CTRL_REG__SQ0__SHIFT 0xa
37105 #define CGTS_SA1_WGP10_CU1_SIMD1_CTRL_REG__SQ1__SHIFT 0xa
37126 #define CGTS_SA1_WGP10_CU1_TATD_CTRL_REG__TD__SHIFT 0xa
37147 #define CGTS_SA1_WGP10_CU1_TCP_CTRL_REG__TCPI__SHIFT 0xa
37168 #define CGTS_SA1_WGP11_CU0_SIMD0_CTRL_REG__SQ0__SHIFT 0xa
37199 #define CGTS_SA1_WGP11_CU0_SIMD1_CTRL_REG__SQ1__SHIFT 0xa
37230 #define CGTS_SA1_WGP11_CU0_TATD_CTRL_REG__TD__SHIFT 0xa
37251 #define CGTS_SA1_WGP11_CU0_TCP_CTRL_REG__TCPI__SHIFT 0xa
37272 #define CGTS_SA1_WGP11_CU1_SIMD0_CTRL_REG__SQ0__SHIFT 0xa
37293 #define CGTS_SA1_WGP11_CU1_SIMD1_CTRL_REG__SQ1__SHIFT 0xa
37314 #define CGTS_SA1_WGP11_CU1_TATD_CTRL_REG__TD__SHIFT 0xa
37335 #define CGTS_SA1_WGP11_CU1_TCP_CTRL_REG__TCPI__SHIFT 0xa
37356 #define CGTS_SA0_WGP12_CU0_SIMD0_CTRL_REG__SQ0__SHIFT 0xa
37387 #define CGTS_SA0_WGP12_CU0_SIMD1_CTRL_REG__SQ1__SHIFT 0xa
37418 #define CGTS_SA0_WGP12_CU0_TATD_CTRL_REG__TD__SHIFT 0xa
37439 #define CGTS_SA0_WGP12_CU0_TCP_CTRL_REG__TCPI__SHIFT 0xa
37460 #define CGTS_SA0_WGP12_CU1_SIMD0_CTRL_REG__SQ0__SHIFT 0xa
37481 #define CGTS_SA0_WGP12_CU1_SIMD1_CTRL_REG__SQ1__SHIFT 0xa
37502 #define CGTS_SA0_WGP12_CU1_TATD_CTRL_REG__TD__SHIFT 0xa
37523 #define CGTS_SA0_WGP12_CU1_TCP_CTRL_REG__TCPI__SHIFT 0xa
37544 #define CGTS_SA1_WGP12_CU0_SIMD0_CTRL_REG__SQ0__SHIFT 0xa
37575 #define CGTS_SA1_WGP12_CU0_SIMD1_CTRL_REG__SQ1__SHIFT 0xa
37606 #define CGTS_SA1_WGP12_CU0_TATD_CTRL_REG__TD__SHIFT 0xa
37627 #define CGTS_SA1_WGP12_CU0_TCP_CTRL_REG__TCPI__SHIFT 0xa
37648 #define CGTS_SA1_WGP12_CU1_SIMD0_CTRL_REG__SQ0__SHIFT 0xa
37669 #define CGTS_SA1_WGP12_CU1_SIMD1_CTRL_REG__SQ1__SHIFT 0xa
37690 #define CGTS_SA1_WGP12_CU1_TATD_CTRL_REG__TD__SHIFT 0xa
37711 #define CGTS_SA1_WGP12_CU1_TCP_CTRL_REG__TCPI__SHIFT 0xa
39726 #define RLC_GPU_IOV_CFG_REG6__CNTXT_OFFSET__SHIFT 0xa
39758 #define RLC_RLCV_TIMER_STAT__TIMER_0_AUTO_REARM_SYNC__SHIFT 0xa
39807 #define RLC_CLK_CNTL__RLC_SPP_CLK_CNTL__SHIFT 0xa
39831 #define RLC_PACE_TIMER_STAT__TIMER_0_AUTO_REARM_SYNC__SHIFT 0xa
40132 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_CNTL__SHIFT 0xa
40164 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_WATERMARK__SHIFT 0xa
40202 #define SDMA0_CONTEXT_REG_TYPE2__RESERVED__SHIFT 0xa
40266 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_CNTL__SHIFT 0xa
40298 #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_WATERMARK__SHIFT 0xa
40336 #define SDMA1_CONTEXT_REG_TYPE2__RESERVED__SHIFT 0xa
40738 #define PCC_STALL_PATTERN_CTRL__PCC_BEGIN_STEP__SHIFT 0xa
40753 #define PWRBRK_STALL_PATTERN_CTRL__PWRBRK_BEGIN_STEP__SHIFT 0xa
41592 #define GC_CAC_OVRD_TD__OVRRD_VALUE__SHIFT 0xa
41612 #define GC_CAC_OVRD_UTCL2_ROUTER__OVRRD_VALUE__SHIFT 0xa
41826 #define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_3_DONE__SHIFT 0xa
42713 #define SQ_WAVE_MODE__LOD_CLAMPED__SHIFT 0xa
42738 #define SQ_WAVE_STATUS__VCCZ__SHIFT 0xa
42772 #define SQ_WAVE_TRAPSTS__SAVECTX__SHIFT 0xa
42889 #define SQ_WAVE_HW_ID1__WGP_ID__SHIFT 0xa
42933 #define SQ_WAVE_IB_STS2__FWD_PROGRESS__SHIFT 0xa
43201 #define DIDT_SQ_STALL_RELEASE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_LO__SHIFT 0xa
43475 #define DIDT_DB_STALL_RELEASE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_LO__SHIFT 0xa
43574 #define DIDT_DB_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DB2__SHIFT 0xa
43731 #define DIDT_TD_STALL_RELEASE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_LO__SHIFT 0xa
44005 #define DIDT_TCP_STALL_RELEASE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_LO__SHIFT 0xa