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8d7fb7a1 |
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11-Jun-2020 |
Tom St Denis <tom.stdenis@amd.com> |
drm/amd/amdgpu: Add SQ_DEBUG_STS_GLOBAL* registers/bits Even though they are technically MMIO registers I put the bits with the sqind block for organizational purposes. Requested for UMR debugging. Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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055e23e3 |
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09-Jun-2020 |
Tom St Denis <tom.stdenis@amd.com> |
drm/amd/amdgpu: Add SQ debug registers to GFX9/GFX10 headers (v2) Requested for UMR support. (v2): Also add reg/bits for gfx9 headers Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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98456403 |
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07-Aug-2018 |
Shaoyun Liu <Shaoyun.Liu@amd.com> |
drm/amd/include: update the bitfield define for PF_MAX_REGION Correct the definition based on vega20 register spec Signed-off-by: Shaoyun Liu <Shaoyun.Liu@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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133f9794 |
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16-Oct-2017 |
Feifei Xu <Feifei.Xu@amd.com> |
drm/amd/include: Add ip header files for vega12. Add ip header files for IPs with a delta for vg12: GC, MMHUB, OSS Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-By: Ken Wang <ken.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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