Lines Matching refs:xa
44 #define GRBM_STATUS2__ME2PIPE0_RQ_PENDING__SHIFT 0xa
473 #define CP_CPC_STATUS__TCIU_BUSY__SHIFT 0xa
508 #define CP_CPC_BUSY_STAT__MEC1_PIPE0_BUSY__SHIFT 0xa
560 #define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_READ__SHIFT 0xa
592 #define CP_CPF_STATUS__ROQ_CE_INDIRECT1_BUSY__SHIFT 0xa
699 #define CP_CPF_STALLED_STAT1__CMP_UTCL1_WAITING_ON_TRANS__SHIFT 0xa
780 #define CP_STALLED_STAT3__CE_WAITING_ON_BUFFER_DATA__SHIFT 0xa
814 #define CP_STALLED_STAT1__ME_HAS_ACTIVE_CE_BUFFER_FLAG__SHIFT 0xa
851 #define CP_STALLED_STAT2__ME_WAIT_ON_AVAIL_BUFFER__SHIFT 0xa
908 #define CP_BUSY_STAT__RCIU_ME_BUSY__SHIFT 0xa
937 #define CP_STAT__ROQ_INDIRECT1_BUSY__SHIFT 0xa
1294 #define VGT_CNTL_STATUS__VGT_PRIMGEN_BUSY__SHIFT 0xa
1526 #define PA_SC_BINNER_EVENT_CNTL_0__CONTEXT_DONE__SHIFT 0xa
1559 #define PA_SC_BINNER_EVENT_CNTL_1__ZPASS_DONE__SHIFT 0xa
1592 #define PA_SC_BINNER_EVENT_CNTL_2__TGID_ROLLOVER__SHIFT 0xa
1625 #define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_MARKER__SHIFT 0xa
1657 #define PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_PRIMS_THRESHOLD__SHIFT 0xa
1667 #define PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_TRIV_REJECTED_PRIMS_THRESHOLD__SHIFT 0xa
1758 #define PA_UTCL1_CNTL2__LINE_VALID__SHIFT 0xa
1805 #define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_TILE__SHIFT 0xa
1865 #define PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_OPT__SHIFT 0xa
1938 #define SQ_CONFIG__DEBUG_ONE_INST_CLAUSE__SHIFT 0xa
1980 #define SQC_CONFIG__IDENTITY_HASH_SET__SHIFT 0xa
2011 #define SQ_RANDOM_WAVE_PRI__RNG__SHIFT 0xa
2044 #define SQ_DSM_CNTL__SGPR_ENABLE_SINGLE_WRITE__SHIFT 0xa
2169 #define SQ_UTCL1_CNTL2__LINE_VALID__SHIFT 0xa
2491 #define SQ_EXP_0__COMPR__SHIFT 0xa
2753 #define SQ_VINTRP__ATTR__SHIFT 0xa
2988 #define SQ_THREAD_TRACE_WORD_EVENT__EVENT_TYPE__SHIFT 0xa
3023 #define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__WAVE_ID__SHIFT 0xa
3038 #define SQ_THREAD_TRACE_WORD_ISSUE__INST1__SHIFT 0xa
3074 #define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR_BANK__SHIFT 0xa
3090 #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_TYPE__SHIFT 0xa
3132 #define SQ_THREAD_TRACE_WORD_WAVE__WAVE_ID__SHIFT 0xa
3145 #define SQ_THREAD_TRACE_WORD_WAVE_START__WAVE_ID__SHIFT 0xa
3433 #define SQC_ICACHE_UTCL1_CNTL2__LINE_VALID__SHIFT 0xa
3495 #define SQC_DCACHE_UTCL1_CNTL2__LINE_VALID__SHIFT 0xa
3541 #define SX_DEBUG_1__DISABLE_BLEND_OPT_DISCARD_PIXEL__SHIFT 0xa
3580 #define SPI_DSM_CNTL2__UNUSED__SHIFT 0xa
3596 #define SPI_DEBUG_BUSY__CS4_BUSY__SHIFT 0xa
4009 #define TA_CNTL_AUX__ANISO_HALF_THRESH__SHIFT 0xa
4119 #define GDS_CNTL_STATUS__ORD_FIFO_BUSY__SHIFT 0xa
4149 #define GDS_PROTECTION_FAULT__SIMD_ID__SHIFT 0xa
4183 #define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_DATA_RAM_IRRITATOR_DATA_1__SHIFT 0xa
4247 #define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE0__SHIFT 0xa
4343 #define DB_DEBUG3__DISABLE_RECOMP_TO_1ZPLANE_WITHOUT_FASTOP__SHIFT 0xa
4408 #define DB_DEBUG4__DISABLE_UNMAPPED_S_INDICATOR__SHIFT 0xa
4445 #define DB_CREDIT_LIMIT__DB_CB_LQUAD_CREDITS__SHIFT 0xa
4472 #define DB_SUBTILE_CONTROL__MSAA4_Y__SHIFT 0xa
4501 #define DB_FIFO_DEPTH1__MCC_DEPTH__SHIFT 0xa
4543 #define DB_RMI_CACHE_POLICY__HTILE_WR__SHIFT 0xa
5268 #define CB_HW_CONTROL_3__DISABLE_SHADER_BLEND_OPTS__SHIFT 0xa
5320 #define CB_HW_MEM_ARBITER_RD__WEIGHT_CC__SHIFT 0xa
5347 #define CB_HW_MEM_ARBITER_WR__WEIGHT_CC__SHIFT 0xa
5617 #define GCEA_PROBE_MAP__CHADDR10_TO_RIGHTTCC__SHIFT 0xa
5645 #define GCEA_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT 0xa
5690 #define GCEA_SDP_BACKDOOR_CMDCREDITS1__VC6_CREDITS_RECEIVED__SHIFT 0xa
5712 #define GCEA_SDP_BACKDOOR_DATACREDITS1__VC6_CREDITS_RECEIVED__SHIFT 0xa
5766 #define RMI_GENERAL_CNTL1__POLICY_OVERRIDE__SHIFT 0xa
5788 #define RMI_GENERAL_STATUS__TCIW_RTN_FRMTR0_BUSY__SHIFT 0xa
5845 #define RMI_SUBBLOCK_STATUS1__SKID_FIFO_1_FREE_SPACE__SHIFT 0xa
5857 #define RMI_SUBBLOCK_STATUS3__SKID_FIFO_1_FREE_SPACE_TOTAL__SHIFT 0xa
5881 #define RMI_PROBE_POP_LOGIC_CNTL__EXT_LAT_FIFO_1_MAX_DEPTH__SHIFT 0xa
5956 #define RMI_UTCL1_CNTL2__LINE_VALID__SHIFT 0xa
6133 #define RMI_CLOCK_CNTRL__DYN_CLK_RB0_WAKEUP_MASK__SHIFT 0xa
6311 #define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0xa
6410 #define VM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
6526 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS__SHIFT 0xa
6582 #define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID__SHIFT 0xa
6593 #define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID__SHIFT 0xa
6642 #define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
6681 #define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
6720 #define VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
6759 #define VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
6798 #define VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
6837 #define VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
6876 #define VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
6915 #define VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
6954 #define VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
6993 #define VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
7032 #define VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
7071 #define VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
7110 #define VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
7149 #define VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
7188 #define VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
7227 #define VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
7270 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10__SHIFT 0xa
8298 #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa
8331 #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa
8364 #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa
8397 #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa
8683 #define GCEA_ADDRNORM_LIMIT_ADDR0__INTLV_NUM_DIES__SHIFT 0xa
8703 #define GCEA_ADDRNORM_LIMIT_ADDR1__INTLV_NUM_DIES__SHIFT 0xa
8725 #define GCEA_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM__SHIFT 0xa
9296 #define GCEA_IO_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa
9329 #define GCEA_IO_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa
9362 #define GCEA_IO_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa
9395 #define GCEA_IO_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa
9564 #define GCEA_IO_RD_PRI_URGENCY_MASK__CID10_MASK__SHIFT 0xa
9629 #define GCEA_IO_WR_PRI_URGENCY_MASK__CID10_MASK__SHIFT 0xa
9755 #define GCEA_SDP_ARB_FINAL__IO_BURST_LIMIT__SHIFT 0xa
9904 #define GCEA_MISC__EARLYWRRET_ENABLE_VC4__SHIFT 0xa
9955 #define GCEA_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT 0xa
10118 #define TC_CFG_L1_LOAD_POLICY0__POLICY_5__SHIFT 0xa
10151 #define TC_CFG_L1_LOAD_POLICY1__POLICY_21__SHIFT 0xa
10189 #define TC_CFG_L1_STORE_POLICY__POLICY_10__SHIFT 0xa
10249 #define TC_CFG_L2_LOAD_POLICY0__POLICY_5__SHIFT 0xa
10282 #define TC_CFG_L2_LOAD_POLICY1__POLICY_21__SHIFT 0xa
10315 #define TC_CFG_L2_STORE_POLICY0__POLICY_5__SHIFT 0xa
10348 #define TC_CFG_L2_STORE_POLICY1__POLICY_21__SHIFT 0xa
10381 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_5__SHIFT 0xa
10657 #define TCA_BURST_CTRL__SQG_DISABLE__SHIFT 0xa
10716 #define SPI_SHADER_PGM_RSRC1_PS__PRIORITY__SHIFT 0xa
10874 #define SPI_SHADER_PGM_RSRC1_VS__PRIORITY__SHIFT 0xa
10903 #define SPI_SHADER_PGM_RSRC2_VS__SO_BASE2_EN__SHIFT 0xa
11075 #define SPI_SHADER_PGM_RSRC1_GS__PRIORITY__SHIFT 0xa
11230 #define SPI_SHADER_PGM_RSRC3_HS__SIMD_DISABLE__SHIFT 0xa
11245 #define SPI_SHADER_PGM_RSRC1_HS__PRIORITY__SHIFT 0xa
11480 #define COMPUTE_DISPATCH_INITIATOR__SCALAR_L1_INV_VOL__SHIFT 0xa
11555 #define COMPUTE_PGM_RSRC1__PRIORITY__SHIFT 0xa
11582 #define COMPUTE_PGM_RSRC2__TG_SIZE_EN__SHIFT 0xa
11826 #define CP_EOPQ_WAIT_TIME__SCALE_COUNT__SHIFT 0xa
11859 #define CP_GFX_ERROR__QU_PIPE_UTCL1_ERROR__SHIFT 0xa
12468 #define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE2__SHIFT 0xa
12503 #define CP_ECC_FIRSTOCCURRENCE__PIPE__SHIFT 0xa
13167 #define CP_MEC1_F32_INT_DIS__GPF_INT_CPF__SHIFT 0xa
13186 #define CP_MEC2_F32_INT_DIS__GPF_INT_CPF__SHIFT 0xa
13267 #define CP_RB_DOORBELL_CLEAR__MASTER_DOORBELL_EN_CLEAR__SHIFT 0xa
13541 #define SPI_GDBG_WAVE_CNTL3__STALL_CS5__SHIFT 0xa
14146 #define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_EN__SHIFT 0xa
14200 #define CP_HQD_HQ_STATUS0__RSVR_29_10__SHIFT 0xa
14326 #define CP_HQD_ERROR__EOP_UTCL1_ERROR__SHIFT 0xa
14501 #define GC_THROTTLE_CTRL__PCC_THROT_INCR_STEP_INTERVAL__SHIFT 0xa
14654 #define TCP_UTCL1_CNTL2__ANY_LINE_VALID__SHIFT 0xa
14709 #define TCP_PERFCOUNTER_FILTER_EN__COMPRESSION_ENABLE__SHIFT 0xa
14993 #define GDS_GWS_RESET0__RESOURCE10_RESET__SHIFT 0xa
15058 #define GDS_GWS_RESET1__RESOURCE42_RESET__SHIFT 0xa
15131 #define GDS_OA_RESET_MASK__ME2_PIPE2_RESET__SHIFT 0xa
15567 #define DB_RENDER_OVERRIDE__FORCE_COLOR_KILL__SHIFT 0xa
15614 #define DB_RENDER_OVERRIDE2__DEPTH_BOUNDS_HIER_DEPTH_DISABLE__SHIFT 0xa
16204 #define PA_SC_RASTER_CONFIG__PKR_XSEL__SHIFT 0xa
16307 #define CB_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT 0xa
16717 #define SPI_PS_INPUT_CNTL_0__FLAT_SHADE__SHIFT 0xa
16742 #define SPI_PS_INPUT_CNTL_1__FLAT_SHADE__SHIFT 0xa
16767 #define SPI_PS_INPUT_CNTL_2__FLAT_SHADE__SHIFT 0xa
16792 #define SPI_PS_INPUT_CNTL_3__FLAT_SHADE__SHIFT 0xa
16817 #define SPI_PS_INPUT_CNTL_4__FLAT_SHADE__SHIFT 0xa
16842 #define SPI_PS_INPUT_CNTL_5__FLAT_SHADE__SHIFT 0xa
16867 #define SPI_PS_INPUT_CNTL_6__FLAT_SHADE__SHIFT 0xa
16892 #define SPI_PS_INPUT_CNTL_7__FLAT_SHADE__SHIFT 0xa
16917 #define SPI_PS_INPUT_CNTL_8__FLAT_SHADE__SHIFT 0xa
16942 #define SPI_PS_INPUT_CNTL_9__FLAT_SHADE__SHIFT 0xa
16967 #define SPI_PS_INPUT_CNTL_10__FLAT_SHADE__SHIFT 0xa
16992 #define SPI_PS_INPUT_CNTL_11__FLAT_SHADE__SHIFT 0xa
17017 #define SPI_PS_INPUT_CNTL_12__FLAT_SHADE__SHIFT 0xa
17042 #define SPI_PS_INPUT_CNTL_13__FLAT_SHADE__SHIFT 0xa
17067 #define SPI_PS_INPUT_CNTL_14__FLAT_SHADE__SHIFT 0xa
17092 #define SPI_PS_INPUT_CNTL_15__FLAT_SHADE__SHIFT 0xa
17117 #define SPI_PS_INPUT_CNTL_16__FLAT_SHADE__SHIFT 0xa
17142 #define SPI_PS_INPUT_CNTL_17__FLAT_SHADE__SHIFT 0xa
17167 #define SPI_PS_INPUT_CNTL_18__FLAT_SHADE__SHIFT 0xa
17192 #define SPI_PS_INPUT_CNTL_19__FLAT_SHADE__SHIFT 0xa
17217 #define SPI_PS_INPUT_CNTL_20__FLAT_SHADE__SHIFT 0xa
17236 #define SPI_PS_INPUT_CNTL_21__FLAT_SHADE__SHIFT 0xa
17255 #define SPI_PS_INPUT_CNTL_22__FLAT_SHADE__SHIFT 0xa
17274 #define SPI_PS_INPUT_CNTL_23__FLAT_SHADE__SHIFT 0xa
17293 #define SPI_PS_INPUT_CNTL_24__FLAT_SHADE__SHIFT 0xa
17312 #define SPI_PS_INPUT_CNTL_25__FLAT_SHADE__SHIFT 0xa
17331 #define SPI_PS_INPUT_CNTL_26__FLAT_SHADE__SHIFT 0xa
17350 #define SPI_PS_INPUT_CNTL_27__FLAT_SHADE__SHIFT 0xa
17369 #define SPI_PS_INPUT_CNTL_28__FLAT_SHADE__SHIFT 0xa
17388 #define SPI_PS_INPUT_CNTL_29__FLAT_SHADE__SHIFT 0xa
17407 #define SPI_PS_INPUT_CNTL_30__FLAT_SHADE__SHIFT 0xa
17426 #define SPI_PS_INPUT_CNTL_31__FLAT_SHADE__SHIFT 0xa
17458 #define SPI_PS_INPUT_ENA__POS_Z_FLOAT_ENA__SHIFT 0xa
17491 #define SPI_PS_INPUT_ADDR__POS_Z_FLOAT_ENA__SHIFT 0xa
18048 #define DB_SHADER_CONTROL__EXEC_ON_NOOP__SHIFT 0xa
18153 #define PA_CL_VTE_CNTL__VTX_W0_FMT__SHIFT 0xa
18176 #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_2__SHIFT 0xa
18233 #define PA_CL_NANINF_CNTL__VS_Z_NAN_TO_INF__SHIFT 0xa
18331 #define PA_STEREO_CNTL__VP_ID_MODE__SHIFT 0xa
18513 #define PA_SC_MODE_CNTL_1__TILE_COVER_NO_SCISSOR__SHIFT 0xa
18601 #define VGT_DMA_INDEX_TYPE__REQ_PATH__SHIFT 0xa
18627 #define VGT_EVENT_INITIATOR__ADDRESS_HI__SHIFT 0xa
18668 #define DB_HTILE_SURFACE__PREFETCH_HEIGHT__SHIFT 0xa
18773 #define VGT_SHADER_STAGES_EN__DIS_DEALLOC_ACCUM_0__SHIFT 0xa
18832 #define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET1__SHIFT 0xa
18898 #define VGT_DMA_EVENT_INITIATOR__ADDRESS_HI__SHIFT 0xa
18939 #define PA_SC_LINE_CNTL__LAST_PIXEL__SHIFT 0xa
19275 #define PA_SC_BINNER_CNTL_0__CONTEXT_STATES_PER_BIN__SHIFT 0xa
19302 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__PBB_UNCERTAINTY_REGION_ENABLE__SHIFT 0xa
19425 #define CB_COLOR0_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
19546 #define CB_COLOR1_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
19667 #define CB_COLOR2_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
19788 #define CB_COLOR3_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
19909 #define CB_COLOR4_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
20030 #define CB_COLOR5_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
20151 #define CB_COLOR6_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
20272 #define CB_COLOR7_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
20650 #define CP_DMA_PFP_CONTROL__MEMLOG_CLEAR__SHIFT 0xa
20661 #define CP_DMA_ME_CONTROL__MEMLOG_CLEAR__SHIFT 0xa
21004 #define CP_ME_COHER_CNTL__CB4_DEST_BASE_ENA__SHIFT 0xa
21464 #define GDS_ATOM_CNTL__UNUSED2__SHIFT 0xa
21613 #define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_CNT__SHIFT 0xa
22257 #define CPG_PERFCOUNTER1_SELECT__CNTR_SEL1__SHIFT 0xa
22268 #define CPG_PERFCOUNTER0_SELECT1__CNTR_SEL3__SHIFT 0xa
22277 #define CPG_PERFCOUNTER0_SELECT__CNTR_SEL1__SHIFT 0xa
22288 #define CPC_PERFCOUNTER1_SELECT__CNTR_SEL1__SHIFT 0xa
22299 #define CPC_PERFCOUNTER0_SELECT1__CNTR_SEL3__SHIFT 0xa
22308 #define CPF_PERFCOUNTER1_SELECT__CNTR_SEL1__SHIFT 0xa
22319 #define CPF_PERFCOUNTER0_SELECT1__CNTR_SEL3__SHIFT 0xa
22328 #define CPF_PERFCOUNTER0_SELECT__CNTR_SEL1__SHIFT 0xa
22341 #define CP_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT 0xa
22348 #define CPC_PERFCOUNTER0_SELECT__CNTR_SEL1__SHIFT 0xa
22420 #define GRBM_PERFCOUNTER0_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa
22465 #define GRBM_PERFCOUNTER1_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa
22510 #define GRBM_SE0_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa
22537 #define GRBM_SE1_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa
22564 #define GRBM_SE2_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa
22591 #define GRBM_SE3_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa
22638 #define IA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
22664 #define IA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
22673 #define VGT_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
22684 #define VGT_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
22705 #define VGT_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
22714 #define VGT_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
22726 #define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
22737 #define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
22746 #define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
22757 #define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
22780 #define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
22791 #define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
22821 #define SPI_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
22832 #define SPI_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
22843 #define SPI_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa
22854 #define SPI_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa
22865 #define SPI_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
22874 #define SPI_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
22883 #define SPI_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa
22892 #define SPI_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT 0xa
23159 #define SX_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
23170 #define SX_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
23195 #define SX_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
23204 #define SX_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
23213 #define GDS_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
23224 #define GDS_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
23235 #define GDS_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa
23246 #define GDS_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa
23257 #define GDS_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
23266 #define TA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
23277 #define TA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
23293 #define TD_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
23304 #define TD_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
23320 #define TCP_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
23331 #define TCP_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
23340 #define TCP_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
23351 #define TCP_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
23374 #define TCC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
23385 #define TCC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
23394 #define TCC_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
23405 #define TCC_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
23428 #define TCA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
23439 #define TCA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
23448 #define TCA_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
23459 #define TCA_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
23485 #define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_ENABLE__SHIFT 0xa
23507 #define CB_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
23518 #define CB_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
23542 #define DB_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
23553 #define DB_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
23562 #define DB_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
23573 #define DB_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
23582 #define DB_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa
23593 #define DB_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa
23763 #define RLC_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT 0xa
23803 #define RMI_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
23814 #define RMI_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
23828 #define RMI_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa
23839 #define RMI_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa
23857 #define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_CID__SHIFT 0xa
24139 #define RLC_GPM_TIMER_STAT__TIMER_2_ENABLE_SYNC__SHIFT 0xa
24342 #define RLC_GPM_STAT__RESTORING_REGISTERS__SHIFT 0xa
24623 #define RLC_SERDES_WR_CTRL__P1_SELECT__SHIFT 0xa
24719 #define RLC_SPM_MC_CNTL__RESERVED__SHIFT 0xa
25030 #define RLC_UTCL1_STATUS_2__RESERVED__SHIFT 0xa
25365 #define CGTS_CU0_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
25386 #define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
25407 #define CGTS_CU0_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
25428 #define CGTS_CU0_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
25449 #define CGTS_CU0_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
25470 #define CGTS_CU1_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
25491 #define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
25512 #define CGTS_CU1_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
25523 #define CGTS_CU1_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
25544 #define CGTS_CU1_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
25565 #define CGTS_CU2_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
25586 #define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
25607 #define CGTS_CU2_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
25618 #define CGTS_CU2_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
25639 #define CGTS_CU2_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
25660 #define CGTS_CU3_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
25681 #define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
25702 #define CGTS_CU3_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
25723 #define CGTS_CU3_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
25744 #define CGTS_CU3_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
25765 #define CGTS_CU4_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
25786 #define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
25807 #define CGTS_CU4_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
25818 #define CGTS_CU4_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
25839 #define CGTS_CU4_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
25860 #define CGTS_CU5_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
25881 #define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
25902 #define CGTS_CU5_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
25913 #define CGTS_CU5_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
25934 #define CGTS_CU5_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
25955 #define CGTS_CU6_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
25976 #define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
25997 #define CGTS_CU6_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
26018 #define CGTS_CU6_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
26039 #define CGTS_CU6_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
26060 #define CGTS_CU7_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
26081 #define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
26102 #define CGTS_CU7_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
26113 #define CGTS_CU7_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
26134 #define CGTS_CU7_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
26155 #define CGTS_CU8_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
26176 #define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
26197 #define CGTS_CU8_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
26208 #define CGTS_CU8_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
26229 #define CGTS_CU8_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
26250 #define CGTS_CU9_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
26271 #define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
26292 #define CGTS_CU9_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
26313 #define CGTS_CU9_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
26334 #define CGTS_CU9_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
26355 #define CGTS_CU10_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
26376 #define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
26397 #define CGTS_CU10_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
26408 #define CGTS_CU10_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
26429 #define CGTS_CU10_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
26450 #define CGTS_CU11_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
26471 #define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
26492 #define CGTS_CU11_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
26503 #define CGTS_CU11_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
26524 #define CGTS_CU11_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
26545 #define CGTS_CU12_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
26566 #define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
26587 #define CGTS_CU12_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
26608 #define CGTS_CU12_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
26629 #define CGTS_CU12_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
26650 #define CGTS_CU13_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
26671 #define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
26692 #define CGTS_CU13_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
26703 #define CGTS_CU13_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
26724 #define CGTS_CU13_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
26745 #define CGTS_CU14_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
26766 #define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
26787 #define CGTS_CU14_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
26798 #define CGTS_CU14_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
26819 #define CGTS_CU14_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
26840 #define CGTS_CU15_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
26861 #define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
26882 #define CGTS_CU15_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
26903 #define CGTS_CU15_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
26924 #define CGTS_CU15_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
26945 #define CGTS_CU0_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa
26958 #define CGTS_CU1_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa
26971 #define CGTS_CU2_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa
26984 #define CGTS_CU3_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa
26997 #define CGTS_CU4_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa
27010 #define CGTS_CU5_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa
27023 #define CGTS_CU6_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa
27036 #define CGTS_CU7_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa
27049 #define CGTS_CU8_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa
27062 #define CGTS_CU9_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa
27075 #define CGTS_CU10_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa
27088 #define CGTS_CU11_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa
27101 #define CGTS_CU12_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa
27114 #define CGTS_CU13_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa
27127 #define CGTS_CU14_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa
27140 #define CGTS_CU15_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa
28667 #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF10__SHIFT 0xa
28835 #define RLC_GPU_IOV_CFG_REG6__CNTXT_OFFSET__SHIFT 0xa
29757 #define GC_CAC_OVRD_UTCL2_ROUTER__OVRRD_VALUE__SHIFT 0xa
29927 #define SQ_WAVE_MODE__LOD_CLAMPED__SHIFT 0xa
29960 #define SQ_WAVE_STATUS__VCCZ__SHIFT 0xa
30000 #define SQ_WAVE_TRAPSTS__SAVECTX__SHIFT 0xa
30083 #define SQ_WAVE_IB_DBG0__IBUF_WPTR__SHIFT 0xa
30204 #define SQ_INTERRUPT_WORD_AUTO_HI__ENCODING__SHIFT 0xa
30233 #define SQ_INTERRUPT_WORD_CMN_HI__ENCODING__SHIFT 0xa
30257 #define SQ_INTERRUPT_WORD_WAVE_HI__ENCODING__SHIFT 0xa
30399 #define DIDT_SQ_THROTTLE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_LO__SHIFT 0xa
30616 #define DIDT_DB_THROTTLE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_LO__SHIFT 0xa
30826 #define DIDT_TD_THROTTLE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_LO__SHIFT 0xa
31043 #define DIDT_TCP_THROTTLE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_LO__SHIFT 0xa