#
8d7fb7a1 |
|
11-Jun-2020 |
Tom St Denis <tom.stdenis@amd.com> |
drm/amd/amdgpu: Add SQ_DEBUG_STS_GLOBAL* registers/bits Even though they are technically MMIO registers I put the bits with the sqind block for organizational purposes. Requested for UMR debugging. Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
055e23e3 |
|
09-Jun-2020 |
Tom St Denis <tom.stdenis@amd.com> |
drm/amd/amdgpu: Add SQ debug registers to GFX9/GFX10 headers (v2) Requested for UMR support. (v2): Also add reg/bits for gfx9 headers Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
6c33a6f4 |
|
25-Mar-2020 |
Tom St Denis <tom.stdenis@amd.com> |
drm/amd/amdgpu: Move PWR_MISC_CNTL_STATUS to its own header The register is part of the PWR block not the GC block. Move to its own header. Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
1f02c97b |
|
20-Mar-2020 |
Tom St Denis <tom.stdenis@amd.com> |
drm/amd/amdgpu: Add GFX9.1 PWR_MISC_CNTL_STATUS register to headers The registers are needed for umr and not in the headers. I left them in the gfx_v9_0.c since it includes 9.0 and 9.4 headers and including 9.1 headers would result in a lot of duplicate registers clashing. Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
8113cf9c |
|
06-Mar-2018 |
Tom St Denis <tom.stdenis@amd.com> |
drm/amd/amdgpu: re-add missing GC 9.1 and SDMA0 4.1 sh_mask header files These are required by umr to properly parse bitfield offsets. Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Alex Deucher <alexdeucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|