Lines Matching refs:xa
44 #define GRBM_STATUS2__ME2PIPE0_RQ_PENDING__SHIFT 0xa
484 #define CP_CPC_STATUS__TCIU_BUSY__SHIFT 0xa
519 #define CP_CPC_BUSY_STAT__MEC1_PIPE0_BUSY__SHIFT 0xa
571 #define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_READ__SHIFT 0xa
603 #define CP_CPF_STATUS__ROQ_CE_INDIRECT1_BUSY__SHIFT 0xa
710 #define CP_CPF_STALLED_STAT1__CMP_UTCL1_WAITING_ON_TRANS__SHIFT 0xa
778 #define CP_PRT_LOD_STATS_CNTL3__RESET_CNT__SHIFT 0xa
813 #define CP_STALLED_STAT3__CE_WAITING_ON_BUFFER_DATA__SHIFT 0xa
847 #define CP_STALLED_STAT1__ME_HAS_ACTIVE_CE_BUFFER_FLAG__SHIFT 0xa
884 #define CP_STALLED_STAT2__ME_WAIT_ON_AVAIL_BUFFER__SHIFT 0xa
941 #define CP_BUSY_STAT__RCIU_ME_BUSY__SHIFT 0xa
970 #define CP_STAT__ROQ_INDIRECT1_BUSY__SHIFT 0xa
1331 #define VGT_CNTL_STATUS__VGT_PRIMGEN_BUSY__SHIFT 0xa
1548 #define PA_SC_BINNER_EVENT_CNTL_0__CONTEXT_DONE__SHIFT 0xa
1581 #define PA_SC_BINNER_EVENT_CNTL_1__ZPASS_DONE__SHIFT 0xa
1614 #define PA_SC_BINNER_EVENT_CNTL_2__TGID_ROLLOVER__SHIFT 0xa
1647 #define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_MARKER__SHIFT 0xa
1679 #define PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_PRIMS_THRESHOLD__SHIFT 0xa
1689 #define PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_TRIV_REJECTED_PRIMS_THRESHOLD__SHIFT 0xa
1761 #define PA_UTCL1_CNTL2__LINE_VALID__SHIFT 0xa
1808 #define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_TILE__SHIFT 0xa
1868 #define PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_OPT__SHIFT 0xa
1959 #define SQC_CONFIG__IDENTITY_HASH_SET__SHIFT 0xa
1988 #define SQ_RANDOM_WAVE_PRI__RNG__SHIFT 0xa
2021 #define SQ_DSM_CNTL__SGPR_ENABLE_SINGLE_WRITE__SHIFT 0xa
2146 #define SQ_UTCL1_CNTL2__LINE_VALID__SHIFT 0xa
2409 #define SQC_EDC_CNT2__DATA_BANKA_TAG_RAM_DED_COUNT__SHIFT 0xa
2440 #define SQC_EDC_CNT3__DATA_BANKB_TAG_RAM_DED_COUNT__SHIFT 0xa
2533 #define SQ_EXP_0__COMPR__SHIFT 0xa
2795 #define SQ_VINTRP__ATTR__SHIFT 0xa
3026 #define SQC_EDC_CNT__DATA_CU1_WRITE_DATA_BUF_DED_COUNT__SHIFT 0xa
3082 #define SQ_EDC_CNT__SGPR_DED_COUNT__SHIFT 0xa
3120 #define SQ_THREAD_TRACE_WORD_EVENT__EVENT_TYPE__SHIFT 0xa
3155 #define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__WAVE_ID__SHIFT 0xa
3170 #define SQ_THREAD_TRACE_WORD_ISSUE__INST1__SHIFT 0xa
3206 #define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR_BANK__SHIFT 0xa
3222 #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_TYPE__SHIFT 0xa
3264 #define SQ_THREAD_TRACE_WORD_WAVE__WAVE_ID__SHIFT 0xa
3277 #define SQ_THREAD_TRACE_WORD_WAVE_START__WAVE_ID__SHIFT 0xa
3565 #define SQC_ICACHE_UTCL1_CNTL2__LINE_VALID__SHIFT 0xa
3629 #define SQC_DCACHE_UTCL1_CNTL2__LINE_VALID__SHIFT 0xa
3677 #define SX_DEBUG_1__DISABLE_BLEND_OPT_DISCARD_PIXEL__SHIFT 0xa
3716 #define SPI_DSM_CNTL2__UNUSED__SHIFT 0xa
4103 #define TA_CNTL_AUX__ANISO_HALF_THRESH__SHIFT 0xa
4213 #define GDS_CNTL_STATUS__ORD_FIFO_BUSY__SHIFT 0xa
4244 #define GDS_PROTECTION_FAULT__SIMD_ID__SHIFT 0xa
4299 #define GDS_EDC_OA_DED__ME2_PIPE2_DED__SHIFT 0xa
4326 #define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_DATA_RAM_IRRITATOR_DATA_1__SHIFT 0xa
4354 #define GDS_EDC_OA_PHY_CNT__UNUSED1__SHIFT 0xa
4367 #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE2_PIPE_MEM_DED__SHIFT 0xa
4422 #define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE0__SHIFT 0xa
4514 #define DB_DEBUG3__DISABLE_RECOMP_TO_1ZPLANE_WITHOUT_FASTOP__SHIFT 0xa
4579 #define DB_DEBUG4__DISABLE_UNMAPPED_S_INDICATOR__SHIFT 0xa
4612 #define DB_CREDIT_LIMIT__DB_CB_LQUAD_CREDITS__SHIFT 0xa
4639 #define DB_SUBTILE_CONTROL__MSAA4_Y__SHIFT 0xa
4668 #define DB_FIFO_DEPTH1__MCC_DEPTH__SHIFT 0xa
4710 #define DB_RMI_CACHE_POLICY__HTILE_WR__SHIFT 0xa
5435 #define CB_HW_CONTROL_3__DISABLE_SHADER_BLEND_OPTS__SHIFT 0xa
5487 #define CB_HW_MEM_ARBITER_RD__WEIGHT_CC__SHIFT 0xa
5514 #define CB_HW_MEM_ARBITER_WR__WEIGHT_CC__SHIFT 0xa
5573 #define GCEA_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT__SHIFT 0xa
5604 #define GCEA_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT__SHIFT 0xa
5785 #define GCEA_PROBE_MAP__CHADDR10_TO_RIGHTTCC__SHIFT 0xa
5814 #define GCEA_ERR_STATUS__BUSY_ON_ERROR__SHIFT 0xa
5887 #define RMI_GENERAL_CNTL1__POLICY_OVERRIDE__SHIFT 0xa
5909 #define RMI_GENERAL_STATUS__TCIW_RTN_FRMTR0_BUSY__SHIFT 0xa
5966 #define RMI_SUBBLOCK_STATUS1__SKID_FIFO_1_FREE_SPACE__SHIFT 0xa
5978 #define RMI_SUBBLOCK_STATUS3__SKID_FIFO_1_FREE_SPACE_TOTAL__SHIFT 0xa
6002 #define RMI_PROBE_POP_LOGIC_CNTL__EXT_LAT_FIFO_1_MAX_DEPTH__SHIFT 0xa
6077 #define RMI_UTCL1_CNTL2__LINE_VALID__SHIFT 0xa
6257 #define RMI_CLOCK_CNTRL__DYN_CLK_RB0_WAKEUP_MASK__SHIFT 0xa
6488 #define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0xa
6587 #define VM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
6703 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS__SHIFT 0xa
6759 #define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID__SHIFT 0xa
6770 #define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID__SHIFT 0xa
6819 #define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
6858 #define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
6897 #define VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
6936 #define VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
6975 #define VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
7014 #define VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
7053 #define VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
7092 #define VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
7131 #define VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
7170 #define VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
7209 #define VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
7248 #define VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
7287 #define VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
7326 #define VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
7365 #define VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
7404 #define VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
7447 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10__SHIFT 0xa
8467 #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa
8500 #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa
8533 #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa
8566 #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa
8844 #define GCEA_ADDRNORM_LIMIT_ADDR0__INTLV_NUM_DIES__SHIFT 0xa
8864 #define GCEA_ADDRNORM_LIMIT_ADDR1__INTLV_NUM_DIES__SHIFT 0xa
8883 #define GCEA_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM__SHIFT 0xa
9446 #define GCEA_IO_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa
9479 #define GCEA_IO_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa
9512 #define GCEA_IO_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa
9545 #define GCEA_IO_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa
9714 #define GCEA_IO_RD_PRI_URGENCY_MASK__CID10_MASK__SHIFT 0xa
9779 #define GCEA_IO_WR_PRI_URGENCY_MASK__CID10_MASK__SHIFT 0xa
9905 #define GCEA_SDP_ARB_FINAL__IO_BURST_LIMIT__SHIFT 0xa
10054 #define GCEA_MISC__EARLYWRRET_ENABLE_VC4__SHIFT 0xa
10105 #define GCEA_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT 0xa
10288 #define TC_CFG_L1_LOAD_POLICY0__POLICY_5__SHIFT 0xa
10321 #define TC_CFG_L1_LOAD_POLICY1__POLICY_21__SHIFT 0xa
10359 #define TC_CFG_L1_STORE_POLICY__POLICY_10__SHIFT 0xa
10419 #define TC_CFG_L2_LOAD_POLICY0__POLICY_5__SHIFT 0xa
10452 #define TC_CFG_L2_LOAD_POLICY1__POLICY_21__SHIFT 0xa
10485 #define TC_CFG_L2_STORE_POLICY0__POLICY_5__SHIFT 0xa
10518 #define TC_CFG_L2_STORE_POLICY1__POLICY_21__SHIFT 0xa
10551 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_5__SHIFT 0xa
10629 #define TCC_EDC_CNT__HIGH_RATE_TAG_DED_COUNT__SHIFT 0xa
10871 #define TCA_BURST_CTRL__SQG_DISABLE__SHIFT 0xa
10935 #define SPI_SHADER_PGM_RSRC1_PS__PRIORITY__SHIFT 0xa
11089 #define SPI_SHADER_PGM_RSRC1_VS__PRIORITY__SHIFT 0xa
11114 #define SPI_SHADER_PGM_RSRC2_VS__SO_BASE2_EN__SHIFT 0xa
11286 #define SPI_SHADER_PGM_RSRC1_GS__PRIORITY__SHIFT 0xa
11437 #define SPI_SHADER_PGM_RSRC3_HS__SIMD_DISABLE__SHIFT 0xa
11452 #define SPI_SHADER_PGM_RSRC1_HS__PRIORITY__SHIFT 0xa
11683 #define COMPUTE_DISPATCH_INITIATOR__SCALAR_L1_INV_VOL__SHIFT 0xa
11758 #define COMPUTE_PGM_RSRC1__PRIORITY__SHIFT 0xa
11781 #define COMPUTE_PGM_RSRC2__TG_SIZE_EN__SHIFT 0xa
12019 #define CP_EOPQ_WAIT_TIME__SCALE_COUNT__SHIFT 0xa
12053 #define CP_GFX_ERROR__QU_PIPE_UTCL1_ERROR__SHIFT 0xa
12670 #define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE2__SHIFT 0xa
12705 #define CP_ECC_FIRSTOCCURRENCE__PIPE__SHIFT 0xa
13394 #define CP_MEC1_F32_INT_DIS__GPF_INT_CPF__SHIFT 0xa
13427 #define CP_MEC2_F32_INT_DIS__GPF_INT_CPF__SHIFT 0xa
13517 #define CP_RB_DOORBELL_CLEAR__MASTER_DOORBELL_EN_CLEAR__SHIFT 0xa
14281 #define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_EN__SHIFT 0xa
14335 #define CP_HQD_HQ_STATUS0__RSVR_29_10__SHIFT 0xa
14462 #define CP_HQD_ERROR__EOP_UTCL1_ERROR__SHIFT 0xa
14600 #define GC_EDC_CTRL__UNUSED_0__SHIFT 0xa
14796 #define TCP_UTCL1_CNTL2__ANY_LINE_VALID__SHIFT 0xa
14851 #define TCP_PERFCOUNTER_FILTER_EN__COMPRESSION_ENABLE__SHIFT 0xa
15135 #define GDS_GWS_RESET0__RESOURCE10_RESET__SHIFT 0xa
15200 #define GDS_GWS_RESET1__RESOURCE42_RESET__SHIFT 0xa
15273 #define GDS_OA_RESET_MASK__ME2_PIPE2_RESET__SHIFT 0xa
15705 #define DB_RENDER_OVERRIDE__FORCE_COLOR_KILL__SHIFT 0xa
15752 #define DB_RENDER_OVERRIDE2__DEPTH_BOUNDS_HIER_DEPTH_DISABLE__SHIFT 0xa
16342 #define PA_SC_RASTER_CONFIG__PKR_XSEL__SHIFT 0xa
16842 #define SPI_PS_INPUT_CNTL_0__FLAT_SHADE__SHIFT 0xa
16867 #define SPI_PS_INPUT_CNTL_1__FLAT_SHADE__SHIFT 0xa
16892 #define SPI_PS_INPUT_CNTL_2__FLAT_SHADE__SHIFT 0xa
16917 #define SPI_PS_INPUT_CNTL_3__FLAT_SHADE__SHIFT 0xa
16942 #define SPI_PS_INPUT_CNTL_4__FLAT_SHADE__SHIFT 0xa
16967 #define SPI_PS_INPUT_CNTL_5__FLAT_SHADE__SHIFT 0xa
16992 #define SPI_PS_INPUT_CNTL_6__FLAT_SHADE__SHIFT 0xa
17017 #define SPI_PS_INPUT_CNTL_7__FLAT_SHADE__SHIFT 0xa
17042 #define SPI_PS_INPUT_CNTL_8__FLAT_SHADE__SHIFT 0xa
17067 #define SPI_PS_INPUT_CNTL_9__FLAT_SHADE__SHIFT 0xa
17092 #define SPI_PS_INPUT_CNTL_10__FLAT_SHADE__SHIFT 0xa
17117 #define SPI_PS_INPUT_CNTL_11__FLAT_SHADE__SHIFT 0xa
17142 #define SPI_PS_INPUT_CNTL_12__FLAT_SHADE__SHIFT 0xa
17167 #define SPI_PS_INPUT_CNTL_13__FLAT_SHADE__SHIFT 0xa
17192 #define SPI_PS_INPUT_CNTL_14__FLAT_SHADE__SHIFT 0xa
17217 #define SPI_PS_INPUT_CNTL_15__FLAT_SHADE__SHIFT 0xa
17242 #define SPI_PS_INPUT_CNTL_16__FLAT_SHADE__SHIFT 0xa
17267 #define SPI_PS_INPUT_CNTL_17__FLAT_SHADE__SHIFT 0xa
17292 #define SPI_PS_INPUT_CNTL_18__FLAT_SHADE__SHIFT 0xa
17317 #define SPI_PS_INPUT_CNTL_19__FLAT_SHADE__SHIFT 0xa
17342 #define SPI_PS_INPUT_CNTL_20__FLAT_SHADE__SHIFT 0xa
17361 #define SPI_PS_INPUT_CNTL_21__FLAT_SHADE__SHIFT 0xa
17380 #define SPI_PS_INPUT_CNTL_22__FLAT_SHADE__SHIFT 0xa
17399 #define SPI_PS_INPUT_CNTL_23__FLAT_SHADE__SHIFT 0xa
17418 #define SPI_PS_INPUT_CNTL_24__FLAT_SHADE__SHIFT 0xa
17437 #define SPI_PS_INPUT_CNTL_25__FLAT_SHADE__SHIFT 0xa
17456 #define SPI_PS_INPUT_CNTL_26__FLAT_SHADE__SHIFT 0xa
17475 #define SPI_PS_INPUT_CNTL_27__FLAT_SHADE__SHIFT 0xa
17494 #define SPI_PS_INPUT_CNTL_28__FLAT_SHADE__SHIFT 0xa
17513 #define SPI_PS_INPUT_CNTL_29__FLAT_SHADE__SHIFT 0xa
17532 #define SPI_PS_INPUT_CNTL_30__FLAT_SHADE__SHIFT 0xa
17551 #define SPI_PS_INPUT_CNTL_31__FLAT_SHADE__SHIFT 0xa
17583 #define SPI_PS_INPUT_ENA__POS_Z_FLOAT_ENA__SHIFT 0xa
17616 #define SPI_PS_INPUT_ADDR__POS_Z_FLOAT_ENA__SHIFT 0xa
18173 #define DB_SHADER_CONTROL__EXEC_ON_NOOP__SHIFT 0xa
18276 #define PA_CL_VTE_CNTL__VTX_W0_FMT__SHIFT 0xa
18299 #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_2__SHIFT 0xa
18356 #define PA_CL_NANINF_CNTL__VS_Z_NAN_TO_INF__SHIFT 0xa
18623 #define PA_SC_MODE_CNTL_1__TILE_COVER_NO_SCISSOR__SHIFT 0xa
18711 #define VGT_DMA_INDEX_TYPE__REQ_PATH__SHIFT 0xa
18737 #define VGT_EVENT_INITIATOR__ADDRESS_HI__SHIFT 0xa
18777 #define DB_HTILE_SURFACE__PREFETCH_HEIGHT__SHIFT 0xa
18882 #define VGT_SHADER_STAGES_EN__DIS_DEALLOC_ACCUM_0__SHIFT 0xa
18941 #define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET1__SHIFT 0xa
19007 #define VGT_DMA_EVENT_INITIATOR__ADDRESS_HI__SHIFT 0xa
19048 #define PA_SC_LINE_CNTL__LAST_PIXEL__SHIFT 0xa
19382 #define PA_SC_BINNER_CNTL_0__CONTEXT_STATES_PER_BIN__SHIFT 0xa
19407 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__PBB_UNCERTAINTY_REGION_ENABLE__SHIFT 0xa
19530 #define CB_COLOR0_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
19647 #define CB_COLOR1_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
19764 #define CB_COLOR2_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
19881 #define CB_COLOR3_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
19998 #define CB_COLOR4_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
20115 #define CB_COLOR5_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
20232 #define CB_COLOR6_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
20349 #define CB_COLOR7_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
20723 #define CP_DMA_PFP_CONTROL__MEMLOG_CLEAR__SHIFT 0xa
20734 #define CP_DMA_ME_CONTROL__MEMLOG_CLEAR__SHIFT 0xa
21077 #define CP_ME_COHER_CNTL__CB4_DEST_BASE_ENA__SHIFT 0xa
21534 #define GDS_ATOM_CNTL__UNUSED2__SHIFT 0xa
21683 #define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_CNT__SHIFT 0xa
22318 #define CPG_PERFCOUNTER1_SELECT__CNTR_SEL1__SHIFT 0xa
22329 #define CPG_PERFCOUNTER0_SELECT1__CNTR_SEL3__SHIFT 0xa
22338 #define CPG_PERFCOUNTER0_SELECT__CNTR_SEL1__SHIFT 0xa
22349 #define CPC_PERFCOUNTER1_SELECT__CNTR_SEL1__SHIFT 0xa
22360 #define CPC_PERFCOUNTER0_SELECT1__CNTR_SEL3__SHIFT 0xa
22369 #define CPF_PERFCOUNTER1_SELECT__CNTR_SEL1__SHIFT 0xa
22380 #define CPF_PERFCOUNTER0_SELECT1__CNTR_SEL3__SHIFT 0xa
22389 #define CPF_PERFCOUNTER0_SELECT__CNTR_SEL1__SHIFT 0xa
22402 #define CP_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT 0xa
22409 #define CPC_PERFCOUNTER0_SELECT__CNTR_SEL1__SHIFT 0xa
22481 #define GRBM_PERFCOUNTER0_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa
22526 #define GRBM_PERFCOUNTER1_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa
22571 #define GRBM_SE0_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa
22598 #define GRBM_SE1_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa
22625 #define GRBM_SE2_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa
22652 #define GRBM_SE3_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa
22699 #define IA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
22725 #define IA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
22734 #define VGT_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
22745 #define VGT_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
22766 #define VGT_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
22775 #define VGT_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
22787 #define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
22794 #define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
22799 #define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
22806 #define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
22821 #define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
22828 #define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
22854 #define SPI_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
22865 #define SPI_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
22876 #define SPI_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa
22887 #define SPI_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa
22898 #define SPI_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
22907 #define SPI_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
22916 #define SPI_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa
22925 #define SPI_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT 0xa
23192 #define SX_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa
23199 #define SX_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa
23206 #define SX_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa
23213 #define SX_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa
23220 #define SX_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT3__SHIFT 0xa
23225 #define SX_PERFCOUNTER1_SELECT1__PERFCOUNTER_SELECT3__SHIFT 0xa
23230 #define GDS_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa
23237 #define GDS_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa
23244 #define GDS_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa
23251 #define GDS_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa
23258 #define GDS_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT3__SHIFT 0xa
23263 #define TA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
23274 #define TA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
23283 #define TA_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
23294 #define TD_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
23305 #define TD_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
23314 #define TD_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
23325 #define TCP_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
23336 #define TCP_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
23345 #define TCP_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
23356 #define TCP_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
23379 #define TCC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
23390 #define TCC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
23399 #define TCC_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
23410 #define TCC_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
23433 #define TCA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
23444 #define TCA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
23453 #define TCA_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
23464 #define TCA_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
23490 #define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_ENABLE__SHIFT 0xa
23512 #define CB_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
23523 #define CB_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
23547 #define DB_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
23558 #define DB_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
23567 #define DB_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
23578 #define DB_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
23587 #define DB_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa
23598 #define DB_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa
23760 #define RLC_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT 0xa
23800 #define RMI_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
23811 #define RMI_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
23825 #define RMI_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa
23836 #define RMI_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa
23854 #define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_CID__SHIFT 0xa
24291 #define RLC_GPM_STAT__RESTORING_REGISTERS__SHIFT 0xa
24559 #define RLC_SERDES_WR_CTRL__P1_SELECT__SHIFT 0xa
24655 #define RLC_SPM_MC_CNTL__RESERVED__SHIFT 0xa
24967 #define RLC_UTCL1_STATUS_2__RESERVED__SHIFT 0xa
25234 #define CGTS_CU0_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
25255 #define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
25276 #define CGTS_CU0_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
25297 #define CGTS_CU0_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
25318 #define CGTS_CU0_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
25339 #define CGTS_CU1_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
25360 #define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
25381 #define CGTS_CU1_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
25392 #define CGTS_CU1_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
25413 #define CGTS_CU1_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
25434 #define CGTS_CU2_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
25455 #define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
25476 #define CGTS_CU2_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
25487 #define CGTS_CU2_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
25508 #define CGTS_CU2_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
25529 #define CGTS_CU3_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
25550 #define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
25571 #define CGTS_CU3_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
25592 #define CGTS_CU3_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
25613 #define CGTS_CU3_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
25634 #define CGTS_CU4_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
25655 #define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
25676 #define CGTS_CU4_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
25687 #define CGTS_CU4_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
25708 #define CGTS_CU4_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
25729 #define CGTS_CU5_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
25750 #define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
25771 #define CGTS_CU5_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
25782 #define CGTS_CU5_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
25803 #define CGTS_CU5_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
25824 #define CGTS_CU6_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
25845 #define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
25866 #define CGTS_CU6_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
25887 #define CGTS_CU6_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
25908 #define CGTS_CU6_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
25929 #define CGTS_CU7_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
25950 #define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
25971 #define CGTS_CU7_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
25982 #define CGTS_CU7_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
26003 #define CGTS_CU7_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
26024 #define CGTS_CU8_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
26045 #define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
26066 #define CGTS_CU8_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
26077 #define CGTS_CU8_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
26098 #define CGTS_CU8_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
26119 #define CGTS_CU9_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
26140 #define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
26161 #define CGTS_CU9_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
26182 #define CGTS_CU9_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
26203 #define CGTS_CU9_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
26224 #define CGTS_CU10_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
26245 #define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
26266 #define CGTS_CU10_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
26277 #define CGTS_CU10_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
26298 #define CGTS_CU10_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
26319 #define CGTS_CU11_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
26340 #define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
26361 #define CGTS_CU11_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
26372 #define CGTS_CU11_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
26393 #define CGTS_CU11_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
26414 #define CGTS_CU12_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
26435 #define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
26456 #define CGTS_CU12_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
26477 #define CGTS_CU12_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
26498 #define CGTS_CU12_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
26519 #define CGTS_CU13_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
26540 #define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
26561 #define CGTS_CU13_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
26572 #define CGTS_CU13_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
26593 #define CGTS_CU13_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
26614 #define CGTS_CU14_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
26635 #define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
26656 #define CGTS_CU14_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
26667 #define CGTS_CU14_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
26688 #define CGTS_CU14_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
26709 #define CGTS_CU15_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
26730 #define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
26751 #define CGTS_CU15_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
26772 #define CGTS_CU15_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
26793 #define CGTS_CU15_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
26814 #define CGTS_CU0_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa
26827 #define CGTS_CU1_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa
26840 #define CGTS_CU2_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa
26853 #define CGTS_CU3_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa
26866 #define CGTS_CU4_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa
26879 #define CGTS_CU5_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa
26892 #define CGTS_CU6_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa
26905 #define CGTS_CU7_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa
26918 #define CGTS_CU8_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa
26931 #define CGTS_CU9_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa
26944 #define CGTS_CU10_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa
26957 #define CGTS_CU11_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa
26970 #define CGTS_CU12_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa
26983 #define CGTS_CU13_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa
26996 #define CGTS_CU14_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa
27009 #define CGTS_CU15_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa
28512 #define RLC_GPU_IOV_CFG_REG6__CNTXT_OFFSET__SHIFT 0xa
29508 #define GC_CAC_OVRD_UTCL2_ROUTER__OVRRD_VALUE__SHIFT 0xa
29605 #define SQ_WAVE_MODE__LOD_CLAMPED__SHIFT 0xa
29636 #define SQ_WAVE_STATUS__VCCZ__SHIFT 0xa
29672 #define SQ_WAVE_TRAPSTS__SAVECTX__SHIFT 0xa
29755 #define SQ_WAVE_IB_DBG0__IBUF_WPTR__SHIFT 0xa
29876 #define SQ_INTERRUPT_WORD_AUTO_HI__ENCODING__SHIFT 0xa
29905 #define SQ_INTERRUPT_WORD_CMN_HI__ENCODING__SHIFT 0xa
29929 #define SQ_INTERRUPT_WORD_WAVE_HI__ENCODING__SHIFT 0xa