Lines Matching refs:xa
44 #define UVD_CGC_GATE__LBSI__SHIFT 0xa
144 #define AVM_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa
209 #define CDEFE_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa
274 #define EFC_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa
339 #define ENT_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa
404 #define IME_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa
469 #define PPU_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa
534 #define SAOE_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa
599 #define SCM_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa
664 #define SDB_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa
729 #define SIT0_NXT_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa
794 #define SIT1_NXT_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa
859 #define SIT2_NXT_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa
924 #define SIT_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa
989 #define SMPA_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa
1054 #define SMP_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa
1119 #define SRE_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa
1184 #define UVD_MPBE0_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa
1249 #define UVD_MPBE1_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa
1314 #define UVD_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa
1379 #define AVM_SUVD_CGC_GATE2__SIT_NXT_DEC__SHIFT 0xa
1404 #define CDEFE_SUVD_CGC_GATE2__SIT_NXT_DEC__SHIFT 0xa
1429 #define DBR_SUVD_CGC_GATE2__SIT_NXT_DEC__SHIFT 0xa
1454 #define ENT_SUVD_CGC_GATE2__SIT_NXT_DEC__SHIFT 0xa
1479 #define IME_SUVD_CGC_GATE2__SIT_NXT_DEC__SHIFT 0xa
1504 #define MPC1_SUVD_CGC_GATE2__SIT_NXT_DEC__SHIFT 0xa
1529 #define SAOE_SUVD_CGC_GATE2__SIT_NXT_DEC__SHIFT 0xa
1554 #define SDB_SUVD_CGC_GATE2__SIT_NXT_DEC__SHIFT 0xa
1579 #define SIT0_NXT_SUVD_CGC_GATE2__SIT_NXT_DEC__SHIFT 0xa
1604 #define SIT1_NXT_SUVD_CGC_GATE2__SIT_NXT_DEC__SHIFT 0xa
1629 #define SIT2_NXT_SUVD_CGC_GATE2__SIT_NXT_DEC__SHIFT 0xa
1654 #define SIT_SUVD_CGC_GATE2__SIT_NXT_DEC__SHIFT 0xa
1679 #define SMPA_SUVD_CGC_GATE2__SIT_NXT_DEC__SHIFT 0xa
1704 #define SMP_SUVD_CGC_GATE2__SIT_NXT_DEC__SHIFT 0xa
1729 #define SRE_SUVD_CGC_GATE2__SIT_NXT_DEC__SHIFT 0xa
1784 #define UVD_SUVD_CGC_GATE2__SIT_NXT_DEC__SHIFT 0xa
1809 #define AVM_SUVD_CGC_CTRL__EFC_MODE__SHIFT 0xa
1862 #define CDEFE_SUVD_CGC_CTRL__EFC_MODE__SHIFT 0xa
1915 #define DBR_SUVD_CGC_CTRL__EFC_MODE__SHIFT 0xa
1968 #define EFC_SUVD_CGC_CTRL__EFC_MODE__SHIFT 0xa
2021 #define ENT_SUVD_CGC_CTRL__EFC_MODE__SHIFT 0xa
2074 #define IME_SUVD_CGC_CTRL__EFC_MODE__SHIFT 0xa
2127 #define MPC1_SUVD_CGC_CTRL__EFC_MODE__SHIFT 0xa
2180 #define PPU_SUVD_CGC_CTRL__EFC_MODE__SHIFT 0xa
2233 #define SAOE_SUVD_CGC_CTRL__EFC_MODE__SHIFT 0xa
2286 #define SCM_SUVD_CGC_CTRL__EFC_MODE__SHIFT 0xa
2339 #define SDB_SUVD_CGC_CTRL__EFC_MODE__SHIFT 0xa
2392 #define SIT0_NXT_SUVD_CGC_CTRL__EFC_MODE__SHIFT 0xa
2445 #define SIT1_NXT_SUVD_CGC_CTRL__EFC_MODE__SHIFT 0xa
2498 #define SIT2_NXT_SUVD_CGC_CTRL__EFC_MODE__SHIFT 0xa
2551 #define SIT_SUVD_CGC_CTRL__EFC_MODE__SHIFT 0xa
2604 #define SMPA_SUVD_CGC_CTRL__EFC_MODE__SHIFT 0xa
2657 #define SMP_SUVD_CGC_CTRL__EFC_MODE__SHIFT 0xa
2710 #define SRE_SUVD_CGC_CTRL__EFC_MODE__SHIFT 0xa
2763 #define UVD_MPBE0_SUVD_CGC_CTRL__EFC_MODE__SHIFT 0xa
2806 #define UVD_MPBE1_SUVD_CGC_CTRL__EFC_MODE__SHIFT 0xa
2849 #define UVD_SUVD_CGC_CTRL__EFC_MODE__SHIFT 0xa
2935 #define UVD_VCPU_INT_EN__SW_RB5_INT_EN__SHIFT 0xa
2990 #define UVD_VCPU_INT_STATUS__SW_RB5_INT__SHIFT 0xa
3047 #define UVD_VCPU_INT_ACK__SW_RB5_INT_ACK__SHIFT 0xa
3593 #define UVD_SUVD_CGC_STATUS2__CDEFE_DCLK__SHIFT 0xa
3667 #define UVD_ENC_PIPE_BUSY__MDM_WR_RECON_BUSY__SHIFT 0xa
3732 #define UVD_FW_POWER_STATUS__UVDNB_PWR_OFF__SHIFT 0xa
3763 #define UVD_SOFT_RESET__IH_SOFT_RESET__SHIFT 0xa
3854 #define UVD_CGC_STATUS__REGS_VCLK__SHIFT 0xa
3919 #define UVD_CGC_UDEC_STATUS__DB_DCLK__SHIFT 0xa
3950 #define UVD_SUVD_CGC_STATUS__SCM_H264_DCLK__SHIFT 0xa
4088 #define UVD_VCPU_CNTL__TRCE_EN__SHIFT 0xa
4139 #define UVD_MP_SWAP_CNTL__MP_REF5_MC_SWAP__SHIFT 0xa
4719 #define UVD_LMI_ARB_CTRL2__MIF_RD_REQ_RET_MAX__SHIFT 0xa
4761 #define UVD_LMI_LAT_CTRL__AVG_START__SHIFT 0xa
4835 #define UVD_LMI_URGENT_CTRL__ASSERT_MC_WR_URGENT__SHIFT 0xa
4904 #define UVD_LMI_STATUS__UMC_UVD_IDLE__SHIFT 0xa
4946 #define UVD_LMI_ADP_SWAP_CNTL__CM_MC_SWAP__SHIFT 0xa
5089 #define UVD_JPEG_INT_EN__RST_ERR_EN__SHIFT 0xa
5124 #define UVD_JPEG_INT_STAT__RST_ERR_INT__SHIFT 0xa
5190 #define UVD_JPEG_TIER_CNTL2__TA__SHIFT 0xa
5856 #define UVD_JRBC0_UVD_JRBC_STATUS__RB_TRAP_STATUS__SHIFT 0xa
6020 #define UVD_JMI0_UVD_JMI_DEC_SWAP_CNTL__IB_MEM_RD_MC_SWAP__SHIFT 0xa
6132 #define UVD_JMI_LAT_CTRL__AVG_START__SHIFT 0xa
6172 #define UVD_JMI_CLEAN_STATUS__DJPEG_CORE2_READ_CLEAN__SHIFT 0xa
6226 #define JPEG_SOFT_RESET_STATUS__DJRBC2_RESET_STATUS__SHIFT 0xa
6265 #define JPEG_SYS_INT_EN__DJRBC2__SHIFT 0xa
6327 #define JPEG_SYS_INT_STATUS__DJRBC2__SHIFT 0xa
6389 #define JPEG_SYS_INT_ACK__DJRBC2__SHIFT 0xa
6451 #define JPEG_MEMCHECK_SYS_INT_EN__BSFETCH2_RD_ERR_EN__SHIFT 0xa
6529 #define JPEG_MEMCHECK_SYS_INT_STAT__BSFETCH2_RD_LO_ERR__SHIFT 0xa
6594 #define JPEG_MEMCHECK_SYS_INT_STAT1__DJRBC2_RD_LO_ERR__SHIFT 0xa
6659 #define JPEG_MEMCHECK_SYS_INT_STAT2__SCALAR_WR_HI_ERR__SHIFT 0xa
6684 #define JPEG_MEMCHECK_SYS_INT_ACK__BSFETCH2_RD_LO_ERR__SHIFT 0xa
6749 #define JPEG_MEMCHECK_SYS_INT_ACK1__DJRBC2_RD_LO_ERR__SHIFT 0xa
6814 #define JPEG_MEMCHECK_SYS_INT_ACK2__SCALAR_WR_HI_ERR__SHIFT 0xa
6881 #define JPEG_CGC_GATE__JRBBM__SHIFT 0xa
6933 #define JPEG_CGC_STATUS__JPEG5_DEC_VCLK_ACTIVE__SHIFT 0xa
6985 #define JPEG_DEC_CGC_MEM_CTRL__JPEG2_DEC_SD_EN__SHIFT 0xa
7087 #define UVD_PGFSM_CONFIG__UVDTA_PWR_CONFIG__SHIFT 0xa
7118 #define UVD_PGFSM_STATUS__UVDTA_PWR_STATUS__SHIFT 0xa
7311 #define UVD_PF_STATUS__ENCODER0_PF_CLEAR__SHIFT 0xa
7449 #define UVD_GPCNT3_CNTL__DIV__SHIFT 0xa
7498 #define VCN_FEATURES__HAS_AV1_DEC__SHIFT 0xa
7858 #define MMSCH_CNTL__MMSCH_DB_BUSY_INTR_EN__SHIFT 0xa
8003 #define MMSCH_GPUIOV_CNTXT__CNTXT_OFFSET__SHIFT 0xa
8316 #define UVD_JRBC1_UVD_JRBC_STATUS__RB_TRAP_STATUS__SHIFT 0xa
8434 #define UVD_JRBC2_UVD_JRBC_STATUS__RB_TRAP_STATUS__SHIFT 0xa
8552 #define UVD_JRBC3_UVD_JRBC_STATUS__RB_TRAP_STATUS__SHIFT 0xa
8670 #define UVD_JRBC4_UVD_JRBC_STATUS__RB_TRAP_STATUS__SHIFT 0xa
8788 #define UVD_JRBC5_UVD_JRBC_STATUS__RB_TRAP_STATUS__SHIFT 0xa
8906 #define UVD_JRBC6_UVD_JRBC_STATUS__RB_TRAP_STATUS__SHIFT 0xa
9024 #define UVD_JRBC7_UVD_JRBC_STATUS__RB_TRAP_STATUS__SHIFT 0xa
9188 #define UVD_JMI1_UVD_JMI_DEC_SWAP_CNTL__IB_MEM_RD_MC_SWAP__SHIFT 0xa
9342 #define UVD_JMI2_UVD_JMI_DEC_SWAP_CNTL__IB_MEM_RD_MC_SWAP__SHIFT 0xa
9496 #define UVD_JMI3_UVD_JMI_DEC_SWAP_CNTL__IB_MEM_RD_MC_SWAP__SHIFT 0xa
9650 #define UVD_JMI4_UVD_JMI_DEC_SWAP_CNTL__IB_MEM_RD_MC_SWAP__SHIFT 0xa
9804 #define UVD_JMI5_UVD_JMI_DEC_SWAP_CNTL__IB_MEM_RD_MC_SWAP__SHIFT 0xa
9958 #define UVD_JMI6_UVD_JMI_DEC_SWAP_CNTL__IB_MEM_RD_MC_SWAP__SHIFT 0xa
10112 #define UVD_JMI7_UVD_JMI_DEC_SWAP_CNTL__IB_MEM_RD_MC_SWAP__SHIFT 0xa
10187 #define UVD_CGC_MEM_CTRL__VCPU_LS_EN__SHIFT 0xa
10229 #define UVD_CGC_MEM_DS_CTRL__VCPU_DS_EN__SHIFT 0xa
10260 #define UVD_CGC_MEM_SD_CTRL__VCPU_SD_EN__SHIFT 0xa
10398 #define UVD_MEMCHECK_SYS_INT_EN__MIF_BSP0_ERR_EN__SHIFT 0xa
10451 #define UVD_MEMCHECK_SYS_INT_STAT__CM_LO_ERR__SHIFT 0xa
10508 #define UVD_MEMCHECK_SYS_INT_ACK__CM_LO_ACK__SHIFT 0xa
10565 #define UVD_MEMCHECK_VCPU_INT_EN__MIF_BSP0_ERR_EN__SHIFT 0xa
10618 #define UVD_MEMCHECK_VCPU_INT_STAT__CM_LO_ERR__SHIFT 0xa
10675 #define UVD_MEMCHECK_VCPU_INT_ACK__CM_LO_ACK__SHIFT 0xa
10732 #define UVD_MEMCHECK2_SYS_INT_STAT__LBSI_RD_LO_ERR__SHIFT 0xa
10781 #define UVD_MEMCHECK2_SYS_INT_ACK__LBSI_RD_LO_ACK__SHIFT 0xa
10830 #define UVD_MEMCHECK2_VCPU_INT_STAT__LBSI_RD_LO_ERR__SHIFT 0xa
10879 #define UVD_MEMCHECK2_VCPU_INT_ACK__LBSI_RD_LO_ACK__SHIFT 0xa