1/* 2 * Copyright 2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23#ifndef _smuio_13_0_6_SH_MASK_HEADER 24#define _smuio_13_0_6_SH_MASK_HEADER 25 26 27// addressBlock: smuio_smuio_reset_SmuSmuioDec 28//SMUIO_MP_RESET_INTR 29#define SMUIO_MP_RESET_INTR__SMUIO_MP_RESET_INTR__SHIFT 0x0 30#define SMUIO_MP_RESET_INTR__SMUIO_MP_RESET_INTR_MASK 0x00000001L 31//SMUIO_SOC_HALT 32#define SMUIO_SOC_HALT__WDT_FORCE_PWROK_EN__SHIFT 0x2 33#define SMUIO_SOC_HALT__WDT_FORCE_RESETn_EN__SHIFT 0x3 34#define SMUIO_SOC_HALT__WDT_FORCE_PWROK_EN_MASK 0x00000004L 35#define SMUIO_SOC_HALT__WDT_FORCE_RESETn_EN_MASK 0x00000008L 36 37 38// addressBlock: smuio_smuio_tsc_SmuSmuioDec 39//PWROK_REFCLK_GAP_CYCLES 40#define PWROK_REFCLK_GAP_CYCLES__Pwrok_PreAssertion_clkgap_cycles__SHIFT 0x0 41#define PWROK_REFCLK_GAP_CYCLES__Pwrok_PostAssertion_clkgap_cycles__SHIFT 0x8 42#define PWROK_REFCLK_GAP_CYCLES__Pwrok_PreAssertion_clkgap_cycles_MASK 0x000000FFL 43#define PWROK_REFCLK_GAP_CYCLES__Pwrok_PostAssertion_clkgap_cycles_MASK 0x0000FF00L 44//GOLDEN_TSC_INCREMENT_UPPER 45#define GOLDEN_TSC_INCREMENT_UPPER__GoldenTscIncrementUpper__SHIFT 0x0 46#define GOLDEN_TSC_INCREMENT_UPPER__GoldenTscIncrementUpper_MASK 0x00FFFFFFL 47//GOLDEN_TSC_INCREMENT_LOWER 48#define GOLDEN_TSC_INCREMENT_LOWER__GoldenTscIncrementLower__SHIFT 0x0 49#define GOLDEN_TSC_INCREMENT_LOWER__GoldenTscIncrementLower_MASK 0xFFFFFFFFL 50//GOLDEN_TSC_COUNT_UPPER 51#define GOLDEN_TSC_COUNT_UPPER__GoldenTscCountUpper__SHIFT 0x0 52#define GOLDEN_TSC_COUNT_UPPER__GoldenTscCountUpper_MASK 0x00FFFFFFL 53//GOLDEN_TSC_COUNT_LOWER 54#define GOLDEN_TSC_COUNT_LOWER__GoldenTscCountLower__SHIFT 0x0 55#define GOLDEN_TSC_COUNT_LOWER__GoldenTscCountLower_MASK 0xFFFFFFFFL 56//SOC_GOLDEN_TSC_SHADOW_UPPER 57#define SOC_GOLDEN_TSC_SHADOW_UPPER__SocGoldenTscShadowUpper__SHIFT 0x0 58#define SOC_GOLDEN_TSC_SHADOW_UPPER__SocGoldenTscShadowUpper_MASK 0x00FFFFFFL 59//SOC_GOLDEN_TSC_SHADOW_LOWER 60#define SOC_GOLDEN_TSC_SHADOW_LOWER__SocGoldenTscShadowLower__SHIFT 0x0 61#define SOC_GOLDEN_TSC_SHADOW_LOWER__SocGoldenTscShadowLower_MASK 0xFFFFFFFFL 62//SOC_GAP_PWROK 63#define SOC_GAP_PWROK__soc_gap_pwrok__SHIFT 0x0 64#define SOC_GAP_PWROK__soc_gap_pwrok_MASK 0x00000001L 65 66 67// addressBlock: smuio_smuio_swtimer_SmuSmuioDec 68//PWR_DISP_TIMER_CONTROL 69#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x0 70#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x19 71#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_DISABLE__SHIFT 0x1a 72#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_MASK__SHIFT 0x1b 73#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1c 74#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_TYPE__SHIFT 0x1d 75#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_MODE__SHIFT 0x1e 76#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x01FFFFFFL 77#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x02000000L 78#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_DISABLE_MASK 0x04000000L 79#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_MASK_MASK 0x08000000L 80#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x10000000L 81#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_TYPE_MASK 0x20000000L 82#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_MODE_MASK 0x40000000L 83//PWR_DISP_TIMER_DEBUG 84#define PWR_DISP_TIMER_DEBUG__DISP_TIMER_INT_RUNNING__SHIFT 0x0 85#define PWR_DISP_TIMER_DEBUG__DISP_TIMER_INT_STAT__SHIFT 0x1 86#define PWR_DISP_TIMER_DEBUG__DISP_TIMER_INT__SHIFT 0x2 87#define PWR_DISP_TIMER_DEBUG__DISP_TIMER_RUN_VAL__SHIFT 0x7 88#define PWR_DISP_TIMER_DEBUG__DISP_TIMER_INT_RUNNING_MASK 0x00000001L 89#define PWR_DISP_TIMER_DEBUG__DISP_TIMER_INT_STAT_MASK 0x00000002L 90#define PWR_DISP_TIMER_DEBUG__DISP_TIMER_INT_MASK 0x00000004L 91#define PWR_DISP_TIMER_DEBUG__DISP_TIMER_RUN_VAL_MASK 0xFFFFFF80L 92//PWR_DISP_TIMER2_CONTROL 93#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x0 94#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x19 95#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_DISABLE__SHIFT 0x1a 96#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_MASK__SHIFT 0x1b 97#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1c 98#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_TYPE__SHIFT 0x1d 99#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_MODE__SHIFT 0x1e 100#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x01FFFFFFL 101#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x02000000L 102#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_DISABLE_MASK 0x04000000L 103#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_MASK_MASK 0x08000000L 104#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x10000000L 105#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_TYPE_MASK 0x20000000L 106#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_MODE_MASK 0x40000000L 107//PWR_DISP_TIMER2_DEBUG 108#define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_INT_RUNNING__SHIFT 0x0 109#define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_INT_STAT__SHIFT 0x1 110#define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_INT__SHIFT 0x2 111#define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_RUN_VAL__SHIFT 0x7 112#define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_INT_RUNNING_MASK 0x00000001L 113#define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_INT_STAT_MASK 0x00000002L 114#define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_INT_MASK 0x00000004L 115#define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_RUN_VAL_MASK 0xFFFFFF80L 116//PWR_DISP_TIMER_GLOBAL_CONTROL 117#define PWR_DISP_TIMER_GLOBAL_CONTROL__DISP_TIMER_PULSE_WIDTH__SHIFT 0x0 118#define PWR_DISP_TIMER_GLOBAL_CONTROL__DISP_TIMER_PULSE_EN__SHIFT 0xa 119#define PWR_DISP_TIMER_GLOBAL_CONTROL__DISP_TIMER_PULSE_WIDTH_MASK 0x000003FFL 120#define PWR_DISP_TIMER_GLOBAL_CONTROL__DISP_TIMER_PULSE_EN_MASK 0x00000400L 121//PWR_IH_CONTROL 122#define PWR_IH_CONTROL__MAX_CREDIT__SHIFT 0x0 123#define PWR_IH_CONTROL__DISP_TIMER_TRIGGER_MASK__SHIFT 0x5 124#define PWR_IH_CONTROL__DISP_TIMER2_TRIGGER_MASK__SHIFT 0x6 125#define PWR_IH_CONTROL__PWR_IH_CLK_GATE_EN__SHIFT 0x1f 126#define PWR_IH_CONTROL__MAX_CREDIT_MASK 0x0000001FL 127#define PWR_IH_CONTROL__DISP_TIMER_TRIGGER_MASK_MASK 0x00000020L 128#define PWR_IH_CONTROL__DISP_TIMER2_TRIGGER_MASK_MASK 0x00000040L 129#define PWR_IH_CONTROL__PWR_IH_CLK_GATE_EN_MASK 0x80000000L 130 131 132// addressBlock: smuio_smuio_misc_SmuSmuioDec 133//SMUIO_MCM_CONFIG 134#define SMUIO_MCM_CONFIG__DIE_ID__SHIFT 0x0 135#define SMUIO_MCM_CONFIG__PKG_TYPE__SHIFT 0x2 136#define SMUIO_MCM_CONFIG__SOCKET_ID__SHIFT 0x8 137#define SMUIO_MCM_CONFIG__PKG_SUBTYPE__SHIFT 0xc 138#define SMUIO_MCM_CONFIG__CONSOLE_K__SHIFT 0x10 139#define SMUIO_MCM_CONFIG__CONSOLE_A__SHIFT 0x11 140#define SMUIO_MCM_CONFIG__DIE_ID_MASK 0x00000003L 141#define SMUIO_MCM_CONFIG__PKG_TYPE_MASK 0x0000001CL 142#define SMUIO_MCM_CONFIG__SOCKET_ID_MASK 0x00000300L 143#define SMUIO_MCM_CONFIG__PKG_SUBTYPE_MASK 0x00001000L 144#define SMUIO_MCM_CONFIG__CONSOLE_K_MASK 0x00010000L 145#define SMUIO_MCM_CONFIG__CONSOLE_A_MASK 0x00020000L 146//IP_DISCOVERY_VERSION 147#define IP_DISCOVERY_VERSION__IP_DISCOVERY_VERSION__SHIFT 0x0 148#define IP_DISCOVERY_VERSION__IP_DISCOVERY_VERSION_MASK 0xFFFFFFFFL 149//SCRATCH_REGISTER0 150#define SCRATCH_REGISTER0__ScratchPad0__SHIFT 0x0 151#define SCRATCH_REGISTER0__ScratchPad0_MASK 0xFFFFFFFFL 152//SCRATCH_REGISTER1 153#define SCRATCH_REGISTER1__ScratchPad1__SHIFT 0x0 154#define SCRATCH_REGISTER1__ScratchPad1_MASK 0xFFFFFFFFL 155//SCRATCH_REGISTER2 156#define SCRATCH_REGISTER2__ScratchPad2__SHIFT 0x0 157#define SCRATCH_REGISTER2__ScratchPad2_MASK 0xFFFFFFFFL 158//SCRATCH_REGISTER3 159#define SCRATCH_REGISTER3__ScratchPad3__SHIFT 0x0 160#define SCRATCH_REGISTER3__ScratchPad3_MASK 0xFFFFFFFFL 161//SCRATCH_REGISTER4 162#define SCRATCH_REGISTER4__ScratchPad4__SHIFT 0x0 163#define SCRATCH_REGISTER4__ScratchPad4_MASK 0xFFFFFFFFL 164//SCRATCH_REGISTER5 165#define SCRATCH_REGISTER5__ScratchPad5__SHIFT 0x0 166#define SCRATCH_REGISTER5__ScratchPad5_MASK 0xFFFFFFFFL 167//SCRATCH_REGISTER6 168#define SCRATCH_REGISTER6__ScratchPad6__SHIFT 0x0 169#define SCRATCH_REGISTER6__ScratchPad6_MASK 0xFFFFFFFFL 170//SCRATCH_REGISTER7 171#define SCRATCH_REGISTER7__ScratchPad7__SHIFT 0x0 172#define SCRATCH_REGISTER7__ScratchPad7_MASK 0xFFFFFFFFL 173 174 175// addressBlock: smuio_smuio_i2c_SmuSmuioDec 176//CKSVII2C_IC_CON 177#define CKSVII2C_IC_CON__IC_MASTER_MODE__SHIFT 0x0 178#define CKSVII2C_IC_CON__IC_MAX_SPEED_MODE__SHIFT 0x1 179#define CKSVII2C_IC_CON__IC_10BITADDR_SLAVE__SHIFT 0x3 180#define CKSVII2C_IC_CON__IC_10BITADDR_MASTER__SHIFT 0x4 181#define CKSVII2C_IC_CON__IC_RESTART_EN__SHIFT 0x5 182#define CKSVII2C_IC_CON__IC_SLAVE_DISABLE__SHIFT 0x6 183#define CKSVII2C_IC_CON__STOP_DET_IFADDRESSED__SHIFT 0x7 184#define CKSVII2C_IC_CON__TX_EMPTY_CTRL__SHIFT 0x8 185#define CKSVII2C_IC_CON__RX_FIFO_FULL_HLD_CTRL__SHIFT 0x9 186#define CKSVII2C_IC_CON__BUS_CLEAR_FEATURE_CTRL__SHIFT 0xb 187#define CKSVII2C_IC_CON__IC_MASTER_MODE_MASK 0x00000001L 188#define CKSVII2C_IC_CON__IC_MAX_SPEED_MODE_MASK 0x00000006L 189#define CKSVII2C_IC_CON__IC_10BITADDR_SLAVE_MASK 0x00000008L 190#define CKSVII2C_IC_CON__IC_10BITADDR_MASTER_MASK 0x00000010L 191#define CKSVII2C_IC_CON__IC_RESTART_EN_MASK 0x00000020L 192#define CKSVII2C_IC_CON__IC_SLAVE_DISABLE_MASK 0x00000040L 193#define CKSVII2C_IC_CON__STOP_DET_IFADDRESSED_MASK 0x00000080L 194#define CKSVII2C_IC_CON__TX_EMPTY_CTRL_MASK 0x00000100L 195#define CKSVII2C_IC_CON__RX_FIFO_FULL_HLD_CTRL_MASK 0x00000200L 196#define CKSVII2C_IC_CON__BUS_CLEAR_FEATURE_CTRL_MASK 0x00000800L 197//CKSVII2C_IC_TAR 198#define CKSVII2C_IC_TAR__IC_TAR__SHIFT 0x0 199#define CKSVII2C_IC_TAR__GC_OR_START__SHIFT 0xa 200#define CKSVII2C_IC_TAR__SPECIAL__SHIFT 0xb 201#define CKSVII2C_IC_TAR__IC_10BITADDR_MASTER__SHIFT 0xc 202#define CKSVII2C_IC_TAR__IC_TAR_MASK 0x000003FFL 203#define CKSVII2C_IC_TAR__GC_OR_START_MASK 0x00000400L 204#define CKSVII2C_IC_TAR__SPECIAL_MASK 0x00000800L 205#define CKSVII2C_IC_TAR__IC_10BITADDR_MASTER_MASK 0x00001000L 206//CKSVII2C_IC_SAR 207#define CKSVII2C_IC_SAR__IC_SAR__SHIFT 0x0 208#define CKSVII2C_IC_SAR__IC_SAR_MASK 0x000003FFL 209//CKSVII2C_IC_HS_MADDR 210#define CKSVII2C_IC_HS_MADDR__IC_HS_MADDR__SHIFT 0x0 211#define CKSVII2C_IC_HS_MADDR__IC_HS_MADDR_MASK 0x00000007L 212//CKSVII2C_IC_DATA_CMD 213#define CKSVII2C_IC_DATA_CMD__DAT__SHIFT 0x0 214#define CKSVII2C_IC_DATA_CMD__CMD__SHIFT 0x8 215#define CKSVII2C_IC_DATA_CMD__STOP__SHIFT 0x9 216#define CKSVII2C_IC_DATA_CMD__RESTART__SHIFT 0xa 217#define CKSVII2C_IC_DATA_CMD__FIRST_DATA_BYTE__SHIFT 0xb 218#define CKSVII2C_IC_DATA_CMD__DAT_MASK 0x000000FFL 219#define CKSVII2C_IC_DATA_CMD__CMD_MASK 0x00000100L 220#define CKSVII2C_IC_DATA_CMD__STOP_MASK 0x00000200L 221#define CKSVII2C_IC_DATA_CMD__RESTART_MASK 0x00000400L 222#define CKSVII2C_IC_DATA_CMD__FIRST_DATA_BYTE_MASK 0x00000800L 223//CKSVII2C_IC_SS_SCL_HCNT 224#define CKSVII2C_IC_SS_SCL_HCNT__IC_SS_SCL_HCNT__SHIFT 0x0 225#define CKSVII2C_IC_SS_SCL_HCNT__IC_SS_SCL_HCNT_MASK 0x0000FFFFL 226//CKSVII2C_IC_SS_SCL_LCNT 227#define CKSVII2C_IC_SS_SCL_LCNT__IC_SS_SCL_LCNT__SHIFT 0x0 228#define CKSVII2C_IC_SS_SCL_LCNT__IC_SS_SCL_LCNT_MASK 0x0000FFFFL 229//CKSVII2C_IC_FS_SCL_HCNT 230#define CKSVII2C_IC_FS_SCL_HCNT__IC_FS_SCL_HCNT__SHIFT 0x0 231#define CKSVII2C_IC_FS_SCL_HCNT__IC_FS_SCL_HCNT_MASK 0x0000FFFFL 232//CKSVII2C_IC_FS_SCL_LCNT 233#define CKSVII2C_IC_FS_SCL_LCNT__IC_FS_SCL_LCNT__SHIFT 0x0 234#define CKSVII2C_IC_FS_SCL_LCNT__IC_FS_SCL_LCNT_MASK 0x0000FFFFL 235//CKSVII2C_IC_HS_SCL_HCNT 236#define CKSVII2C_IC_HS_SCL_HCNT__IC_HS_SCL_HCNT__SHIFT 0x0 237#define CKSVII2C_IC_HS_SCL_HCNT__IC_HS_SCL_HCNT_MASK 0x0000FFFFL 238//CKSVII2C_IC_HS_SCL_LCNT 239#define CKSVII2C_IC_HS_SCL_LCNT__IC_HS_SCL_LCNT__SHIFT 0x0 240#define CKSVII2C_IC_HS_SCL_LCNT__IC_HS_SCL_LCNT_MASK 0x0000FFFFL 241//CKSVII2C_IC_INTR_STAT 242#define CKSVII2C_IC_INTR_STAT__R_RX_UNDER__SHIFT 0x0 243#define CKSVII2C_IC_INTR_STAT__R_RX_OVER__SHIFT 0x1 244#define CKSVII2C_IC_INTR_STAT__R_RX_FULL__SHIFT 0x2 245#define CKSVII2C_IC_INTR_STAT__R_TX_OVER__SHIFT 0x3 246#define CKSVII2C_IC_INTR_STAT__R_TX_EMPTY__SHIFT 0x4 247#define CKSVII2C_IC_INTR_STAT__R_RD_REQ__SHIFT 0x5 248#define CKSVII2C_IC_INTR_STAT__R_TX_ABRT__SHIFT 0x6 249#define CKSVII2C_IC_INTR_STAT__R_RX_DONE__SHIFT 0x7 250#define CKSVII2C_IC_INTR_STAT__R_ACTIVITY__SHIFT 0x8 251#define CKSVII2C_IC_INTR_STAT__R_STOP_DET__SHIFT 0x9 252#define CKSVII2C_IC_INTR_STAT__R_START_DET__SHIFT 0xa 253#define CKSVII2C_IC_INTR_STAT__R_GEN_CALL__SHIFT 0xb 254#define CKSVII2C_IC_INTR_STAT__R_RESTART_DET__SHIFT 0xc 255#define CKSVII2C_IC_INTR_STAT__R_MST_ON_HOLD__SHIFT 0xd 256#define CKSVII2C_IC_INTR_STAT__R_SCL_STUCK_AT_LOW__SHIFT 0xe 257#define CKSVII2C_IC_INTR_STAT__R_RX_UNDER_MASK 0x00000001L 258#define CKSVII2C_IC_INTR_STAT__R_RX_OVER_MASK 0x00000002L 259#define CKSVII2C_IC_INTR_STAT__R_RX_FULL_MASK 0x00000004L 260#define CKSVII2C_IC_INTR_STAT__R_TX_OVER_MASK 0x00000008L 261#define CKSVII2C_IC_INTR_STAT__R_TX_EMPTY_MASK 0x00000010L 262#define CKSVII2C_IC_INTR_STAT__R_RD_REQ_MASK 0x00000020L 263#define CKSVII2C_IC_INTR_STAT__R_TX_ABRT_MASK 0x00000040L 264#define CKSVII2C_IC_INTR_STAT__R_RX_DONE_MASK 0x00000080L 265#define CKSVII2C_IC_INTR_STAT__R_ACTIVITY_MASK 0x00000100L 266#define CKSVII2C_IC_INTR_STAT__R_STOP_DET_MASK 0x00000200L 267#define CKSVII2C_IC_INTR_STAT__R_START_DET_MASK 0x00000400L 268#define CKSVII2C_IC_INTR_STAT__R_GEN_CALL_MASK 0x00000800L 269#define CKSVII2C_IC_INTR_STAT__R_RESTART_DET_MASK 0x00001000L 270#define CKSVII2C_IC_INTR_STAT__R_MST_ON_HOLD_MASK 0x00002000L 271#define CKSVII2C_IC_INTR_STAT__R_SCL_STUCK_AT_LOW_MASK 0x00004000L 272//CKSVII2C_IC_INTR_MASK 273#define CKSVII2C_IC_INTR_MASK__M_RX_UNDER__SHIFT 0x0 274#define CKSVII2C_IC_INTR_MASK__M_RX_OVER__SHIFT 0x1 275#define CKSVII2C_IC_INTR_MASK__M_RX_FULL__SHIFT 0x2 276#define CKSVII2C_IC_INTR_MASK__M_TX_OVER__SHIFT 0x3 277#define CKSVII2C_IC_INTR_MASK__M_TX_EMPTY__SHIFT 0x4 278#define CKSVII2C_IC_INTR_MASK__M_RD_REQ__SHIFT 0x5 279#define CKSVII2C_IC_INTR_MASK__M_TX_ABRT__SHIFT 0x6 280#define CKSVII2C_IC_INTR_MASK__M_RX_DONE__SHIFT 0x7 281#define CKSVII2C_IC_INTR_MASK__M_ACTIVITY__SHIFT 0x8 282#define CKSVII2C_IC_INTR_MASK__M_STOP_DET__SHIFT 0x9 283#define CKSVII2C_IC_INTR_MASK__M_START_DET__SHIFT 0xa 284#define CKSVII2C_IC_INTR_MASK__M_GEN_CALL__SHIFT 0xb 285#define CKSVII2C_IC_INTR_MASK__M_RESTART_DET__SHIFT 0xc 286#define CKSVII2C_IC_INTR_MASK__M_MST_ON_HOLD__SHIFT 0xd 287#define CKSVII2C_IC_INTR_MASK__M_SCL_STUCK_AT_LOW__SHIFT 0xe 288#define CKSVII2C_IC_INTR_MASK__M_RX_UNDER_MASK 0x00000001L 289#define CKSVII2C_IC_INTR_MASK__M_RX_OVER_MASK 0x00000002L 290#define CKSVII2C_IC_INTR_MASK__M_RX_FULL_MASK 0x00000004L 291#define CKSVII2C_IC_INTR_MASK__M_TX_OVER_MASK 0x00000008L 292#define CKSVII2C_IC_INTR_MASK__M_TX_EMPTY_MASK 0x00000010L 293#define CKSVII2C_IC_INTR_MASK__M_RD_REQ_MASK 0x00000020L 294#define CKSVII2C_IC_INTR_MASK__M_TX_ABRT_MASK 0x00000040L 295#define CKSVII2C_IC_INTR_MASK__M_RX_DONE_MASK 0x00000080L 296#define CKSVII2C_IC_INTR_MASK__M_ACTIVITY_MASK 0x00000100L 297#define CKSVII2C_IC_INTR_MASK__M_STOP_DET_MASK 0x00000200L 298#define CKSVII2C_IC_INTR_MASK__M_START_DET_MASK 0x00000400L 299#define CKSVII2C_IC_INTR_MASK__M_GEN_CALL_MASK 0x00000800L 300#define CKSVII2C_IC_INTR_MASK__M_RESTART_DET_MASK 0x00001000L 301#define CKSVII2C_IC_INTR_MASK__M_MST_ON_HOLD_MASK 0x00002000L 302#define CKSVII2C_IC_INTR_MASK__M_SCL_STUCK_AT_LOW_MASK 0x00004000L 303//CKSVII2C_IC_RAW_INTR_STAT 304//CKSVII2C_IC_RX_TL 305#define CKSVII2C_IC_RX_TL__RX_TL__SHIFT 0x0 306#define CKSVII2C_IC_RX_TL__RX_TL_MASK 0x000000FFL 307//CKSVII2C_IC_TX_TL 308#define CKSVII2C_IC_TX_TL__TX_TL__SHIFT 0x0 309#define CKSVII2C_IC_TX_TL__TX_TL_MASK 0x000000FFL 310//CKSVII2C_IC_CLR_INTR 311//CKSVII2C_IC_CLR_RX_UNDER 312//CKSVII2C_IC_CLR_RX_OVER 313//CKSVII2C_IC_CLR_TX_OVER 314//CKSVII2C_IC_CLR_RD_REQ 315//CKSVII2C_IC_CLR_TX_ABRT 316//CKSVII2C_IC_CLR_RX_DONE 317//CKSVII2C_IC_CLR_ACTIVITY 318//CKSVII2C_IC_CLR_STOP_DET 319//CKSVII2C_IC_CLR_START_DET 320//CKSVII2C_IC_CLR_GEN_CALL 321//CKSVII2C_IC_ENABLE 322#define CKSVII2C_IC_ENABLE__ENABLE__SHIFT 0x0 323#define CKSVII2C_IC_ENABLE__ABORT__SHIFT 0x1 324#define CKSVII2C_IC_ENABLE__TX_CMD_BLOCK__SHIFT 0x2 325#define CKSVII2C_IC_ENABLE__SDA_STUCK_RECOVERY_ENABLE__SHIFT 0x3 326#define CKSVII2C_IC_ENABLE__ENABLE_MASK 0x00000001L 327#define CKSVII2C_IC_ENABLE__ABORT_MASK 0x00000002L 328#define CKSVII2C_IC_ENABLE__TX_CMD_BLOCK_MASK 0x00000004L 329#define CKSVII2C_IC_ENABLE__SDA_STUCK_RECOVERY_ENABLE_MASK 0x00000008L 330//CKSVII2C_IC_STATUS 331#define CKSVII2C_IC_STATUS__ACTIVITY__SHIFT 0x0 332#define CKSVII2C_IC_STATUS__TFNF__SHIFT 0x1 333#define CKSVII2C_IC_STATUS__TFE__SHIFT 0x2 334#define CKSVII2C_IC_STATUS__RFNE__SHIFT 0x3 335#define CKSVII2C_IC_STATUS__RFF__SHIFT 0x4 336#define CKSVII2C_IC_STATUS__MST_ACTIVITY__SHIFT 0x5 337#define CKSVII2C_IC_STATUS__SLV_ACTIVITY__SHIFT 0x6 338#define CKSVII2C_IC_STATUS__MST_HOLD_TX_FIFO_EMPTY__SHIFT 0x7 339#define CKSVII2C_IC_STATUS__MST_HOLD_RX_FIFO_FULL__SHIFT 0x8 340#define CKSVII2C_IC_STATUS__SLV_HOLD_TX_FIFO_EMPTY__SHIFT 0x9 341#define CKSVII2C_IC_STATUS__SLV_HOLD_RX_FIFO_FULL__SHIFT 0xa 342#define CKSVII2C_IC_STATUS__SDA_STUCK_NOT_RECOVERED__SHIFT 0xb 343#define CKSVII2C_IC_STATUS__ACTIVITY_MASK 0x00000001L 344#define CKSVII2C_IC_STATUS__TFNF_MASK 0x00000002L 345#define CKSVII2C_IC_STATUS__TFE_MASK 0x00000004L 346#define CKSVII2C_IC_STATUS__RFNE_MASK 0x00000008L 347#define CKSVII2C_IC_STATUS__RFF_MASK 0x00000010L 348#define CKSVII2C_IC_STATUS__MST_ACTIVITY_MASK 0x00000020L 349#define CKSVII2C_IC_STATUS__SLV_ACTIVITY_MASK 0x00000040L 350#define CKSVII2C_IC_STATUS__MST_HOLD_TX_FIFO_EMPTY_MASK 0x00000080L 351#define CKSVII2C_IC_STATUS__MST_HOLD_RX_FIFO_FULL_MASK 0x00000100L 352#define CKSVII2C_IC_STATUS__SLV_HOLD_TX_FIFO_EMPTY_MASK 0x00000200L 353#define CKSVII2C_IC_STATUS__SLV_HOLD_RX_FIFO_FULL_MASK 0x00000400L 354#define CKSVII2C_IC_STATUS__SDA_STUCK_NOT_RECOVERED_MASK 0x00000800L 355//CKSVII2C_IC_TXFLR 356#define CKSVII2C_IC_TXFLR__TXFLR__SHIFT 0x0 357#define CKSVII2C_IC_TXFLR__TXFLR_MASK 0x0000003FL 358//CKSVII2C_IC_RXFLR 359#define CKSVII2C_IC_RXFLR__RXFLR__SHIFT 0x0 360#define CKSVII2C_IC_RXFLR__RXFLR_MASK 0x0000003FL 361//CKSVII2C_IC_SDA_HOLD 362#define CKSVII2C_IC_SDA_HOLD__IC_SDA_TX_HOLD__SHIFT 0x0 363#define CKSVII2C_IC_SDA_HOLD__IC_SDA_RX_HOLD__SHIFT 0x10 364#define CKSVII2C_IC_SDA_HOLD__IC_SDA_TX_HOLD_MASK 0x0000FFFFL 365#define CKSVII2C_IC_SDA_HOLD__IC_SDA_RX_HOLD_MASK 0x00FF0000L 366//CKSVII2C_IC_TX_ABRT_SOURCE 367//CKSVII2C_IC_SLV_DATA_NACK_ONLY 368//CKSVII2C_IC_DMA_CR 369//CKSVII2C_IC_DMA_TDLR 370//CKSVII2C_IC_DMA_RDLR 371//CKSVII2C_IC_SDA_SETUP 372#define CKSVII2C_IC_SDA_SETUP__SDA_SETUP__SHIFT 0x0 373#define CKSVII2C_IC_SDA_SETUP__SDA_SETUP_MASK 0x000000FFL 374//CKSVII2C_IC_ACK_GENERAL_CALL 375#define CKSVII2C_IC_ACK_GENERAL_CALL__ACK_GENERAL_CALL__SHIFT 0x0 376#define CKSVII2C_IC_ACK_GENERAL_CALL__ACK_GENERAL_CALL_MASK 0x00000001L 377//CKSVII2C_IC_ENABLE_STATUS 378#define CKSVII2C_IC_ENABLE_STATUS__IC_EN__SHIFT 0x0 379#define CKSVII2C_IC_ENABLE_STATUS__SLV_DISABLED_WHILE_BUSY__SHIFT 0x1 380#define CKSVII2C_IC_ENABLE_STATUS__SLV_RX_DATA_LOST__SHIFT 0x2 381#define CKSVII2C_IC_ENABLE_STATUS__IC_EN_MASK 0x00000001L 382#define CKSVII2C_IC_ENABLE_STATUS__SLV_DISABLED_WHILE_BUSY_MASK 0x00000002L 383#define CKSVII2C_IC_ENABLE_STATUS__SLV_RX_DATA_LOST_MASK 0x00000004L 384//CKSVII2C_IC_FS_SPKLEN 385#define CKSVII2C_IC_FS_SPKLEN__FS_SPKLEN__SHIFT 0x0 386#define CKSVII2C_IC_FS_SPKLEN__FS_SPKLEN_MASK 0x000000FFL 387//CKSVII2C_IC_HS_SPKLEN 388#define CKSVII2C_IC_HS_SPKLEN__HS_SPKLEN__SHIFT 0x0 389#define CKSVII2C_IC_HS_SPKLEN__HS_SPKLEN_MASK 0x000000FFL 390//CKSVII2C_IC_CLR_RESTART_DET 391//CKSVII2C_IC_COMP_PARAM_1 392#define CKSVII2C_IC_COMP_PARAM_1__APB_DATA_WIDTH__SHIFT 0x0 393#define CKSVII2C_IC_COMP_PARAM_1__MAX_SPEED_MODE__SHIFT 0x2 394#define CKSVII2C_IC_COMP_PARAM_1__HC_COUNT_VALUES__SHIFT 0x4 395#define CKSVII2C_IC_COMP_PARAM_1__INTR_IO__SHIFT 0x5 396#define CKSVII2C_IC_COMP_PARAM_1__HAS_DMA__SHIFT 0x6 397#define CKSVII2C_IC_COMP_PARAM_1__ADD_ENCODED_PARAMS__SHIFT 0x7 398#define CKSVII2C_IC_COMP_PARAM_1__RX_BUFFER_DEPTH__SHIFT 0x8 399#define CKSVII2C_IC_COMP_PARAM_1__TX_BUFFER_DEPTH__SHIFT 0x10 400#define CKSVII2C_IC_COMP_PARAM_1__APB_DATA_WIDTH_MASK 0x00000003L 401#define CKSVII2C_IC_COMP_PARAM_1__MAX_SPEED_MODE_MASK 0x0000000CL 402#define CKSVII2C_IC_COMP_PARAM_1__HC_COUNT_VALUES_MASK 0x00000010L 403#define CKSVII2C_IC_COMP_PARAM_1__INTR_IO_MASK 0x00000020L 404#define CKSVII2C_IC_COMP_PARAM_1__HAS_DMA_MASK 0x00000040L 405#define CKSVII2C_IC_COMP_PARAM_1__ADD_ENCODED_PARAMS_MASK 0x00000080L 406#define CKSVII2C_IC_COMP_PARAM_1__RX_BUFFER_DEPTH_MASK 0x0000FF00L 407#define CKSVII2C_IC_COMP_PARAM_1__TX_BUFFER_DEPTH_MASK 0x00FF0000L 408//CKSVII2C_IC_COMP_VERSION 409#define CKSVII2C_IC_COMP_VERSION__COMP_VERSION__SHIFT 0x0 410#define CKSVII2C_IC_COMP_VERSION__COMP_VERSION_MASK 0xFFFFFFFFL 411//CKSVII2C_IC_COMP_TYPE 412#define CKSVII2C_IC_COMP_TYPE__COMP_TYPE__SHIFT 0x0 413#define CKSVII2C_IC_COMP_TYPE__COMP_TYPE_MASK 0xFFFFFFFFL 414//CKSVII2C1_IC_CON 415#define CKSVII2C1_IC_CON__IC1_MASTER_MODE__SHIFT 0x0 416#define CKSVII2C1_IC_CON__IC1_MAX_SPEED_MODE__SHIFT 0x1 417#define CKSVII2C1_IC_CON__IC1_10BITADDR_SLAVE__SHIFT 0x3 418#define CKSVII2C1_IC_CON__IC1_10BITADDR_MASTER__SHIFT 0x4 419#define CKSVII2C1_IC_CON__IC1_RESTART_EN__SHIFT 0x5 420#define CKSVII2C1_IC_CON__IC1_SLAVE_DISABLE__SHIFT 0x6 421#define CKSVII2C1_IC_CON__STOP1_DET_IFADDRESSED__SHIFT 0x7 422#define CKSVII2C1_IC_CON__TX1_EMPTY_CTRL__SHIFT 0x8 423#define CKSVII2C1_IC_CON__RX1_FIFO_FULL_HLD_CTRL__SHIFT 0x9 424#define CKSVII2C1_IC_CON__BUS_CLEAR_FEATURE_CTRL1__SHIFT 0xb 425#define CKSVII2C1_IC_CON__IC1_MASTER_MODE_MASK 0x00000001L 426#define CKSVII2C1_IC_CON__IC1_MAX_SPEED_MODE_MASK 0x00000006L 427#define CKSVII2C1_IC_CON__IC1_10BITADDR_SLAVE_MASK 0x00000008L 428#define CKSVII2C1_IC_CON__IC1_10BITADDR_MASTER_MASK 0x00000010L 429#define CKSVII2C1_IC_CON__IC1_RESTART_EN_MASK 0x00000020L 430#define CKSVII2C1_IC_CON__IC1_SLAVE_DISABLE_MASK 0x00000040L 431#define CKSVII2C1_IC_CON__STOP1_DET_IFADDRESSED_MASK 0x00000080L 432#define CKSVII2C1_IC_CON__TX1_EMPTY_CTRL_MASK 0x00000100L 433#define CKSVII2C1_IC_CON__RX1_FIFO_FULL_HLD_CTRL_MASK 0x00000200L 434#define CKSVII2C1_IC_CON__BUS_CLEAR_FEATURE_CTRL1_MASK 0x00000800L 435//CKSVII2C1_IC_TAR 436#define CKSVII2C1_IC_TAR__IC1_TAR__SHIFT 0x0 437#define CKSVII2C1_IC_TAR__GC1_OR_START__SHIFT 0xa 438#define CKSVII2C1_IC_TAR__SPECIAL1__SHIFT 0xb 439#define CKSVII2C1_IC_TAR__IC1_10BITADDR_MASTER__SHIFT 0xc 440#define CKSVII2C1_IC_TAR__IC1_TAR_MASK 0x000003FFL 441#define CKSVII2C1_IC_TAR__GC1_OR_START_MASK 0x00000400L 442#define CKSVII2C1_IC_TAR__SPECIAL1_MASK 0x00000800L 443#define CKSVII2C1_IC_TAR__IC1_10BITADDR_MASTER_MASK 0x00001000L 444//CKSVII2C1_IC_SAR 445#define CKSVII2C1_IC_SAR__IC1_SAR__SHIFT 0x0 446#define CKSVII2C1_IC_SAR__IC1_SAR_MASK 0x000003FFL 447//CKSVII2C1_IC_HS_MADDR 448#define CKSVII2C1_IC_HS_MADDR__IC1_HS_MADDR__SHIFT 0x0 449#define CKSVII2C1_IC_HS_MADDR__IC1_HS_MADDR_MASK 0x00000007L 450//CKSVII2C1_IC_DATA_CMD 451#define CKSVII2C1_IC_DATA_CMD__DAT1__SHIFT 0x0 452#define CKSVII2C1_IC_DATA_CMD__CMD1__SHIFT 0x8 453#define CKSVII2C1_IC_DATA_CMD__STOP1__SHIFT 0x9 454#define CKSVII2C1_IC_DATA_CMD__RESTART1__SHIFT 0xa 455#define CKSVII2C1_IC_DATA_CMD__FIRST1_DATA_BYTE__SHIFT 0xb 456#define CKSVII2C1_IC_DATA_CMD__DAT1_MASK 0x000000FFL 457#define CKSVII2C1_IC_DATA_CMD__CMD1_MASK 0x00000100L 458#define CKSVII2C1_IC_DATA_CMD__STOP1_MASK 0x00000200L 459#define CKSVII2C1_IC_DATA_CMD__RESTART1_MASK 0x00000400L 460#define CKSVII2C1_IC_DATA_CMD__FIRST1_DATA_BYTE_MASK 0x00000800L 461//CKSVII2C1_IC_SS_SCL_HCNT 462#define CKSVII2C1_IC_SS_SCL_HCNT__IC1_SS_SCL_HCNT__SHIFT 0x0 463#define CKSVII2C1_IC_SS_SCL_HCNT__IC1_SS_SCL_HCNT_MASK 0x0000FFFFL 464//CKSVII2C1_IC_SS_SCL_LCNT 465#define CKSVII2C1_IC_SS_SCL_LCNT__IC1_SS_SCL_LCNT__SHIFT 0x0 466#define CKSVII2C1_IC_SS_SCL_LCNT__IC1_SS_SCL_LCNT_MASK 0x0000FFFFL 467//CKSVII2C1_IC_FS_SCL_HCNT 468#define CKSVII2C1_IC_FS_SCL_HCNT__IC1_FS_SCL_HCNT__SHIFT 0x0 469#define CKSVII2C1_IC_FS_SCL_HCNT__IC1_FS_SCL_HCNT_MASK 0x0000FFFFL 470//CKSVII2C1_IC_FS_SCL_LCNT 471#define CKSVII2C1_IC_FS_SCL_LCNT__IC1_FS_SCL_LCNT__SHIFT 0x0 472#define CKSVII2C1_IC_FS_SCL_LCNT__IC1_FS_SCL_LCNT_MASK 0x0000FFFFL 473//CKSVII2C1_IC_HS_SCL_HCNT 474#define CKSVII2C1_IC_HS_SCL_HCNT__IC1_HS_SCL_HCNT__SHIFT 0x0 475#define CKSVII2C1_IC_HS_SCL_HCNT__IC1_HS_SCL_HCNT_MASK 0x0000FFFFL 476//CKSVII2C1_IC_HS_SCL_LCNT 477#define CKSVII2C1_IC_HS_SCL_LCNT__IC1_HS_SCL_LCNT__SHIFT 0x0 478#define CKSVII2C1_IC_HS_SCL_LCNT__IC1_HS_SCL_LCNT_MASK 0x0000FFFFL 479//CKSVII2C1_IC_INTR_STAT 480#define CKSVII2C1_IC_INTR_STAT__R1_RX_UNDER__SHIFT 0x0 481#define CKSVII2C1_IC_INTR_STAT__R1_RX_OVER__SHIFT 0x1 482#define CKSVII2C1_IC_INTR_STAT__R1_RX_FULL__SHIFT 0x2 483#define CKSVII2C1_IC_INTR_STAT__R1_TX_OVER__SHIFT 0x3 484#define CKSVII2C1_IC_INTR_STAT__R1_TX_EMPTY__SHIFT 0x4 485#define CKSVII2C1_IC_INTR_STAT__R1_RD_REQ__SHIFT 0x5 486#define CKSVII2C1_IC_INTR_STAT__R1_TX_ABRT__SHIFT 0x6 487#define CKSVII2C1_IC_INTR_STAT__R1_RX_DONE__SHIFT 0x7 488#define CKSVII2C1_IC_INTR_STAT__R1_ACTIVITY__SHIFT 0x8 489#define CKSVII2C1_IC_INTR_STAT__R1_STOP_DET__SHIFT 0x9 490#define CKSVII2C1_IC_INTR_STAT__R1_START_DET__SHIFT 0xa 491#define CKSVII2C1_IC_INTR_STAT__R1_GEN_CALL__SHIFT 0xb 492#define CKSVII2C1_IC_INTR_STAT__R1_RESTART_DET__SHIFT 0xc 493#define CKSVII2C1_IC_INTR_STAT__R1_MST_ON_HOLD__SHIFT 0xd 494#define CKSVII2C1_IC_INTR_STAT__R1_SCL_STUCK_AT_LOW__SHIFT 0xe 495#define CKSVII2C1_IC_INTR_STAT__R1_RX_UNDER_MASK 0x00000001L 496#define CKSVII2C1_IC_INTR_STAT__R1_RX_OVER_MASK 0x00000002L 497#define CKSVII2C1_IC_INTR_STAT__R1_RX_FULL_MASK 0x00000004L 498#define CKSVII2C1_IC_INTR_STAT__R1_TX_OVER_MASK 0x00000008L 499#define CKSVII2C1_IC_INTR_STAT__R1_TX_EMPTY_MASK 0x00000010L 500#define CKSVII2C1_IC_INTR_STAT__R1_RD_REQ_MASK 0x00000020L 501#define CKSVII2C1_IC_INTR_STAT__R1_TX_ABRT_MASK 0x00000040L 502#define CKSVII2C1_IC_INTR_STAT__R1_RX_DONE_MASK 0x00000080L 503#define CKSVII2C1_IC_INTR_STAT__R1_ACTIVITY_MASK 0x00000100L 504#define CKSVII2C1_IC_INTR_STAT__R1_STOP_DET_MASK 0x00000200L 505#define CKSVII2C1_IC_INTR_STAT__R1_START_DET_MASK 0x00000400L 506#define CKSVII2C1_IC_INTR_STAT__R1_GEN_CALL_MASK 0x00000800L 507#define CKSVII2C1_IC_INTR_STAT__R1_RESTART_DET_MASK 0x00001000L 508#define CKSVII2C1_IC_INTR_STAT__R1_MST_ON_HOLD_MASK 0x00002000L 509#define CKSVII2C1_IC_INTR_STAT__R1_SCL_STUCK_AT_LOW_MASK 0x00004000L 510//CKSVII2C1_IC_INTR_MASK 511#define CKSVII2C1_IC_INTR_MASK__M1_RX_UNDER__SHIFT 0x0 512#define CKSVII2C1_IC_INTR_MASK__M1_RX_OVER__SHIFT 0x1 513#define CKSVII2C1_IC_INTR_MASK__M1_RX_FULL__SHIFT 0x2 514#define CKSVII2C1_IC_INTR_MASK__M1_TX_OVER__SHIFT 0x3 515#define CKSVII2C1_IC_INTR_MASK__M1_TX_EMPTY__SHIFT 0x4 516#define CKSVII2C1_IC_INTR_MASK__M1_RD_REQ__SHIFT 0x5 517#define CKSVII2C1_IC_INTR_MASK__M1_TX_ABRT__SHIFT 0x6 518#define CKSVII2C1_IC_INTR_MASK__M1_RX_DONE__SHIFT 0x7 519#define CKSVII2C1_IC_INTR_MASK__M1_ACTIVITY__SHIFT 0x8 520#define CKSVII2C1_IC_INTR_MASK__M1_STOP_DET__SHIFT 0x9 521#define CKSVII2C1_IC_INTR_MASK__M1_START_DET__SHIFT 0xa 522#define CKSVII2C1_IC_INTR_MASK__M1_GEN_CALL__SHIFT 0xb 523#define CKSVII2C1_IC_INTR_MASK__M1_RESTART_DET__SHIFT 0xc 524#define CKSVII2C1_IC_INTR_MASK__M1_MST_ON_HOLD__SHIFT 0xd 525#define CKSVII2C1_IC_INTR_MASK__M1_SCL_STUCK_AT_LOW__SHIFT 0xe 526#define CKSVII2C1_IC_INTR_MASK__M1_RX_UNDER_MASK 0x00000001L 527#define CKSVII2C1_IC_INTR_MASK__M1_RX_OVER_MASK 0x00000002L 528#define CKSVII2C1_IC_INTR_MASK__M1_RX_FULL_MASK 0x00000004L 529#define CKSVII2C1_IC_INTR_MASK__M1_TX_OVER_MASK 0x00000008L 530#define CKSVII2C1_IC_INTR_MASK__M1_TX_EMPTY_MASK 0x00000010L 531#define CKSVII2C1_IC_INTR_MASK__M1_RD_REQ_MASK 0x00000020L 532#define CKSVII2C1_IC_INTR_MASK__M1_TX_ABRT_MASK 0x00000040L 533#define CKSVII2C1_IC_INTR_MASK__M1_RX_DONE_MASK 0x00000080L 534#define CKSVII2C1_IC_INTR_MASK__M1_ACTIVITY_MASK 0x00000100L 535#define CKSVII2C1_IC_INTR_MASK__M1_STOP_DET_MASK 0x00000200L 536#define CKSVII2C1_IC_INTR_MASK__M1_START_DET_MASK 0x00000400L 537#define CKSVII2C1_IC_INTR_MASK__M1_GEN_CALL_MASK 0x00000800L 538#define CKSVII2C1_IC_INTR_MASK__M1_RESTART_DET_MASK 0x00001000L 539#define CKSVII2C1_IC_INTR_MASK__M1_MST_ON_HOLD_MASK 0x00002000L 540#define CKSVII2C1_IC_INTR_MASK__M1_SCL_STUCK_AT_LOW_MASK 0x00004000L 541//CKSVII2C1_IC_RAW_INTR_STAT 542//CKSVII2C1_IC_RX_TL 543#define CKSVII2C1_IC_RX_TL__RX1_TL__SHIFT 0x0 544#define CKSVII2C1_IC_RX_TL__RX1_TL_MASK 0x000000FFL 545//CKSVII2C1_IC_TX_TL 546#define CKSVII2C1_IC_TX_TL__TX1_TL__SHIFT 0x0 547#define CKSVII2C1_IC_TX_TL__TX1_TL_MASK 0x000000FFL 548//CKSVII2C1_IC_CLR_INTR 549//CKSVII2C1_IC_CLR_RX_UNDER 550//CKSVII2C1_IC_CLR_RX_OVER 551//CKSVII2C1_IC_CLR_TX_OVER 552//CKSVII2C1_IC_CLR_RD_REQ 553//CKSVII2C1_IC_CLR_TX_ABRT 554//CKSVII2C1_IC_CLR_RX_DONE 555//CKSVII2C1_IC_CLR_ACTIVITY 556//CKSVII2C1_IC_CLR_STOP_DET 557//CKSVII2C1_IC_CLR_START_DET 558//CKSVII2C1_IC_CLR_GEN_CALL 559//CKSVII2C1_IC_ENABLE 560#define CKSVII2C1_IC_ENABLE__ENABLE1__SHIFT 0x0 561#define CKSVII2C1_IC_ENABLE__ABORT1__SHIFT 0x1 562#define CKSVII2C1_IC_ENABLE__TX1_CMD_BLOCK__SHIFT 0x2 563#define CKSVII2C1_IC_ENABLE__SDA1_STUCK_RECOVERY_ENABLE__SHIFT 0x3 564#define CKSVII2C1_IC_ENABLE__ENABLE1_MASK 0x00000001L 565#define CKSVII2C1_IC_ENABLE__ABORT1_MASK 0x00000002L 566#define CKSVII2C1_IC_ENABLE__TX1_CMD_BLOCK_MASK 0x00000004L 567#define CKSVII2C1_IC_ENABLE__SDA1_STUCK_RECOVERY_ENABLE_MASK 0x00000008L 568//CKSVII2C1_IC_STATUS 569#define CKSVII2C1_IC_STATUS__ACTIVITY1__SHIFT 0x0 570#define CKSVII2C1_IC_STATUS__TFNF1__SHIFT 0x1 571#define CKSVII2C1_IC_STATUS__TFE1__SHIFT 0x2 572#define CKSVII2C1_IC_STATUS__RFNE1__SHIFT 0x3 573#define CKSVII2C1_IC_STATUS__RFF1__SHIFT 0x4 574#define CKSVII2C1_IC_STATUS__MST1_ACTIVITY__SHIFT 0x5 575#define CKSVII2C1_IC_STATUS__SLV1_ACTIVITY__SHIFT 0x6 576#define CKSVII2C1_IC_STATUS__MST1_HOLD_TX_FIFO_EMPTY__SHIFT 0x7 577#define CKSVII2C1_IC_STATUS__MST1_HOLD_RX_FIFO_FULL__SHIFT 0x8 578#define CKSVII2C1_IC_STATUS__SLV1_HOLD_TX_FIFO_EMPTY__SHIFT 0x9 579#define CKSVII2C1_IC_STATUS__SLV1_HOLD_RX_FIFO_FULL__SHIFT 0xa 580#define CKSVII2C1_IC_STATUS__SDA1_STUCK_NOT_RECOVERED__SHIFT 0xb 581#define CKSVII2C1_IC_STATUS__ACTIVITY1_MASK 0x00000001L 582#define CKSVII2C1_IC_STATUS__TFNF1_MASK 0x00000002L 583#define CKSVII2C1_IC_STATUS__TFE1_MASK 0x00000004L 584#define CKSVII2C1_IC_STATUS__RFNE1_MASK 0x00000008L 585#define CKSVII2C1_IC_STATUS__RFF1_MASK 0x00000010L 586#define CKSVII2C1_IC_STATUS__MST1_ACTIVITY_MASK 0x00000020L 587#define CKSVII2C1_IC_STATUS__SLV1_ACTIVITY_MASK 0x00000040L 588#define CKSVII2C1_IC_STATUS__MST1_HOLD_TX_FIFO_EMPTY_MASK 0x00000080L 589#define CKSVII2C1_IC_STATUS__MST1_HOLD_RX_FIFO_FULL_MASK 0x00000100L 590#define CKSVII2C1_IC_STATUS__SLV1_HOLD_TX_FIFO_EMPTY_MASK 0x00000200L 591#define CKSVII2C1_IC_STATUS__SLV1_HOLD_RX_FIFO_FULL_MASK 0x00000400L 592#define CKSVII2C1_IC_STATUS__SDA1_STUCK_NOT_RECOVERED_MASK 0x00000800L 593//CKSVII2C1_IC_TXFLR 594#define CKSVII2C1_IC_TXFLR__TXFLR1__SHIFT 0x0 595#define CKSVII2C1_IC_TXFLR__TXFLR1_MASK 0x0000003FL 596//CKSVII2C1_IC_RXFLR 597#define CKSVII2C1_IC_RXFLR__RXFLR1__SHIFT 0x0 598#define CKSVII2C1_IC_RXFLR__RXFLR1_MASK 0x0000003FL 599//CKSVII2C1_IC_SDA_HOLD 600#define CKSVII2C1_IC_SDA_HOLD__IC1_SDA_TX_HOLD__SHIFT 0x0 601#define CKSVII2C1_IC_SDA_HOLD__IC1_SDA_RX_HOLD__SHIFT 0x10 602#define CKSVII2C1_IC_SDA_HOLD__IC1_SDA_TX_HOLD_MASK 0x0000FFFFL 603#define CKSVII2C1_IC_SDA_HOLD__IC1_SDA_RX_HOLD_MASK 0x00FF0000L 604//CKSVII2C1_IC_TX_ABRT_SOURCE 605//CKSVII2C1_IC_SLV_DATA_NACK_ONLY 606//CKSVII2C1_IC_DMA_CR 607//CKSVII2C1_IC_DMA_TDLR 608//CKSVII2C1_IC_DMA_RDLR 609//CKSVII2C1_IC_SDA_SETUP 610#define CKSVII2C1_IC_SDA_SETUP__SDA1_SETUP__SHIFT 0x0 611#define CKSVII2C1_IC_SDA_SETUP__SDA1_SETUP_MASK 0x000000FFL 612//CKSVII2C1_IC_ACK_GENERAL_CALL 613#define CKSVII2C1_IC_ACK_GENERAL_CALL__ACK1_GENERAL_CALL__SHIFT 0x0 614#define CKSVII2C1_IC_ACK_GENERAL_CALL__ACK1_GENERAL_CALL_MASK 0x00000001L 615//CKSVII2C1_IC_ENABLE_STATUS 616#define CKSVII2C1_IC_ENABLE_STATUS__IC1_EN__SHIFT 0x0 617#define CKSVII2C1_IC_ENABLE_STATUS__SLV1_DISABLED_WHILE_BUSY__SHIFT 0x1 618#define CKSVII2C1_IC_ENABLE_STATUS__SLV1_RX_DATA_LOST__SHIFT 0x2 619#define CKSVII2C1_IC_ENABLE_STATUS__IC1_EN_MASK 0x00000001L 620#define CKSVII2C1_IC_ENABLE_STATUS__SLV1_DISABLED_WHILE_BUSY_MASK 0x00000002L 621#define CKSVII2C1_IC_ENABLE_STATUS__SLV1_RX_DATA_LOST_MASK 0x00000004L 622//CKSVII2C1_IC_FS_SPKLEN 623#define CKSVII2C1_IC_FS_SPKLEN__FS1_SPKLEN__SHIFT 0x0 624#define CKSVII2C1_IC_FS_SPKLEN__FS1_SPKLEN_MASK 0x000000FFL 625//CKSVII2C1_IC_HS_SPKLEN 626#define CKSVII2C1_IC_HS_SPKLEN__HS1_SPKLEN__SHIFT 0x0 627#define CKSVII2C1_IC_HS_SPKLEN__HS1_SPKLEN_MASK 0x000000FFL 628//CKSVII2C1_IC_CLR_RESTART_DET 629//CKSVII2C1_IC_COMP_PARAM_1 630#define CKSVII2C1_IC_COMP_PARAM_1__APB1_DATA_WIDTH__SHIFT 0x0 631#define CKSVII2C1_IC_COMP_PARAM_1__MAX1_SPEED_MODE__SHIFT 0x2 632#define CKSVII2C1_IC_COMP_PARAM_1__HC1_COUNT_VALUES__SHIFT 0x4 633#define CKSVII2C1_IC_COMP_PARAM_1__INTR1_IO__SHIFT 0x5 634#define CKSVII2C1_IC_COMP_PARAM_1__HAS1_DMA__SHIFT 0x6 635#define CKSVII2C1_IC_COMP_PARAM_1__ADD1_ENCODED_PARAMS__SHIFT 0x7 636#define CKSVII2C1_IC_COMP_PARAM_1__RX1_BUFFER_DEPTH__SHIFT 0x8 637#define CKSVII2C1_IC_COMP_PARAM_1__TX1_BUFFER_DEPTH__SHIFT 0x10 638#define CKSVII2C1_IC_COMP_PARAM_1__APB1_DATA_WIDTH_MASK 0x00000003L 639#define CKSVII2C1_IC_COMP_PARAM_1__MAX1_SPEED_MODE_MASK 0x0000000CL 640#define CKSVII2C1_IC_COMP_PARAM_1__HC1_COUNT_VALUES_MASK 0x00000010L 641#define CKSVII2C1_IC_COMP_PARAM_1__INTR1_IO_MASK 0x00000020L 642#define CKSVII2C1_IC_COMP_PARAM_1__HAS1_DMA_MASK 0x00000040L 643#define CKSVII2C1_IC_COMP_PARAM_1__ADD1_ENCODED_PARAMS_MASK 0x00000080L 644#define CKSVII2C1_IC_COMP_PARAM_1__RX1_BUFFER_DEPTH_MASK 0x0000FF00L 645#define CKSVII2C1_IC_COMP_PARAM_1__TX1_BUFFER_DEPTH_MASK 0x00FF0000L 646//CKSVII2C1_IC_COMP_VERSION 647#define CKSVII2C1_IC_COMP_VERSION__COMP1_VERSION__SHIFT 0x0 648#define CKSVII2C1_IC_COMP_VERSION__COMP1_VERSION_MASK 0xFFFFFFFFL 649//CKSVII2C1_IC_COMP_TYPE 650#define CKSVII2C1_IC_COMP_TYPE__COMP1_TYPE__SHIFT 0x0 651#define CKSVII2C1_IC_COMP_TYPE__COMP1_TYPE_MASK 0xFFFFFFFFL 652//SMUIO_PWRMGT 653#define SMUIO_PWRMGT__i2c_clk_gate_en__SHIFT 0x0 654#define SMUIO_PWRMGT__i2c1_clk_gate_en__SHIFT 0x4 655#define SMUIO_PWRMGT__i2c_clk_gate_en_MASK 0x00000001L 656#define SMUIO_PWRMGT__i2c1_clk_gate_en_MASK 0x00000010L 657 658 659// addressBlock: smuio_smuio_rom_SmuSmuioDec 660//ROM_CNTL 661#define ROM_CNTL__CLOCK_GATING_EN__SHIFT 0x0 662#define ROM_CNTL__READ_MODE__SHIFT 0x1 663#define ROM_CNTL__READ_MODE_OVERRIDE__SHIFT 0x3 664#define ROM_CNTL__SPI_TIMING_RELAX_SCK__SHIFT 0x4 665#define ROM_CNTL__SPI_TIMING_RELAX_SCK_OVERRIDE__SHIFT 0x5 666#define ROM_CNTL__FOUR_BYTE_ADDRESS_MODE__SHIFT 0x6 667#define ROM_CNTL__DUMMY_CYCLE_NUM__SHIFT 0x8 668#define ROM_CNTL__SPI_TIMING_RELAX__SHIFT 0x14 669#define ROM_CNTL__SPI_TIMING_RELAX_OVERRIDE__SHIFT 0x15 670#define ROM_CNTL__SPI_FAST_MODE__SHIFT 0x16 671#define ROM_CNTL__SPI_FAST_MODE_OVERRIDE__SHIFT 0x17 672#define ROM_CNTL__SCK_PRESCALE_REFCLK__SHIFT 0x18 673#define ROM_CNTL__SCK_PRESCALE_REFCLK_OVERRIDE__SHIFT 0x1c 674#define ROM_CNTL__ROM_INDEX_ADDRESS_AUTO_INCREASE__SHIFT 0x1d 675#define ROM_CNTL__PAD_SAMPLE_MODE__SHIFT 0x1e 676#define ROM_CNTL__PAD_SAMPLE_MODE_OVERRIDE__SHIFT 0x1f 677#define ROM_CNTL__CLOCK_GATING_EN_MASK 0x00000001L 678#define ROM_CNTL__READ_MODE_MASK 0x00000006L 679#define ROM_CNTL__READ_MODE_OVERRIDE_MASK 0x00000008L 680#define ROM_CNTL__SPI_TIMING_RELAX_SCK_MASK 0x00000010L 681#define ROM_CNTL__SPI_TIMING_RELAX_SCK_OVERRIDE_MASK 0x00000020L 682#define ROM_CNTL__FOUR_BYTE_ADDRESS_MODE_MASK 0x00000040L 683#define ROM_CNTL__DUMMY_CYCLE_NUM_MASK 0x00000F00L 684#define ROM_CNTL__SPI_TIMING_RELAX_MASK 0x00100000L 685#define ROM_CNTL__SPI_TIMING_RELAX_OVERRIDE_MASK 0x00200000L 686#define ROM_CNTL__SPI_FAST_MODE_MASK 0x00400000L 687#define ROM_CNTL__SPI_FAST_MODE_OVERRIDE_MASK 0x00800000L 688#define ROM_CNTL__SCK_PRESCALE_REFCLK_MASK 0x0F000000L 689#define ROM_CNTL__SCK_PRESCALE_REFCLK_OVERRIDE_MASK 0x10000000L 690#define ROM_CNTL__ROM_INDEX_ADDRESS_AUTO_INCREASE_MASK 0x20000000L 691#define ROM_CNTL__PAD_SAMPLE_MODE_MASK 0x40000000L 692#define ROM_CNTL__PAD_SAMPLE_MODE_OVERRIDE_MASK 0x80000000L 693//PAGE_MIRROR_CNTL 694#define PAGE_MIRROR_CNTL__PAGE_MIRROR_BASE_ADDR__SHIFT 0x0 695#define PAGE_MIRROR_CNTL__PAGE_MIRROR_ENABLE__SHIFT 0x19 696#define PAGE_MIRROR_CNTL__PAGE_MIRROR_USAGE__SHIFT 0x1a 697#define PAGE_MIRROR_CNTL__PAGE_MIRROR_INVALIDATE__SHIFT 0x1c 698#define PAGE_MIRROR_CNTL__PAGE_MIRROR_BASE_ADDR_MASK 0x01FFFFFFL 699#define PAGE_MIRROR_CNTL__PAGE_MIRROR_ENABLE_MASK 0x02000000L 700#define PAGE_MIRROR_CNTL__PAGE_MIRROR_USAGE_MASK 0x0C000000L 701#define PAGE_MIRROR_CNTL__PAGE_MIRROR_INVALIDATE_MASK 0x10000000L 702//ROM_STATUS 703#define ROM_STATUS__ROM_BUSY__SHIFT 0x0 704#define ROM_STATUS__ROM_BUSY_MASK 0x00000001L 705//CGTT_ROM_CLK_CTRL0 706#define CGTT_ROM_CLK_CTRL0__ON_DELAY__SHIFT 0x0 707#define CGTT_ROM_CLK_CTRL0__OFF_HYSTERESIS__SHIFT 0x4 708#define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1__SHIFT 0x1e 709#define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0__SHIFT 0x1f 710#define CGTT_ROM_CLK_CTRL0__ON_DELAY_MASK 0x0000000FL 711#define CGTT_ROM_CLK_CTRL0__OFF_HYSTERESIS_MASK 0x00000FF0L 712#define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK 0x40000000L 713#define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK 0x80000000L 714//ROM_INDEX 715#define ROM_INDEX__ROM_INDEX__SHIFT 0x0 716#define ROM_INDEX__ROM_INDEX_MASK 0x01FFFFFFL 717//ROM_DATA 718#define ROM_DATA__ROM_DATA__SHIFT 0x0 719#define ROM_DATA__ROM_DATA_MASK 0xFFFFFFFFL 720//ROM_START 721#define ROM_START__ROM_START__SHIFT 0x0 722#define ROM_START__ROM_START_MASK 0x01FFFFFFL 723//ROM_SW_CNTL 724#define ROM_SW_CNTL__DATA_SIZE__SHIFT 0x0 725#define ROM_SW_CNTL__COMMAND_SIZE__SHIFT 0x10 726#define ROM_SW_CNTL__ROM_SW_RETURN_DATA_ENABLE__SHIFT 0x13 727#define ROM_SW_CNTL__DATA_SIZE_MASK 0x0000FFFFL 728#define ROM_SW_CNTL__COMMAND_SIZE_MASK 0x00070000L 729#define ROM_SW_CNTL__ROM_SW_RETURN_DATA_ENABLE_MASK 0x00080000L 730//ROM_SW_STATUS 731#define ROM_SW_STATUS__ROM_SW_DONE__SHIFT 0x0 732#define ROM_SW_STATUS__ROM_SW_DONE_MASK 0x00000001L 733//ROM_SW_COMMAND 734#define ROM_SW_COMMAND__ROM_SW_INSTRUCTION__SHIFT 0x0 735#define ROM_SW_COMMAND__ROM_SW_ADDRESS__SHIFT 0x8 736#define ROM_SW_COMMAND__ROM_SW_INSTRUCTION_MASK 0x000000FFL 737#define ROM_SW_COMMAND__ROM_SW_ADDRESS_MASK 0xFFFFFF00L 738//ROM_SW_DATA_1 739#define ROM_SW_DATA_1__ROM_SW_DATA__SHIFT 0x0 740#define ROM_SW_DATA_1__ROM_SW_DATA_MASK 0xFFFFFFFFL 741//ROM_SW_DATA_2 742#define ROM_SW_DATA_2__ROM_SW_DATA__SHIFT 0x0 743#define ROM_SW_DATA_2__ROM_SW_DATA_MASK 0xFFFFFFFFL 744//ROM_SW_DATA_3 745#define ROM_SW_DATA_3__ROM_SW_DATA__SHIFT 0x0 746#define ROM_SW_DATA_3__ROM_SW_DATA_MASK 0xFFFFFFFFL 747//ROM_SW_DATA_4 748#define ROM_SW_DATA_4__ROM_SW_DATA__SHIFT 0x0 749#define ROM_SW_DATA_4__ROM_SW_DATA_MASK 0xFFFFFFFFL 750//ROM_SW_DATA_5 751#define ROM_SW_DATA_5__ROM_SW_DATA__SHIFT 0x0 752#define ROM_SW_DATA_5__ROM_SW_DATA_MASK 0xFFFFFFFFL 753//ROM_SW_DATA_6 754#define ROM_SW_DATA_6__ROM_SW_DATA__SHIFT 0x0 755#define ROM_SW_DATA_6__ROM_SW_DATA_MASK 0xFFFFFFFFL 756//ROM_SW_DATA_7 757#define ROM_SW_DATA_7__ROM_SW_DATA__SHIFT 0x0 758#define ROM_SW_DATA_7__ROM_SW_DATA_MASK 0xFFFFFFFFL 759//ROM_SW_DATA_8 760#define ROM_SW_DATA_8__ROM_SW_DATA__SHIFT 0x0 761#define ROM_SW_DATA_8__ROM_SW_DATA_MASK 0xFFFFFFFFL 762//ROM_SW_DATA_9 763#define ROM_SW_DATA_9__ROM_SW_DATA__SHIFT 0x0 764#define ROM_SW_DATA_9__ROM_SW_DATA_MASK 0xFFFFFFFFL 765//ROM_SW_DATA_10 766#define ROM_SW_DATA_10__ROM_SW_DATA__SHIFT 0x0 767#define ROM_SW_DATA_10__ROM_SW_DATA_MASK 0xFFFFFFFFL 768//ROM_SW_DATA_11 769#define ROM_SW_DATA_11__ROM_SW_DATA__SHIFT 0x0 770#define ROM_SW_DATA_11__ROM_SW_DATA_MASK 0xFFFFFFFFL 771//ROM_SW_DATA_12 772#define ROM_SW_DATA_12__ROM_SW_DATA__SHIFT 0x0 773#define ROM_SW_DATA_12__ROM_SW_DATA_MASK 0xFFFFFFFFL 774//ROM_SW_DATA_13 775#define ROM_SW_DATA_13__ROM_SW_DATA__SHIFT 0x0 776#define ROM_SW_DATA_13__ROM_SW_DATA_MASK 0xFFFFFFFFL 777//ROM_SW_DATA_14 778#define ROM_SW_DATA_14__ROM_SW_DATA__SHIFT 0x0 779#define ROM_SW_DATA_14__ROM_SW_DATA_MASK 0xFFFFFFFFL 780//ROM_SW_DATA_15 781#define ROM_SW_DATA_15__ROM_SW_DATA__SHIFT 0x0 782#define ROM_SW_DATA_15__ROM_SW_DATA_MASK 0xFFFFFFFFL 783//ROM_SW_DATA_16 784#define ROM_SW_DATA_16__ROM_SW_DATA__SHIFT 0x0 785#define ROM_SW_DATA_16__ROM_SW_DATA_MASK 0xFFFFFFFFL 786//ROM_SW_DATA_17 787#define ROM_SW_DATA_17__ROM_SW_DATA__SHIFT 0x0 788#define ROM_SW_DATA_17__ROM_SW_DATA_MASK 0xFFFFFFFFL 789//ROM_SW_DATA_18 790#define ROM_SW_DATA_18__ROM_SW_DATA__SHIFT 0x0 791#define ROM_SW_DATA_18__ROM_SW_DATA_MASK 0xFFFFFFFFL 792//ROM_SW_DATA_19 793#define ROM_SW_DATA_19__ROM_SW_DATA__SHIFT 0x0 794#define ROM_SW_DATA_19__ROM_SW_DATA_MASK 0xFFFFFFFFL 795//ROM_SW_DATA_20 796#define ROM_SW_DATA_20__ROM_SW_DATA__SHIFT 0x0 797#define ROM_SW_DATA_20__ROM_SW_DATA_MASK 0xFFFFFFFFL 798//ROM_SW_DATA_21 799#define ROM_SW_DATA_21__ROM_SW_DATA__SHIFT 0x0 800#define ROM_SW_DATA_21__ROM_SW_DATA_MASK 0xFFFFFFFFL 801//ROM_SW_DATA_22 802#define ROM_SW_DATA_22__ROM_SW_DATA__SHIFT 0x0 803#define ROM_SW_DATA_22__ROM_SW_DATA_MASK 0xFFFFFFFFL 804//ROM_SW_DATA_23 805#define ROM_SW_DATA_23__ROM_SW_DATA__SHIFT 0x0 806#define ROM_SW_DATA_23__ROM_SW_DATA_MASK 0xFFFFFFFFL 807//ROM_SW_DATA_24 808#define ROM_SW_DATA_24__ROM_SW_DATA__SHIFT 0x0 809#define ROM_SW_DATA_24__ROM_SW_DATA_MASK 0xFFFFFFFFL 810//ROM_SW_DATA_25 811#define ROM_SW_DATA_25__ROM_SW_DATA__SHIFT 0x0 812#define ROM_SW_DATA_25__ROM_SW_DATA_MASK 0xFFFFFFFFL 813//ROM_SW_DATA_26 814#define ROM_SW_DATA_26__ROM_SW_DATA__SHIFT 0x0 815#define ROM_SW_DATA_26__ROM_SW_DATA_MASK 0xFFFFFFFFL 816//ROM_SW_DATA_27 817#define ROM_SW_DATA_27__ROM_SW_DATA__SHIFT 0x0 818#define ROM_SW_DATA_27__ROM_SW_DATA_MASK 0xFFFFFFFFL 819//ROM_SW_DATA_28 820#define ROM_SW_DATA_28__ROM_SW_DATA__SHIFT 0x0 821#define ROM_SW_DATA_28__ROM_SW_DATA_MASK 0xFFFFFFFFL 822//ROM_SW_DATA_29 823#define ROM_SW_DATA_29__ROM_SW_DATA__SHIFT 0x0 824#define ROM_SW_DATA_29__ROM_SW_DATA_MASK 0xFFFFFFFFL 825//ROM_SW_DATA_30 826#define ROM_SW_DATA_30__ROM_SW_DATA__SHIFT 0x0 827#define ROM_SW_DATA_30__ROM_SW_DATA_MASK 0xFFFFFFFFL 828//ROM_SW_DATA_31 829#define ROM_SW_DATA_31__ROM_SW_DATA__SHIFT 0x0 830#define ROM_SW_DATA_31__ROM_SW_DATA_MASK 0xFFFFFFFFL 831//ROM_SW_DATA_32 832#define ROM_SW_DATA_32__ROM_SW_DATA__SHIFT 0x0 833#define ROM_SW_DATA_32__ROM_SW_DATA_MASK 0xFFFFFFFFL 834//ROM_SW_DATA_33 835#define ROM_SW_DATA_33__ROM_SW_DATA__SHIFT 0x0 836#define ROM_SW_DATA_33__ROM_SW_DATA_MASK 0xFFFFFFFFL 837//ROM_SW_DATA_34 838#define ROM_SW_DATA_34__ROM_SW_DATA__SHIFT 0x0 839#define ROM_SW_DATA_34__ROM_SW_DATA_MASK 0xFFFFFFFFL 840//ROM_SW_DATA_35 841#define ROM_SW_DATA_35__ROM_SW_DATA__SHIFT 0x0 842#define ROM_SW_DATA_35__ROM_SW_DATA_MASK 0xFFFFFFFFL 843//ROM_SW_DATA_36 844#define ROM_SW_DATA_36__ROM_SW_DATA__SHIFT 0x0 845#define ROM_SW_DATA_36__ROM_SW_DATA_MASK 0xFFFFFFFFL 846//ROM_SW_DATA_37 847#define ROM_SW_DATA_37__ROM_SW_DATA__SHIFT 0x0 848#define ROM_SW_DATA_37__ROM_SW_DATA_MASK 0xFFFFFFFFL 849//ROM_SW_DATA_38 850#define ROM_SW_DATA_38__ROM_SW_DATA__SHIFT 0x0 851#define ROM_SW_DATA_38__ROM_SW_DATA_MASK 0xFFFFFFFFL 852//ROM_SW_DATA_39 853#define ROM_SW_DATA_39__ROM_SW_DATA__SHIFT 0x0 854#define ROM_SW_DATA_39__ROM_SW_DATA_MASK 0xFFFFFFFFL 855//ROM_SW_DATA_40 856#define ROM_SW_DATA_40__ROM_SW_DATA__SHIFT 0x0 857#define ROM_SW_DATA_40__ROM_SW_DATA_MASK 0xFFFFFFFFL 858//ROM_SW_DATA_41 859#define ROM_SW_DATA_41__ROM_SW_DATA__SHIFT 0x0 860#define ROM_SW_DATA_41__ROM_SW_DATA_MASK 0xFFFFFFFFL 861//ROM_SW_DATA_42 862#define ROM_SW_DATA_42__ROM_SW_DATA__SHIFT 0x0 863#define ROM_SW_DATA_42__ROM_SW_DATA_MASK 0xFFFFFFFFL 864//ROM_SW_DATA_43 865#define ROM_SW_DATA_43__ROM_SW_DATA__SHIFT 0x0 866#define ROM_SW_DATA_43__ROM_SW_DATA_MASK 0xFFFFFFFFL 867//ROM_SW_DATA_44 868#define ROM_SW_DATA_44__ROM_SW_DATA__SHIFT 0x0 869#define ROM_SW_DATA_44__ROM_SW_DATA_MASK 0xFFFFFFFFL 870//ROM_SW_DATA_45 871#define ROM_SW_DATA_45__ROM_SW_DATA__SHIFT 0x0 872#define ROM_SW_DATA_45__ROM_SW_DATA_MASK 0xFFFFFFFFL 873//ROM_SW_DATA_46 874#define ROM_SW_DATA_46__ROM_SW_DATA__SHIFT 0x0 875#define ROM_SW_DATA_46__ROM_SW_DATA_MASK 0xFFFFFFFFL 876//ROM_SW_DATA_47 877#define ROM_SW_DATA_47__ROM_SW_DATA__SHIFT 0x0 878#define ROM_SW_DATA_47__ROM_SW_DATA_MASK 0xFFFFFFFFL 879//ROM_SW_DATA_48 880#define ROM_SW_DATA_48__ROM_SW_DATA__SHIFT 0x0 881#define ROM_SW_DATA_48__ROM_SW_DATA_MASK 0xFFFFFFFFL 882//ROM_SW_DATA_49 883#define ROM_SW_DATA_49__ROM_SW_DATA__SHIFT 0x0 884#define ROM_SW_DATA_49__ROM_SW_DATA_MASK 0xFFFFFFFFL 885//ROM_SW_DATA_50 886#define ROM_SW_DATA_50__ROM_SW_DATA__SHIFT 0x0 887#define ROM_SW_DATA_50__ROM_SW_DATA_MASK 0xFFFFFFFFL 888//ROM_SW_DATA_51 889#define ROM_SW_DATA_51__ROM_SW_DATA__SHIFT 0x0 890#define ROM_SW_DATA_51__ROM_SW_DATA_MASK 0xFFFFFFFFL 891//ROM_SW_DATA_52 892#define ROM_SW_DATA_52__ROM_SW_DATA__SHIFT 0x0 893#define ROM_SW_DATA_52__ROM_SW_DATA_MASK 0xFFFFFFFFL 894//ROM_SW_DATA_53 895#define ROM_SW_DATA_53__ROM_SW_DATA__SHIFT 0x0 896#define ROM_SW_DATA_53__ROM_SW_DATA_MASK 0xFFFFFFFFL 897//ROM_SW_DATA_54 898#define ROM_SW_DATA_54__ROM_SW_DATA__SHIFT 0x0 899#define ROM_SW_DATA_54__ROM_SW_DATA_MASK 0xFFFFFFFFL 900//ROM_SW_DATA_55 901#define ROM_SW_DATA_55__ROM_SW_DATA__SHIFT 0x0 902#define ROM_SW_DATA_55__ROM_SW_DATA_MASK 0xFFFFFFFFL 903//ROM_SW_DATA_56 904#define ROM_SW_DATA_56__ROM_SW_DATA__SHIFT 0x0 905#define ROM_SW_DATA_56__ROM_SW_DATA_MASK 0xFFFFFFFFL 906//ROM_SW_DATA_57 907#define ROM_SW_DATA_57__ROM_SW_DATA__SHIFT 0x0 908#define ROM_SW_DATA_57__ROM_SW_DATA_MASK 0xFFFFFFFFL 909//ROM_SW_DATA_58 910#define ROM_SW_DATA_58__ROM_SW_DATA__SHIFT 0x0 911#define ROM_SW_DATA_58__ROM_SW_DATA_MASK 0xFFFFFFFFL 912//ROM_SW_DATA_59 913#define ROM_SW_DATA_59__ROM_SW_DATA__SHIFT 0x0 914#define ROM_SW_DATA_59__ROM_SW_DATA_MASK 0xFFFFFFFFL 915//ROM_SW_DATA_60 916#define ROM_SW_DATA_60__ROM_SW_DATA__SHIFT 0x0 917#define ROM_SW_DATA_60__ROM_SW_DATA_MASK 0xFFFFFFFFL 918//ROM_SW_DATA_61 919#define ROM_SW_DATA_61__ROM_SW_DATA__SHIFT 0x0 920#define ROM_SW_DATA_61__ROM_SW_DATA_MASK 0xFFFFFFFFL 921//ROM_SW_DATA_62 922#define ROM_SW_DATA_62__ROM_SW_DATA__SHIFT 0x0 923#define ROM_SW_DATA_62__ROM_SW_DATA_MASK 0xFFFFFFFFL 924//ROM_SW_DATA_63 925#define ROM_SW_DATA_63__ROM_SW_DATA__SHIFT 0x0 926#define ROM_SW_DATA_63__ROM_SW_DATA_MASK 0xFFFFFFFFL 927//ROM_SW_DATA_64 928#define ROM_SW_DATA_64__ROM_SW_DATA__SHIFT 0x0 929#define ROM_SW_DATA_64__ROM_SW_DATA_MASK 0xFFFFFFFFL 930 931 932// addressBlock: smuio_smuio_gpio_SmuSmuioDec 933//SMU_GPIOPAD_SW_INT_STAT 934#define SMU_GPIOPAD_SW_INT_STAT__SW_INT_STAT__SHIFT 0x0 935#define SMU_GPIOPAD_SW_INT_STAT__SW_INT_STAT_MASK 0x00000001L 936//SMU_GPIOPAD_MASK 937#define SMU_GPIOPAD_MASK__GPIO_MASK__SHIFT 0x0 938#define SMU_GPIOPAD_MASK__GPIO_MASK_MASK 0x7FFFFFFFL 939//SMU_GPIOPAD_A 940#define SMU_GPIOPAD_A__GPIO_A__SHIFT 0x0 941#define SMU_GPIOPAD_A__GPIO_A_MASK 0x7FFFFFFFL 942//SMU_GPIOPAD_TXIMPSEL 943#define SMU_GPIOPAD_TXIMPSEL__GPIO_TXIMPSEL__SHIFT 0x0 944#define SMU_GPIOPAD_TXIMPSEL__GPIO_TXIMPSEL_MASK 0x7FFFFFFFL 945//SMU_GPIOPAD_EN 946#define SMU_GPIOPAD_EN__GPIO_EN__SHIFT 0x0 947#define SMU_GPIOPAD_EN__GPIO_EN_MASK 0x7FFFFFFFL 948//SMU_GPIOPAD_Y 949#define SMU_GPIOPAD_Y__GPIO_Y__SHIFT 0x0 950#define SMU_GPIOPAD_Y__GPIO_Y_MASK 0x7FFFFFFFL 951//SMU_GPIOPAD_RXEN 952#define SMU_GPIOPAD_RXEN__GPIO_RXEN__SHIFT 0x0 953#define SMU_GPIOPAD_RXEN__GPIO_RXEN_MASK 0x7FFFFFFFL 954//SMU_GPIOPAD_RCVR_SEL0 955#define SMU_GPIOPAD_RCVR_SEL0__GPIO_RCVR_SEL0__SHIFT 0x0 956#define SMU_GPIOPAD_RCVR_SEL0__GPIO_RCVR_SEL0_MASK 0x7FFFFFFFL 957//SMU_GPIOPAD_RCVR_SEL1 958#define SMU_GPIOPAD_RCVR_SEL1__GPIO_RCVR_SEL1__SHIFT 0x0 959#define SMU_GPIOPAD_RCVR_SEL1__GPIO_RCVR_SEL1_MASK 0x7FFFFFFFL 960//SMU_GPIOPAD_PU_EN 961#define SMU_GPIOPAD_PU_EN__GPIO_PU_EN__SHIFT 0x0 962#define SMU_GPIOPAD_PU_EN__GPIO_PU_EN_MASK 0x7FFFFFFFL 963//SMU_GPIOPAD_PD_EN 964#define SMU_GPIOPAD_PD_EN__GPIO_PD_EN__SHIFT 0x0 965#define SMU_GPIOPAD_PD_EN__GPIO_PD_EN_MASK 0x7FFFFFFFL 966//SMU_GPIOPAD_PINSTRAPS 967#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_0__SHIFT 0x0 968#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_1__SHIFT 0x1 969#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_2__SHIFT 0x2 970#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_3__SHIFT 0x3 971#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_4__SHIFT 0x4 972#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_5__SHIFT 0x5 973#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_6__SHIFT 0x6 974#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_7__SHIFT 0x7 975#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_8__SHIFT 0x8 976#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_9__SHIFT 0x9 977#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_10__SHIFT 0xa 978#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_11__SHIFT 0xb 979#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_12__SHIFT 0xc 980#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_13__SHIFT 0xd 981#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_14__SHIFT 0xe 982#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_15__SHIFT 0xf 983#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_16__SHIFT 0x10 984#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_17__SHIFT 0x11 985#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_18__SHIFT 0x12 986#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_19__SHIFT 0x13 987#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_20__SHIFT 0x14 988#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_21__SHIFT 0x15 989#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_22__SHIFT 0x16 990#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_23__SHIFT 0x17 991#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_24__SHIFT 0x18 992#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_25__SHIFT 0x19 993#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_26__SHIFT 0x1a 994#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_27__SHIFT 0x1b 995#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_28__SHIFT 0x1c 996#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_29__SHIFT 0x1d 997#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_30__SHIFT 0x1e 998#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_0_MASK 0x00000001L 999#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_1_MASK 0x00000002L 1000#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_2_MASK 0x00000004L 1001#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_3_MASK 0x00000008L 1002#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_4_MASK 0x00000010L 1003#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_5_MASK 0x00000020L 1004#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_6_MASK 0x00000040L 1005#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_7_MASK 0x00000080L 1006#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_8_MASK 0x00000100L 1007#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_9_MASK 0x00000200L 1008#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_10_MASK 0x00000400L 1009#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_11_MASK 0x00000800L 1010#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_12_MASK 0x00001000L 1011#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_13_MASK 0x00002000L 1012#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_14_MASK 0x00004000L 1013#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_15_MASK 0x00008000L 1014#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_16_MASK 0x00010000L 1015#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_17_MASK 0x00020000L 1016#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_18_MASK 0x00040000L 1017#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_19_MASK 0x00080000L 1018#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_20_MASK 0x00100000L 1019#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_21_MASK 0x00200000L 1020#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_22_MASK 0x00400000L 1021#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_23_MASK 0x00800000L 1022#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_24_MASK 0x01000000L 1023#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_25_MASK 0x02000000L 1024#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_26_MASK 0x04000000L 1025#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_27_MASK 0x08000000L 1026#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_28_MASK 0x10000000L 1027#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_29_MASK 0x20000000L 1028#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_30_MASK 0x40000000L 1029//DFT_PINSTRAPS 1030#define DFT_PINSTRAPS__DFT_PINSTRAPS__SHIFT 0x0 1031#define DFT_PINSTRAPS__DFT_PINSTRAPS_MASK 0x000000FFL 1032//SMU_GPIOPAD_INT_STAT_EN 1033#define SMU_GPIOPAD_INT_STAT_EN__GPIO_INT_STAT_EN__SHIFT 0x0 1034#define SMU_GPIOPAD_INT_STAT_EN__SW_INITIATED_INT_STAT_EN__SHIFT 0x1f 1035#define SMU_GPIOPAD_INT_STAT_EN__GPIO_INT_STAT_EN_MASK 0x1FFFFFFFL 1036#define SMU_GPIOPAD_INT_STAT_EN__SW_INITIATED_INT_STAT_EN_MASK 0x80000000L 1037//SMU_GPIOPAD_INT_STAT 1038#define SMU_GPIOPAD_INT_STAT__GPIO_INT_STAT__SHIFT 0x0 1039#define SMU_GPIOPAD_INT_STAT__SW_INITIATED_INT_STAT__SHIFT 0x1f 1040#define SMU_GPIOPAD_INT_STAT__GPIO_INT_STAT_MASK 0x1FFFFFFFL 1041#define SMU_GPIOPAD_INT_STAT__SW_INITIATED_INT_STAT_MASK 0x80000000L 1042//SMU_GPIOPAD_INT_STAT_AK 1043#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_0__SHIFT 0x0 1044#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_1__SHIFT 0x1 1045#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_2__SHIFT 0x2 1046#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_3__SHIFT 0x3 1047#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_4__SHIFT 0x4 1048#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_5__SHIFT 0x5 1049#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_6__SHIFT 0x6 1050#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_7__SHIFT 0x7 1051#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_8__SHIFT 0x8 1052#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_9__SHIFT 0x9 1053#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_10__SHIFT 0xa 1054#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_11__SHIFT 0xb 1055#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_12__SHIFT 0xc 1056#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_13__SHIFT 0xd 1057#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_14__SHIFT 0xe 1058#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_15__SHIFT 0xf 1059#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_16__SHIFT 0x10 1060#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_17__SHIFT 0x11 1061#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_18__SHIFT 0x12 1062#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_19__SHIFT 0x13 1063#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_20__SHIFT 0x14 1064#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_21__SHIFT 0x15 1065#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_22__SHIFT 0x16 1066#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_23__SHIFT 0x17 1067#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_24__SHIFT 0x18 1068#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_25__SHIFT 0x19 1069#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_26__SHIFT 0x1a 1070#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_27__SHIFT 0x1b 1071#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_28__SHIFT 0x1c 1072#define SMU_GPIOPAD_INT_STAT_AK__SW_INITIATED_INT_STAT_AK__SHIFT 0x1f 1073#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_0_MASK 0x00000001L 1074#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_1_MASK 0x00000002L 1075#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_2_MASK 0x00000004L 1076#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_3_MASK 0x00000008L 1077#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_4_MASK 0x00000010L 1078#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_5_MASK 0x00000020L 1079#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_6_MASK 0x00000040L 1080#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_7_MASK 0x00000080L 1081#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_8_MASK 0x00000100L 1082#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_9_MASK 0x00000200L 1083#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_10_MASK 0x00000400L 1084#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_11_MASK 0x00000800L 1085#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_12_MASK 0x00001000L 1086#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_13_MASK 0x00002000L 1087#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_14_MASK 0x00004000L 1088#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_15_MASK 0x00008000L 1089#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_16_MASK 0x00010000L 1090#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_17_MASK 0x00020000L 1091#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_18_MASK 0x00040000L 1092#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_19_MASK 0x00080000L 1093#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_20_MASK 0x00100000L 1094#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_21_MASK 0x00200000L 1095#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_22_MASK 0x00400000L 1096#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_23_MASK 0x00800000L 1097#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_24_MASK 0x01000000L 1098#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_25_MASK 0x02000000L 1099#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_26_MASK 0x04000000L 1100#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_27_MASK 0x08000000L 1101#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_28_MASK 0x10000000L 1102#define SMU_GPIOPAD_INT_STAT_AK__SW_INITIATED_INT_STAT_AK_MASK 0x80000000L 1103//SMU_GPIOPAD_INT_EN 1104#define SMU_GPIOPAD_INT_EN__GPIO_INT_EN__SHIFT 0x0 1105#define SMU_GPIOPAD_INT_EN__SW_INITIATED_INT_EN__SHIFT 0x1f 1106#define SMU_GPIOPAD_INT_EN__GPIO_INT_EN_MASK 0x1FFFFFFFL 1107#define SMU_GPIOPAD_INT_EN__SW_INITIATED_INT_EN_MASK 0x80000000L 1108//SMU_GPIOPAD_INT_TYPE 1109#define SMU_GPIOPAD_INT_TYPE__GPIO_INT_TYPE__SHIFT 0x0 1110#define SMU_GPIOPAD_INT_TYPE__SW_INITIATED_INT_TYPE__SHIFT 0x1f 1111#define SMU_GPIOPAD_INT_TYPE__GPIO_INT_TYPE_MASK 0x1FFFFFFFL 1112#define SMU_GPIOPAD_INT_TYPE__SW_INITIATED_INT_TYPE_MASK 0x80000000L 1113//SMU_GPIOPAD_INT_POLARITY 1114#define SMU_GPIOPAD_INT_POLARITY__GPIO_INT_POLARITY__SHIFT 0x0 1115#define SMU_GPIOPAD_INT_POLARITY__SW_INITIATED_INT_POLARITY__SHIFT 0x1f 1116#define SMU_GPIOPAD_INT_POLARITY__GPIO_INT_POLARITY_MASK 0x1FFFFFFFL 1117#define SMU_GPIOPAD_INT_POLARITY__SW_INITIATED_INT_POLARITY_MASK 0x80000000L 1118//SMUIO_PCC_GPIO_SELECT 1119#define SMUIO_PCC_GPIO_SELECT__GPIO__SHIFT 0x0 1120#define SMUIO_PCC_GPIO_SELECT__GPIO_MASK 0xFFFFFFFFL 1121//SMU_GPIOPAD_S0 1122#define SMU_GPIOPAD_S0__GPIO_S0__SHIFT 0x0 1123#define SMU_GPIOPAD_S0__GPIO_S0_MASK 0x7FFFFFFFL 1124//SMU_GPIOPAD_S1 1125#define SMU_GPIOPAD_S1__GPIO_S1__SHIFT 0x0 1126#define SMU_GPIOPAD_S1__GPIO_S1_MASK 0x7FFFFFFFL 1127//SMU_GPIOPAD_SCHMEN 1128#define SMU_GPIOPAD_SCHMEN__GPIO_SCHMEN__SHIFT 0x0 1129#define SMU_GPIOPAD_SCHMEN__GPIO_SCHMEN_MASK 0x7FFFFFFFL 1130//SMU_GPIOPAD_SCL_EN 1131#define SMU_GPIOPAD_SCL_EN__GPIO_SCL_EN__SHIFT 0x0 1132#define SMU_GPIOPAD_SCL_EN__GPIO_SCL_EN_MASK 0x7FFFFFFFL 1133//SMU_GPIOPAD_SDA_EN 1134#define SMU_GPIOPAD_SDA_EN__GPIO_SDA_EN__SHIFT 0x0 1135#define SMU_GPIOPAD_SDA_EN__GPIO_SDA_EN_MASK 0x7FFFFFFFL 1136//SMUIO_GPIO_INT0_SELECT 1137#define SMUIO_GPIO_INT0_SELECT__GPIO_INT0_SELECT__SHIFT 0x0 1138#define SMUIO_GPIO_INT0_SELECT__GPIO_INT0_SELECT_MASK 0xFFFFFFFFL 1139//SMUIO_GPIO_INT1_SELECT 1140#define SMUIO_GPIO_INT1_SELECT__GPIO_INT1_SELECT__SHIFT 0x0 1141#define SMUIO_GPIO_INT1_SELECT__GPIO_INT1_SELECT_MASK 0xFFFFFFFFL 1142//SMUIO_GPIO_INT2_SELECT 1143#define SMUIO_GPIO_INT2_SELECT__GPIO_INT2_SELECT__SHIFT 0x0 1144#define SMUIO_GPIO_INT2_SELECT__GPIO_INT2_SELECT_MASK 0xFFFFFFFFL 1145//SMUIO_GPIO_INT3_SELECT 1146#define SMUIO_GPIO_INT3_SELECT__GPIO_INT3_SELECT__SHIFT 0x0 1147#define SMUIO_GPIO_INT3_SELECT__GPIO_INT3_SELECT_MASK 0xFFFFFFFFL 1148//SMU_GPIOPAD_MP_INT0_STAT 1149#define SMU_GPIOPAD_MP_INT0_STAT__GPIO_MP_INT0_STAT__SHIFT 0x0 1150#define SMU_GPIOPAD_MP_INT0_STAT__GPIO_MP_INT0_STAT_MASK 0x1FFFFFFFL 1151//SMU_GPIOPAD_MP_INT1_STAT 1152#define SMU_GPIOPAD_MP_INT1_STAT__GPIO_MP_INT1_STAT__SHIFT 0x0 1153#define SMU_GPIOPAD_MP_INT1_STAT__GPIO_MP_INT1_STAT_MASK 0x1FFFFFFFL 1154//SMU_GPIOPAD_MP_INT2_STAT 1155#define SMU_GPIOPAD_MP_INT2_STAT__GPIO_MP_INT2_STAT__SHIFT 0x0 1156#define SMU_GPIOPAD_MP_INT2_STAT__GPIO_MP_INT2_STAT_MASK 0x1FFFFFFFL 1157//SMU_GPIOPAD_MP_INT3_STAT 1158#define SMU_GPIOPAD_MP_INT3_STAT__GPIO_MP_INT3_STAT__SHIFT 0x0 1159#define SMU_GPIOPAD_MP_INT3_STAT__GPIO_MP_INT3_STAT_MASK 0x1FFFFFFFL 1160//SMIO_INDEX 1161#define SMIO_INDEX__SW_SMIO_INDEX__SHIFT 0x0 1162#define SMIO_INDEX__SW_SMIO_INDEX_MASK 0x00000001L 1163//S0_VID_SMIO_CNTL 1164#define S0_VID_SMIO_CNTL__S0_SMIO_VALUES__SHIFT 0x0 1165#define S0_VID_SMIO_CNTL__S0_SMIO_VALUES_MASK 0xFFFFFFFFL 1166//S1_VID_SMIO_CNTL 1167#define S1_VID_SMIO_CNTL__S1_SMIO_VALUES__SHIFT 0x0 1168#define S1_VID_SMIO_CNTL__S1_SMIO_VALUES_MASK 0xFFFFFFFFL 1169//OPEN_DRAIN_SELECT 1170#define OPEN_DRAIN_SELECT__OPEN_DRAIN_SELECT__SHIFT 0x0 1171#define OPEN_DRAIN_SELECT__RESERVED__SHIFT 0x1f 1172#define OPEN_DRAIN_SELECT__OPEN_DRAIN_SELECT_MASK 0x7FFFFFFFL 1173#define OPEN_DRAIN_SELECT__RESERVED_MASK 0x80000000L 1174//SMIO_ENABLE 1175#define SMIO_ENABLE__SMIO_ENABLE__SHIFT 0x0 1176#define SMIO_ENABLE__SMIO_ENABLE_MASK 0xFFFFFFFFL 1177 1178#endif 1179