Lines Matching refs:xa
44 #define UVD_CGC_GATE__LBSI__SHIFT 0xa
144 #define AVM_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa
209 #define EFC_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa
274 #define ENT_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa
339 #define IME_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa
404 #define PPU_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa
469 #define SAOE_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa
534 #define SCM_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa
599 #define SDB_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa
664 #define SIT0_NXT_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa
729 #define SIT1_NXT_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa
794 #define SIT2_NXT_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa
859 #define SIT_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa
924 #define SMPA_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa
989 #define SMP_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa
1054 #define SRE_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa
1119 #define UVD_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa
1184 #define AVM_SUVD_CGC_GATE2__SIT_NXT_DEC__SHIFT 0xa
1209 #define DBR_SUVD_CGC_GATE2__SIT_NXT_DEC__SHIFT 0xa
1234 #define ENT_SUVD_CGC_GATE2__SIT_NXT_DEC__SHIFT 0xa
1259 #define IME_SUVD_CGC_GATE2__SIT_NXT_DEC__SHIFT 0xa
1284 #define SAOE_SUVD_CGC_GATE2__SIT_NXT_DEC__SHIFT 0xa
1309 #define SDB_SUVD_CGC_GATE2__SIT_NXT_DEC__SHIFT 0xa
1334 #define SIT0_NXT_SUVD_CGC_GATE2__SIT_NXT_DEC__SHIFT 0xa
1359 #define SIT1_NXT_SUVD_CGC_GATE2__SIT_NXT_DEC__SHIFT 0xa
1384 #define SIT2_NXT_SUVD_CGC_GATE2__SIT_NXT_DEC__SHIFT 0xa
1409 #define SIT_SUVD_CGC_GATE2__SIT_NXT_DEC__SHIFT 0xa
1434 #define SMPA_SUVD_CGC_GATE2__SIT_NXT_DEC__SHIFT 0xa
1459 #define SMP_SUVD_CGC_GATE2__SIT_NXT_DEC__SHIFT 0xa
1484 #define SRE_SUVD_CGC_GATE2__SIT_NXT_DEC__SHIFT 0xa
1509 #define UVD_SUVD_CGC_GATE2__SIT_NXT_DEC__SHIFT 0xa
1534 #define AVM_SUVD_CGC_CTRL__EFC_MODE__SHIFT 0xa
1587 #define DBR_SUVD_CGC_CTRL__EFC_MODE__SHIFT 0xa
1640 #define EFC_SUVD_CGC_CTRL__EFC_MODE__SHIFT 0xa
1693 #define ENT_SUVD_CGC_CTRL__EFC_MODE__SHIFT 0xa
1746 #define IME_SUVD_CGC_CTRL__EFC_MODE__SHIFT 0xa
1799 #define PPU_SUVD_CGC_CTRL__EFC_MODE__SHIFT 0xa
1852 #define SAOE_SUVD_CGC_CTRL__EFC_MODE__SHIFT 0xa
1905 #define SCM_SUVD_CGC_CTRL__EFC_MODE__SHIFT 0xa
1958 #define SDB_SUVD_CGC_CTRL__EFC_MODE__SHIFT 0xa
2011 #define SIT0_NXT_SUVD_CGC_CTRL__EFC_MODE__SHIFT 0xa
2064 #define SIT1_NXT_SUVD_CGC_CTRL__EFC_MODE__SHIFT 0xa
2117 #define SIT2_NXT_SUVD_CGC_CTRL__EFC_MODE__SHIFT 0xa
2170 #define SIT_SUVD_CGC_CTRL__EFC_MODE__SHIFT 0xa
2223 #define SMPA_SUVD_CGC_CTRL__EFC_MODE__SHIFT 0xa
2276 #define SMP_SUVD_CGC_CTRL__EFC_MODE__SHIFT 0xa
2329 #define SRE_SUVD_CGC_CTRL__EFC_MODE__SHIFT 0xa
2382 #define UVD_SUVD_CGC_CTRL__EFC_MODE__SHIFT 0xa
2468 #define UVD_VCPU_INT_EN__SW_RB5_INT_EN__SHIFT 0xa
2523 #define UVD_VCPU_INT_STATUS__SW_RB5_INT__SHIFT 0xa
2580 #define UVD_VCPU_INT_ACK__SW_RB5_INT_ACK__SHIFT 0xa
3114 #define UVD_SUVD_CGC_STATUS2__CDEFE_DCLK__SHIFT 0xa
3188 #define UVD_ENC_PIPE_BUSY__MDM_WR_RECON_BUSY__SHIFT 0xa
3253 #define UVD_FW_POWER_STATUS__UVDNB_PWR_OFF__SHIFT 0xa
3284 #define UVD_SOFT_RESET__IH_SOFT_RESET__SHIFT 0xa
3375 #define UVD_CGC_STATUS__REGS_VCLK__SHIFT 0xa
3440 #define UVD_CGC_UDEC_STATUS__DB_DCLK__SHIFT 0xa
3471 #define UVD_SUVD_CGC_STATUS__SCM_H264_DCLK__SHIFT 0xa
3546 #define CDEFE_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa
3611 #define CDEFE_SUVD_CGC_GATE2__SIT_NXT_DEC__SHIFT 0xa
3636 #define CDEFE_SUVD_CGC_CTRL__EFC_MODE__SHIFT 0xa
3751 #define UVD_VCPU_CNTL__TRCE_EN__SHIFT 0xa
4091 #define UVD_LMI_ARB_CTRL2__MIF_RD_REQ_RET_MAX__SHIFT 0xa
4133 #define UVD_LMI_LAT_CTRL__AVG_START__SHIFT 0xa
4207 #define UVD_LMI_URGENT_CTRL__ASSERT_MC_WR_URGENT__SHIFT 0xa
4274 #define UVD_LMI_STATUS__UMC_UVD_IDLE__SHIFT 0xa
4316 #define UVD_LMI_ADP_SWAP_CNTL__CM_MC_SWAP__SHIFT 0xa
4432 #define UVD_JPEG_INT_EN__RST_ERR_EN__SHIFT 0xa
4459 #define UVD_JPEG_INT_STAT__RST_ERR_INT__SHIFT 0xa
4517 #define UVD_JPEG_TIER_CNTL2__TA__SHIFT 0xa
4688 #define UVD_JRBC_STATUS__RB_TRAP_STATUS__SHIFT 0xa
4850 #define UVD_JMI_DEC_SWAP_CNTL__IB_MEM_RD_MC_SWAP__SHIFT 0xa
4962 #define UVD_JMI_LAT_CTRL__AVG_START__SHIFT 0xa
5133 #define JPEG_MEMCHECK_SYS_INT_STAT2__SCALAR_WR_HI_ERR__SHIFT 0xa
5176 #define JPEG_MEMCHECK_SYS_INT_ACK2__SCALAR_WR_HI_ERR__SHIFT 0xa
5222 #define JPEG_CGC_GATE__JRBBM__SHIFT 0xa
5322 #define UVD_IPX_DLDO_CONFIG__ONO4_PWR_CONFIG__SHIFT 0xa
5505 #define UVD_PF_STATUS__ENCODER0_PF_CLEAR__SHIFT 0xa
5643 #define UVD_GPCNT3_CNTL__DIV__SHIFT 0xa
5692 #define VCN_FEATURES__HAS_AV1_DEC__SHIFT 0xa
5947 #define UMSCH_CTL__UMSCH_BUSY__SHIFT 0xa
6042 #define VCN_UMSCH_MES_BUSY__MesTcBusy__SHIFT 0xa
6890 #define UVD_CGC_MEM_CTRL__VCPU_LS_EN__SHIFT 0xa
6932 #define UVD_CGC_MEM_DS_CTRL__VCPU_DS_EN__SHIFT 0xa
6963 #define UVD_CGC_MEM_SD_CTRL__VCPU_SD_EN__SHIFT 0xa
7106 #define UVD_MEMCHECK_SYS_INT_EN__MIF_BSP0_ERR_EN__SHIFT 0xa
7159 #define UVD_MEMCHECK_SYS_INT_STAT__CM_LO_ERR__SHIFT 0xa
7216 #define UVD_MEMCHECK_SYS_INT_ACK__CM_LO_ACK__SHIFT 0xa
7273 #define UVD_MEMCHECK_VCPU_INT_EN__MIF_BSP0_ERR_EN__SHIFT 0xa
7326 #define UVD_MEMCHECK_VCPU_INT_STAT__CM_LO_ERR__SHIFT 0xa
7383 #define UVD_MEMCHECK_VCPU_INT_ACK__CM_LO_ACK__SHIFT 0xa
7440 #define UVD_MEMCHECK2_SYS_INT_STAT__LBSI_RD_LO_ERR__SHIFT 0xa
7489 #define UVD_MEMCHECK2_SYS_INT_ACK__LBSI_RD_LO_ACK__SHIFT 0xa
7538 #define UVD_MEMCHECK2_VCPU_INT_STAT__LBSI_RD_LO_ERR__SHIFT 0xa
7587 #define UVD_MEMCHECK2_VCPU_INT_ACK__LBSI_RD_LO_ACK__SHIFT 0xa