Lines Matching refs:xa
158 #define UVD_CGC_GATE__LBSI__SHIFT 0xa
202 #define UVD_CGC_STATUS__REGS_VCLK__SHIFT 0xa
314 #define UVD_CGC_UDEC_STATUS__DB_DCLK__SHIFT 0xa
436 #define UVD_LMI_STATUS__UMC_UVD_IDLE__SHIFT 0xa
454 #define UVD_LMI_SWAP_CNTL__CM_MC_SWAP__SHIFT 0xa
484 #define UVD_MP_SWAP_CNTL__MP_REF5_MC_SWAP__SHIFT 0xa
584 #define UVD_VCPU_CNTL__TRCE_EN__SHIFT 0xa
626 #define UVD_SOFT_RESET__IH_SOFT_RESET__SHIFT 0xa
746 #define UVD_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa
772 #define UVD_SUVD_CGC_STATUS__SCM_H264_DCLK__SHIFT 0xa
866 #define UVD_CGC_MEM_CTRL__VCPU_LS_EN__SHIFT 0xa
902 #define UVD_PGFSM_CONFIG__UVD_PGFSM_P1_SELECT__SHIFT 0xa
932 #define UVD_POWER_STATUS__PAUSE_DPG_ACK__SHIFT 0xa