Searched refs:CFG_SYS_SDRAM_BASE (Results 476 - 500 of 556) sorted by relevance

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/u-boot/board/tbs/tbs2910/
H A Dtbs2910.c147 gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
/u-boot/include/configs/
H A DP2041RDB.h64 #define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE macro
H A Dvexpress_aemv8.h99 #define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1 macro
/u-boot/board/Marvell/octeontx2/
H A Dboard.c109 gd->ram_size -= CFG_SYS_SDRAM_BASE;
/u-boot/arch/m68k/cpu/mcf532x/
H A Dspeed.c241 out_be32(sdram_workaround, CFG_SYS_SDRAM_BASE);
/u-boot/board/keymile/pg-wcom-ls102xa/
H A Dpg-wcom-ls102xa.c187 *vstart = CFG_SYS_SDRAM_BASE + (gd->ram_size >> 1);
/u-boot/board/freescale/ls1021atsn/
H A Dls1021atsn.c50 out_be32(&ddr->init_addr, CFG_SYS_SDRAM_BASE);
/u-boot/board/siemens/common/
H A Dboard_am335x.c72 gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
/u-boot/board/cssi/mcr3000/
H A Dmcr3000.c107 gd->ram_size = get_ram_size((long *)CFG_SYS_SDRAM_BASE,
/u-boot/arch/arm/mach-imx/mx6/
H A Dlitesom.c175 ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, SZ_512M);
H A Dopos6ul.c47 gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
/u-boot/board/freescale/ls1021aqds/
H A Dddr.c195 gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
/u-boot/board/eets/pdu001/
H A Dboard.c289 gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
/u-boot/board/bosch/guardian/
H A Dboard.c185 gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
/u-boot/board/esd/meesc/
H A Dmeesc.c267 gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
/u-boot/board/freescale/mx51evk/
H A Dmx51evk.c33 gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE,
/u-boot/board/grinn/chiliboard/
H A Dboard.c98 gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
/u-boot/board/bluewater/gurnard/
H A Dgurnard.c310 gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
410 gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE,
/u-boot/drivers/ram/rockchip/
H A Ddmc-rk3368.c621 writel(0, CFG_SYS_SDRAM_BASE);
622 addr = CFG_SYS_SDRAM_BASE +
626 (readl(CFG_SYS_SDRAM_BASE) == 0))
641 writel(0, CFG_SYS_SDRAM_BASE);
642 addr = CFG_SYS_SDRAM_BASE + (1 << (row + 15 - 1));
645 (readl(CFG_SYS_SDRAM_BASE) == 0))
H A Dsdram_rk3288.c687 writel(0, CFG_SYS_SDRAM_BASE);
688 addr = CFG_SYS_SDRAM_BASE +
692 (readl(CFG_SYS_SDRAM_BASE) == 0))
708 writel(0, CFG_SYS_SDRAM_BASE);
709 addr = CFG_SYS_SDRAM_BASE + (1 << (row + 15 - 1));
712 (readl(CFG_SYS_SDRAM_BASE) == 0))
1090 priv->info.base = CFG_SYS_SDRAM_BASE;
/u-boot/drivers/ram/mediatek/
H A Dddr3-mt7629.c247 writel(WALKING_PATTERN, CFG_SYS_SDRAM_BASE);
249 if (readl(CFG_SYS_SDRAM_BASE) != WALKING_PATTERN)
253 writel(~WALKING_PATTERN, CFG_SYS_SDRAM_BASE +
256 start = readl(CFG_SYS_SDRAM_BASE);
257 test = readl(CFG_SYS_SDRAM_BASE + (WALKING_STEP << step));
731 info->base = CFG_SYS_SDRAM_BASE;
/u-boot/drivers/ram/aspeed/
H A Dsdram_ast2500.c206 const u32 write_addr_base = CFG_SYS_SDRAM_BASE + write_test_offset;
234 info->info.base = CFG_SYS_SDRAM_BASE;
/u-boot/drivers/pci/
H A Dpcie_dw_mvebu.c462 bar0 = CFG_SYS_SDRAM_BASE & ~0xf;
464 writel(CFG_SYS_SDRAM_BASE, regs_base + PCIE_CONFIG_BAR0);
/u-boot/board/friendlyarm/nanopi2/
H A Dboard.c521 gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x00000100;
523 gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
/u-boot/arch/arm/cpu/armv7/ls102xa/
H A Dls102xa_psci.c32 const char *src = (const char *)CFG_SYS_SDRAM_BASE;

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