1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * (C) Copyright 2009 Freescale Semiconductor, Inc. 4 */ 5 6#include <common.h> 7#include <init.h> 8#include <asm/global_data.h> 9#include <asm/io.h> 10#include <asm/gpio.h> 11#include <asm/arch/imx-regs.h> 12#include <asm/arch/iomux-mx51.h> 13#include <linux/delay.h> 14#include <linux/errno.h> 15#include <asm/arch/sys_proto.h> 16#include <asm/arch/crm_regs.h> 17#include <asm/arch/clock.h> 18#include <asm/mach-imx/mx5_video.h> 19#include <i2c.h> 20#include <input.h> 21#include <mmc.h> 22#include <fsl_esdhc_imx.h> 23#include <power/pmic.h> 24#include <fsl_pmic.h> 25#include <mc13892.h> 26#include <usb/ehci-ci.h> 27 28DECLARE_GLOBAL_DATA_PTR; 29 30int dram_init(void) 31{ 32 /* dram_init must store complete ramsize in gd->ram_size */ 33 gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, 34 PHYS_SDRAM_1_SIZE); 35 return 0; 36} 37 38#ifdef CONFIG_REVISION_TAG 39u32 get_board_rev(void) 40{ 41 u32 rev = get_cpu_rev(); 42 if (!gpio_get_value(IMX_GPIO_NR(1, 22))) 43 rev |= BOARD_REV_2_0 << BOARD_VER_OFFSET; 44 return rev; 45} 46#endif 47 48#define UART_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | PAD_CTL_DSE_HIGH) 49 50static void setup_iomux_uart(void) 51{ 52 static const iomux_v3_cfg_t uart_pads[] = { 53 MX51_PAD_UART1_RXD__UART1_RXD, 54 MX51_PAD_UART1_TXD__UART1_TXD, 55 NEW_PAD_CTRL(MX51_PAD_UART1_RTS__UART1_RTS, UART_PAD_CTRL), 56 NEW_PAD_CTRL(MX51_PAD_UART1_CTS__UART1_CTS, UART_PAD_CTRL), 57 }; 58 59 imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads)); 60} 61 62#ifdef CONFIG_MXC_SPI 63static void setup_iomux_spi(void) 64{ 65 static const iomux_v3_cfg_t spi_pads[] = { 66 NEW_PAD_CTRL(MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI, PAD_CTL_HYS | 67 PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST), 68 NEW_PAD_CTRL(MX51_PAD_CSPI1_MISO__ECSPI1_MISO, PAD_CTL_HYS | 69 PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST), 70 NEW_PAD_CTRL(MX51_PAD_CSPI1_SS1__ECSPI1_SS1, 71 MX51_GPIO_PAD_CTRL), 72 MX51_PAD_CSPI1_SS0__ECSPI1_SS0, 73 NEW_PAD_CTRL(MX51_PAD_CSPI1_RDY__ECSPI1_RDY, MX51_PAD_CTRL_2), 74 NEW_PAD_CTRL(MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK, PAD_CTL_HYS | 75 PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST), 76 }; 77 78 imx_iomux_v3_setup_multiple_pads(spi_pads, ARRAY_SIZE(spi_pads)); 79} 80#endif 81 82static void power_init(void) 83{ 84 unsigned int val; 85 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE; 86 struct pmic *p; 87 int ret; 88 89 ret = pmic_init(CFG_FSL_PMIC_BUS); 90 if (ret) 91 return; 92 93 p = pmic_get("FSL_PMIC"); 94 if (!p) 95 return; 96 97 /* Write needed to Power Gate 2 register */ 98 pmic_reg_read(p, REG_POWER_MISC, &val); 99 val &= ~PWGT2SPIEN; 100 pmic_reg_write(p, REG_POWER_MISC, val); 101 102 /* Externally powered */ 103 pmic_reg_read(p, REG_CHARGE, &val); 104 val |= ICHRG0 | ICHRG1 | ICHRG2 | ICHRG3 | CHGAUTOB; 105 pmic_reg_write(p, REG_CHARGE, val); 106 107 /* power up the system first */ 108 pmic_reg_write(p, REG_POWER_MISC, PWUP); 109 110 /* Set core voltage to 1.1V */ 111 pmic_reg_read(p, REG_SW_0, &val); 112 val = (val & ~SWx_VOLT_MASK) | SWx_1_100V; 113 pmic_reg_write(p, REG_SW_0, val); 114 115 /* Setup VCC (SW2) to 1.25 */ 116 pmic_reg_read(p, REG_SW_1, &val); 117 val = (val & ~SWx_VOLT_MASK) | SWx_1_250V; 118 pmic_reg_write(p, REG_SW_1, val); 119 120 /* Setup 1V2_DIG1 (SW3) to 1.25 */ 121 pmic_reg_read(p, REG_SW_2, &val); 122 val = (val & ~SWx_VOLT_MASK) | SWx_1_250V; 123 pmic_reg_write(p, REG_SW_2, val); 124 udelay(50); 125 126 /* Raise the core frequency to 800MHz */ 127 writel(0x0, &mxc_ccm->cacrr); 128 129 /* Set switchers in Auto in NORMAL mode & STANDBY mode */ 130 /* Setup the switcher mode for SW1 & SW2*/ 131 pmic_reg_read(p, REG_SW_4, &val); 132 val = (val & ~((SWMODE_MASK << SWMODE1_SHIFT) | 133 (SWMODE_MASK << SWMODE2_SHIFT))); 134 val |= (SWMODE_AUTO_AUTO << SWMODE1_SHIFT) | 135 (SWMODE_AUTO_AUTO << SWMODE2_SHIFT); 136 pmic_reg_write(p, REG_SW_4, val); 137 138 /* Setup the switcher mode for SW3 & SW4 */ 139 pmic_reg_read(p, REG_SW_5, &val); 140 val = (val & ~((SWMODE_MASK << SWMODE3_SHIFT) | 141 (SWMODE_MASK << SWMODE4_SHIFT))); 142 val |= (SWMODE_AUTO_AUTO << SWMODE3_SHIFT) | 143 (SWMODE_AUTO_AUTO << SWMODE4_SHIFT); 144 pmic_reg_write(p, REG_SW_5, val); 145 146 /* Set VDIG to 1.65V, VGEN3 to 1.8V, VCAM to 2.6V */ 147 pmic_reg_read(p, REG_SETTING_0, &val); 148 val &= ~(VCAM_MASK | VGEN3_MASK | VDIG_MASK); 149 val |= VDIG_1_65 | VGEN3_1_8 | VCAM_2_6; 150 pmic_reg_write(p, REG_SETTING_0, val); 151 152 /* Set VVIDEO to 2.775V, VAUDIO to 3V, VSD to 3.15V */ 153 pmic_reg_read(p, REG_SETTING_1, &val); 154 val &= ~(VVIDEO_MASK | VSD_MASK | VAUDIO_MASK); 155 val |= VSD_3_15 | VAUDIO_3_0 | VVIDEO_2_775; 156 pmic_reg_write(p, REG_SETTING_1, val); 157 158 /* Configure VGEN3 and VCAM regulators to use external PNP */ 159 val = VGEN3CONFIG | VCAMCONFIG; 160 pmic_reg_write(p, REG_MODE_1, val); 161 udelay(200); 162 163 /* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */ 164 val = VGEN3EN | VGEN3CONFIG | VCAMEN | VCAMCONFIG | 165 VVIDEOEN | VAUDIOEN | VSDEN; 166 pmic_reg_write(p, REG_MODE_1, val); 167 168 imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_EIM_A20__GPIO2_14, 169 NO_PAD_CTRL)); 170 gpio_request(IMX_GPIO_NR(2, 14), "gpio2_14"); 171 gpio_direction_output(IMX_GPIO_NR(2, 14), 0); 172 173 udelay(500); 174 175 gpio_set_value(IMX_GPIO_NR(2, 14), 1); 176} 177 178int board_early_init_f(void) 179{ 180 setup_iomux_uart(); 181 setup_iomux_lcd(); 182 183 return 0; 184} 185 186int board_init(void) 187{ 188 /* address of boot parameters */ 189 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; 190 191 return 0; 192} 193 194#ifdef CONFIG_BOARD_LATE_INIT 195int board_late_init(void) 196{ 197#ifdef CONFIG_MXC_SPI 198 setup_iomux_spi(); 199 power_init(); 200#endif 201 202 return 0; 203} 204#endif 205 206/* 207 * Do not overwrite the console 208 * Use always serial for U-Boot console 209 */ 210int overwrite_console(void) 211{ 212 return 1; 213} 214 215int checkboard(void) 216{ 217 puts("Board: MX51EVK\n"); 218 219 return 0; 220} 221