1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright 2020 Hitachi Power Grids. All rights reserved. 4 */ 5 6#include <config.h> 7#include <event.h> 8#include <i2c.h> 9#include <asm/io.h> 10#include <asm/arch/immap_ls102xa.h> 11#include <asm/arch/clock.h> 12#include <asm/arch/fsl_serdes.h> 13#include <asm/arch/ls102xa_devdis.h> 14#include <asm/arch/ls102xa_soc.h> 15#include <hwconfig.h> 16#include <mmc.h> 17#include <fsl_csu.h> 18#include <fsl_esdhc.h> 19#include <fsl_ifc.h> 20#include <fsl_immap.h> 21#include <netdev.h> 22#include <fsl_mdio.h> 23#include <tsec.h> 24#include <fsl_sec.h> 25#include <fsl_devdis.h> 26#include <fsl_ddr.h> 27#include <spl.h> 28#include <fdt_support.h> 29#include <fsl_qe.h> 30#include <fsl_validate.h> 31 32#include "../common/common.h" 33#include "../common/qrio.h" 34 35DECLARE_GLOBAL_DATA_PTR; 36 37static uchar ivm_content[CONFIG_SYS_IVM_EEPROM_MAX_LEN]; 38 39int checkboard(void) 40{ 41 show_qrio(); 42 43 return 0; 44} 45 46int dram_init(void) 47{ 48 return fsl_initdram(); 49} 50 51int board_early_init_f(void) 52{ 53 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR; 54 struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR; 55 struct fsl_ifc ifc = {(void *)CFG_SYS_IFC_ADDR, (void *)NULL}; 56 57 /* Disable unused MCK1 */ 58 setbits_be32(&gur->ddrclkdr, 2); 59 60 /* IFC Global Configuration */ 61 setbits_be32(&ifc.gregs->ifc_gcr, 12 << IFC_GCR_TBCTL_TRN_TIME_SHIFT); 62 setbits_be32(&ifc.gregs->ifc_ccr, IFC_CCR_CLK_DIV(3) | 63 IFC_CCR_INV_CLK_EN); 64 65 /* clear BD & FR bits for BE BD's and frame data */ 66 clrbits_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR); 67 out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125); 68 69 init_early_memctl_regs(); 70 71 /* QRIO Configuration */ 72 qrio_uprstreq(UPREQ_CORE_RST); 73 74#if IS_ENABLED(CONFIG_TARGET_PG_WCOM_SELI8) 75 qrio_prstcfg(KM_LIU_RST, PRSTCFG_POWUP_UNIT_RST); 76 qrio_wdmask(KM_LIU_RST, true); 77 78 qrio_prstcfg(KM_PAXK_RST, PRSTCFG_POWUP_UNIT_RST); 79 qrio_wdmask(KM_PAXK_RST, true); 80#endif 81 82#if IS_ENABLED(CONFIG_TARGET_PG_WCOM_EXPU1) 83 qrio_prstcfg(WCOM_TMG_RST, PRSTCFG_POWUP_UNIT_RST); 84 qrio_wdmask(WCOM_TMG_RST, true); 85 86 qrio_prstcfg(WCOM_PHY_RST, PRSTCFG_POWUP_UNIT_RST); 87 qrio_prst(WCOM_PHY_RST, false, false); 88 89 qrio_prstcfg(WCOM_QSFP_RST, PRSTCFG_POWUP_UNIT_RST); 90 qrio_wdmask(WCOM_QSFP_RST, true); 91 92 qrio_prstcfg(WCOM_CLIPS_RST, PRSTCFG_POWUP_UNIT_RST); 93 qrio_prst(WCOM_CLIPS_RST, false, false); 94#endif 95 96 /* deasset debug phy reset only if piggy is present */ 97 qrio_prstcfg(KM_DBG_ETH_RST, PRSTCFG_POWUP_UNIT_CORE_RST); 98 qrio_prst(KM_DBG_ETH_RST, !qrio_get_pgy_pres_pin(), false); 99 100 i2c_deblock_gpio_cfg(); 101 102 /* enable the Unit LED (red) & Boot LED (on) */ 103 qrio_set_leds(); 104 105 /* enable Application Buffer */ 106 qrio_enable_app_buffer(); 107 108 arch_soc_init(); 109 110 return 0; 111} 112 113static int pg_wcom_misc_init_f(void) 114{ 115 if (IS_ENABLED(CONFIG_PG_WCOM_UBOOT_UPDATE_SUPPORTED)) 116 check_for_uboot_update(); 117 118 return 0; 119} 120EVENT_SPY_SIMPLE(EVT_MISC_INIT_F, pg_wcom_misc_init_f); 121 122int board_init(void) 123{ 124 if (IS_ENABLED(CONFIG_SYS_FSL_ERRATUM_A010315)) 125 erratum_a010315(); 126 127 fsl_serdes_init(); 128 129 ls102xa_smmu_stream_id_init(); 130 131 u_qe_init(); 132 133 return 0; 134} 135 136int board_late_init(void) 137{ 138 return 0; 139} 140 141int misc_init_r(void) 142{ 143 device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl)); 144 145 ivm_read_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN, 146 CONFIG_PIGGY_MAC_ADDRESS_OFFSET); 147 148 return 0; 149} 150 151int ft_board_setup(void *blob, struct bd_info *bd) 152{ 153 ft_cpu_setup(blob, bd); 154 155 if (IS_ENABLED(CONFIG_PCI)) 156 ft_pci_setup(blob, bd); 157 158 return 0; 159} 160 161#if defined(CONFIG_POST) 162int post_hotkeys_pressed(void) 163{ 164 /* DIC26_SELFTEST: QRIO, SLFTEST */ 165 return qrio_get_selftest_pin(); 166} 167 168/* POST word is located in the unused SCRATCHRW4 register */ 169#define CCSR_SCRATCHRW4_ADDR 0x1ee020c 170 171ulong post_word_load(void) 172{ 173 void *addr = (void *)CCSR_SCRATCHRW4_ADDR; 174 return in_le32(addr); 175} 176 177void post_word_store(ulong value) 178{ 179 void *addr = (void *)CCSR_SCRATCHRW4_ADDR; 180 out_le32(addr, value); 181} 182 183int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset) 184{ 185 /* Define only 1MiB range for mem_regions at the middle of the RAM */ 186 /* For 1GiB range mem_regions takes approx. 4min */ 187 *vstart = CFG_SYS_SDRAM_BASE + (gd->ram_size >> 1); 188 *size = 1 << 20; 189 return 0; 190} 191#endif 192 193u8 flash_read8(void *addr) 194{ 195 return __raw_readb(addr + 1); 196} 197 198void flash_write16(u16 val, void *addr) 199{ 200 u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00)); 201 202 __raw_writew(shftval, addr); 203} 204 205u16 flash_read16(void *addr) 206{ 207 u16 val = __raw_readw(addr); 208 209 return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00); 210} 211 212int hush_init_var(void) 213{ 214 ivm_analyze_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN); 215 return 0; 216} 217 218EVENT_SPY_SIMPLE(EVT_LAST_STAGE_INIT, set_km_env); 219