#
322ca743 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
pg-wcom-ls102xa: Include <config.h> in the board file Given that this file references CFG_* defines, we need to be explicit in our inclusion of config.h, so that these will be defined. Reviewed-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitacienergy.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
5faf66a2 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
fsl_qe: Drop common.h In both include/fsl_qe.h and then also remove common.h from the files which had included fsl_qe.h Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
322ca743 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
pg-wcom-ls102xa: Include <config.h> in the board file Given that this file references CFG_* defines, we need to be explicit in our inclusion of config.h, so that these will be defined. Reviewed-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitacienergy.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
5faf66a2 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
fsl_qe: Drop common.h In both include/fsl_qe.h and then also remove common.h from the files which had included fsl_qe.h Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
322ca743 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
pg-wcom-ls102xa: Include <config.h> in the board file Given that this file references CFG_* defines, we need to be explicit in our inclusion of config.h, so that these will be defined. Reviewed-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitacienergy.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
5faf66a2 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
fsl_qe: Drop common.h In both include/fsl_qe.h and then also remove common.h from the files which had included fsl_qe.h Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
322ca743 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
pg-wcom-ls102xa: Include <config.h> in the board file Given that this file references CFG_* defines, we need to be explicit in our inclusion of config.h, so that these will be defined. Reviewed-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitacienergy.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
5faf66a2 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
fsl_qe: Drop common.h In both include/fsl_qe.h and then also remove common.h from the files which had included fsl_qe.h Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
322ca743 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
pg-wcom-ls102xa: Include <config.h> in the board file Given that this file references CFG_* defines, we need to be explicit in our inclusion of config.h, so that these will be defined. Reviewed-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitacienergy.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
5faf66a2 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
fsl_qe: Drop common.h In both include/fsl_qe.h and then also remove common.h from the files which had included fsl_qe.h Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
322ca743 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
pg-wcom-ls102xa: Include <config.h> in the board file Given that this file references CFG_* defines, we need to be explicit in our inclusion of config.h, so that these will be defined. Reviewed-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitacienergy.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
5faf66a2 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
fsl_qe: Drop common.h In both include/fsl_qe.h and then also remove common.h from the files which had included fsl_qe.h Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
322ca743 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
pg-wcom-ls102xa: Include <config.h> in the board file Given that this file references CFG_* defines, we need to be explicit in our inclusion of config.h, so that these will be defined. Reviewed-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitacienergy.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
5faf66a2 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
fsl_qe: Drop common.h In both include/fsl_qe.h and then also remove common.h from the files which had included fsl_qe.h Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
322ca743 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
pg-wcom-ls102xa: Include <config.h> in the board file Given that this file references CFG_* defines, we need to be explicit in our inclusion of config.h, so that these will be defined. Reviewed-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitacienergy.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
5faf66a2 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
fsl_qe: Drop common.h In both include/fsl_qe.h and then also remove common.h from the files which had included fsl_qe.h Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
322ca743 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
pg-wcom-ls102xa: Include <config.h> in the board file Given that this file references CFG_* defines, we need to be explicit in our inclusion of config.h, so that these will be defined. Reviewed-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitacienergy.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
5faf66a2 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
fsl_qe: Drop common.h In both include/fsl_qe.h and then also remove common.h from the files which had included fsl_qe.h Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
322ca743 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
pg-wcom-ls102xa: Include <config.h> in the board file Given that this file references CFG_* defines, we need to be explicit in our inclusion of config.h, so that these will be defined. Reviewed-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitacienergy.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
5faf66a2 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
fsl_qe: Drop common.h In both include/fsl_qe.h and then also remove common.h from the files which had included fsl_qe.h Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
322ca743 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
pg-wcom-ls102xa: Include <config.h> in the board file Given that this file references CFG_* defines, we need to be explicit in our inclusion of config.h, so that these will be defined. Reviewed-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitacienergy.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
5faf66a2 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
fsl_qe: Drop common.h In both include/fsl_qe.h and then also remove common.h from the files which had included fsl_qe.h Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
322ca743 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
pg-wcom-ls102xa: Include <config.h> in the board file Given that this file references CFG_* defines, we need to be explicit in our inclusion of config.h, so that these will be defined. Reviewed-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitacienergy.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
5faf66a2 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
fsl_qe: Drop common.h In both include/fsl_qe.h and then also remove common.h from the files which had included fsl_qe.h Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
322ca743 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
pg-wcom-ls102xa: Include <config.h> in the board file Given that this file references CFG_* defines, we need to be explicit in our inclusion of config.h, so that these will be defined. Reviewed-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitacienergy.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
5faf66a2 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
fsl_qe: Drop common.h In both include/fsl_qe.h and then also remove common.h from the files which had included fsl_qe.h Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
322ca743 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
pg-wcom-ls102xa: Include <config.h> in the board file Given that this file references CFG_* defines, we need to be explicit in our inclusion of config.h, so that these will be defined. Reviewed-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitacienergy.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
5faf66a2 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
fsl_qe: Drop common.h In both include/fsl_qe.h and then also remove common.h from the files which had included fsl_qe.h Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
322ca743 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
pg-wcom-ls102xa: Include <config.h> in the board file Given that this file references CFG_* defines, we need to be explicit in our inclusion of config.h, so that these will be defined. Reviewed-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitacienergy.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
5faf66a2 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
fsl_qe: Drop common.h In both include/fsl_qe.h and then also remove common.h from the files which had included fsl_qe.h Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
322ca743 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
pg-wcom-ls102xa: Include <config.h> in the board file Given that this file references CFG_* defines, we need to be explicit in our inclusion of config.h, so that these will be defined. Reviewed-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitacienergy.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
5faf66a2 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
fsl_qe: Drop common.h In both include/fsl_qe.h and then also remove common.h from the files which had included fsl_qe.h Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
322ca743 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
pg-wcom-ls102xa: Include <config.h> in the board file Given that this file references CFG_* defines, we need to be explicit in our inclusion of config.h, so that these will be defined. Reviewed-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitacienergy.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
5faf66a2 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
fsl_qe: Drop common.h In both include/fsl_qe.h and then also remove common.h from the files which had included fsl_qe.h Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
322ca743 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
pg-wcom-ls102xa: Include <config.h> in the board file Given that this file references CFG_* defines, we need to be explicit in our inclusion of config.h, so that these will be defined. Reviewed-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitacienergy.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
5faf66a2 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
fsl_qe: Drop common.h In both include/fsl_qe.h and then also remove common.h from the files which had included fsl_qe.h Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
322ca743 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
pg-wcom-ls102xa: Include <config.h> in the board file Given that this file references CFG_* defines, we need to be explicit in our inclusion of config.h, so that these will be defined. Reviewed-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitacienergy.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
5faf66a2 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
fsl_qe: Drop common.h In both include/fsl_qe.h and then also remove common.h from the files which had included fsl_qe.h Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
322ca743 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
pg-wcom-ls102xa: Include <config.h> in the board file Given that this file references CFG_* defines, we need to be explicit in our inclusion of config.h, so that these will be defined. Reviewed-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitacienergy.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
5faf66a2 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
fsl_qe: Drop common.h In both include/fsl_qe.h and then also remove common.h from the files which had included fsl_qe.h Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
322ca743 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
pg-wcom-ls102xa: Include <config.h> in the board file Given that this file references CFG_* defines, we need to be explicit in our inclusion of config.h, so that these will be defined. Reviewed-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitacienergy.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
5faf66a2 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
fsl_qe: Drop common.h In both include/fsl_qe.h and then also remove common.h from the files which had included fsl_qe.h Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
322ca743 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
pg-wcom-ls102xa: Include <config.h> in the board file Given that this file references CFG_* defines, we need to be explicit in our inclusion of config.h, so that these will be defined. Reviewed-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitacienergy.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
5faf66a2 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
fsl_qe: Drop common.h In both include/fsl_qe.h and then also remove common.h from the files which had included fsl_qe.h Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
322ca743 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
pg-wcom-ls102xa: Include <config.h> in the board file Given that this file references CFG_* defines, we need to be explicit in our inclusion of config.h, so that these will be defined. Reviewed-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitacienergy.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
5faf66a2 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
fsl_qe: Drop common.h In both include/fsl_qe.h and then also remove common.h from the files which had included fsl_qe.h Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
322ca743 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
pg-wcom-ls102xa: Include <config.h> in the board file Given that this file references CFG_* defines, we need to be explicit in our inclusion of config.h, so that these will be defined. Reviewed-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitacienergy.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
5faf66a2 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
fsl_qe: Drop common.h In both include/fsl_qe.h and then also remove common.h from the files which had included fsl_qe.h Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
322ca743 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
pg-wcom-ls102xa: Include <config.h> in the board file Given that this file references CFG_* defines, we need to be explicit in our inclusion of config.h, so that these will be defined. Reviewed-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitacienergy.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
5faf66a2 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
fsl_qe: Drop common.h In both include/fsl_qe.h and then also remove common.h from the files which had included fsl_qe.h Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
322ca743 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
pg-wcom-ls102xa: Include <config.h> in the board file Given that this file references CFG_* defines, we need to be explicit in our inclusion of config.h, so that these will be defined. Reviewed-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitacienergy.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
5faf66a2 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
fsl_qe: Drop common.h In both include/fsl_qe.h and then also remove common.h from the files which had included fsl_qe.h Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
322ca743 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
pg-wcom-ls102xa: Include <config.h> in the board file Given that this file references CFG_* defines, we need to be explicit in our inclusion of config.h, so that these will be defined. Reviewed-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitacienergy.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
5faf66a2 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
fsl_qe: Drop common.h In both include/fsl_qe.h and then also remove common.h from the files which had included fsl_qe.h Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
322ca743 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
pg-wcom-ls102xa: Include <config.h> in the board file Given that this file references CFG_* defines, we need to be explicit in our inclusion of config.h, so that these will be defined. Reviewed-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitacienergy.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
5faf66a2 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
fsl_qe: Drop common.h In both include/fsl_qe.h and then also remove common.h from the files which had included fsl_qe.h Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
322ca743 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
pg-wcom-ls102xa: Include <config.h> in the board file Given that this file references CFG_* defines, we need to be explicit in our inclusion of config.h, so that these will be defined. Reviewed-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitacienergy.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
5faf66a2 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
fsl_qe: Drop common.h In both include/fsl_qe.h and then also remove common.h from the files which had included fsl_qe.h Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
322ca743 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
pg-wcom-ls102xa: Include <config.h> in the board file Given that this file references CFG_* defines, we need to be explicit in our inclusion of config.h, so that these will be defined. Reviewed-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitacienergy.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
5faf66a2 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
fsl_qe: Drop common.h In both include/fsl_qe.h and then also remove common.h from the files which had included fsl_qe.h Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
322ca743 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
pg-wcom-ls102xa: Include <config.h> in the board file Given that this file references CFG_* defines, we need to be explicit in our inclusion of config.h, so that these will be defined. Reviewed-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitacienergy.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
5faf66a2 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
fsl_qe: Drop common.h In both include/fsl_qe.h and then also remove common.h from the files which had included fsl_qe.h Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
322ca743 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
pg-wcom-ls102xa: Include <config.h> in the board file Given that this file references CFG_* defines, we need to be explicit in our inclusion of config.h, so that these will be defined. Reviewed-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitacienergy.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
5faf66a2 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
fsl_qe: Drop common.h In both include/fsl_qe.h and then also remove common.h from the files which had included fsl_qe.h Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
322ca743 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
pg-wcom-ls102xa: Include <config.h> in the board file Given that this file references CFG_* defines, we need to be explicit in our inclusion of config.h, so that these will be defined. Reviewed-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitacienergy.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
5faf66a2 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
fsl_qe: Drop common.h In both include/fsl_qe.h and then also remove common.h from the files which had included fsl_qe.h Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
322ca743 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
pg-wcom-ls102xa: Include <config.h> in the board file Given that this file references CFG_* defines, we need to be explicit in our inclusion of config.h, so that these will be defined. Reviewed-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitacienergy.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
5faf66a2 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
fsl_qe: Drop common.h In both include/fsl_qe.h and then also remove common.h from the files which had included fsl_qe.h Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
322ca743 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
pg-wcom-ls102xa: Include <config.h> in the board file Given that this file references CFG_* defines, we need to be explicit in our inclusion of config.h, so that these will be defined. Reviewed-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitacienergy.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
5faf66a2 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
fsl_qe: Drop common.h In both include/fsl_qe.h and then also remove common.h from the files which had included fsl_qe.h Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
322ca743 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
pg-wcom-ls102xa: Include <config.h> in the board file Given that this file references CFG_* defines, we need to be explicit in our inclusion of config.h, so that these will be defined. Reviewed-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitacienergy.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
5faf66a2 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
fsl_qe: Drop common.h In both include/fsl_qe.h and then also remove common.h from the files which had included fsl_qe.h Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
322ca743 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
pg-wcom-ls102xa: Include <config.h> in the board file Given that this file references CFG_* defines, we need to be explicit in our inclusion of config.h, so that these will be defined. Reviewed-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitacienergy.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
5faf66a2 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
fsl_qe: Drop common.h In both include/fsl_qe.h and then also remove common.h from the files which had included fsl_qe.h Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
322ca743 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
pg-wcom-ls102xa: Include <config.h> in the board file Given that this file references CFG_* defines, we need to be explicit in our inclusion of config.h, so that these will be defined. Reviewed-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitacienergy.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
5faf66a2 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
fsl_qe: Drop common.h In both include/fsl_qe.h and then also remove common.h from the files which had included fsl_qe.h Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
322ca743 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
pg-wcom-ls102xa: Include <config.h> in the board file Given that this file references CFG_* defines, we need to be explicit in our inclusion of config.h, so that these will be defined. Reviewed-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitacienergy.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
5faf66a2 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
fsl_qe: Drop common.h In both include/fsl_qe.h and then also remove common.h from the files which had included fsl_qe.h Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
322ca743 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
pg-wcom-ls102xa: Include <config.h> in the board file Given that this file references CFG_* defines, we need to be explicit in our inclusion of config.h, so that these will be defined. Reviewed-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitacienergy.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
5faf66a2 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
fsl_qe: Drop common.h In both include/fsl_qe.h and then also remove common.h from the files which had included fsl_qe.h Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
322ca743 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
pg-wcom-ls102xa: Include <config.h> in the board file Given that this file references CFG_* defines, we need to be explicit in our inclusion of config.h, so that these will be defined. Reviewed-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitacienergy.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
5faf66a2 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
fsl_qe: Drop common.h In both include/fsl_qe.h and then also remove common.h from the files which had included fsl_qe.h Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
322ca743 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
pg-wcom-ls102xa: Include <config.h> in the board file Given that this file references CFG_* defines, we need to be explicit in our inclusion of config.h, so that these will be defined. Reviewed-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitacienergy.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
5faf66a2 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
fsl_qe: Drop common.h In both include/fsl_qe.h and then also remove common.h from the files which had included fsl_qe.h Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
322ca743 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
pg-wcom-ls102xa: Include <config.h> in the board file Given that this file references CFG_* defines, we need to be explicit in our inclusion of config.h, so that these will be defined. Reviewed-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitacienergy.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
5faf66a2 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
fsl_qe: Drop common.h In both include/fsl_qe.h and then also remove common.h from the files which had included fsl_qe.h Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
322ca743 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
pg-wcom-ls102xa: Include <config.h> in the board file Given that this file references CFG_* defines, we need to be explicit in our inclusion of config.h, so that these will be defined. Reviewed-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitacienergy.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
5faf66a2 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
fsl_qe: Drop common.h In both include/fsl_qe.h and then also remove common.h from the files which had included fsl_qe.h Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
322ca743 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
pg-wcom-ls102xa: Include <config.h> in the board file Given that this file references CFG_* defines, we need to be explicit in our inclusion of config.h, so that these will be defined. Reviewed-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitacienergy.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
5faf66a2 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
fsl_qe: Drop common.h In both include/fsl_qe.h and then also remove common.h from the files which had included fsl_qe.h Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
322ca743 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
pg-wcom-ls102xa: Include <config.h> in the board file Given that this file references CFG_* defines, we need to be explicit in our inclusion of config.h, so that these will be defined. Reviewed-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitacienergy.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
5faf66a2 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
fsl_qe: Drop common.h In both include/fsl_qe.h and then also remove common.h from the files which had included fsl_qe.h Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
322ca743 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
pg-wcom-ls102xa: Include <config.h> in the board file Given that this file references CFG_* defines, we need to be explicit in our inclusion of config.h, so that these will be defined. Reviewed-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitacienergy.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
5faf66a2 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
fsl_qe: Drop common.h In both include/fsl_qe.h and then also remove common.h from the files which had included fsl_qe.h Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
322ca743 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
pg-wcom-ls102xa: Include <config.h> in the board file Given that this file references CFG_* defines, we need to be explicit in our inclusion of config.h, so that these will be defined. Reviewed-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitacienergy.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
5faf66a2 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
fsl_qe: Drop common.h In both include/fsl_qe.h and then also remove common.h from the files which had included fsl_qe.h Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
322ca743 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
pg-wcom-ls102xa: Include <config.h> in the board file Given that this file references CFG_* defines, we need to be explicit in our inclusion of config.h, so that these will be defined. Reviewed-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitacienergy.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
5faf66a2 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
fsl_qe: Drop common.h In both include/fsl_qe.h and then also remove common.h from the files which had included fsl_qe.h Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
322ca743 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
pg-wcom-ls102xa: Include <config.h> in the board file Given that this file references CFG_* defines, we need to be explicit in our inclusion of config.h, so that these will be defined. Reviewed-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitacienergy.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
5faf66a2 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
fsl_qe: Drop common.h In both include/fsl_qe.h and then also remove common.h from the files which had included fsl_qe.h Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
322ca743 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
pg-wcom-ls102xa: Include <config.h> in the board file Given that this file references CFG_* defines, we need to be explicit in our inclusion of config.h, so that these will be defined. Reviewed-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitacienergy.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
5faf66a2 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
fsl_qe: Drop common.h In both include/fsl_qe.h and then also remove common.h from the files which had included fsl_qe.h Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
322ca743 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
pg-wcom-ls102xa: Include <config.h> in the board file Given that this file references CFG_* defines, we need to be explicit in our inclusion of config.h, so that these will be defined. Reviewed-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitacienergy.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
5faf66a2 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
fsl_qe: Drop common.h In both include/fsl_qe.h and then also remove common.h from the files which had included fsl_qe.h Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
322ca743 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
pg-wcom-ls102xa: Include <config.h> in the board file Given that this file references CFG_* defines, we need to be explicit in our inclusion of config.h, so that these will be defined. Reviewed-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitacienergy.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
5faf66a2 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
fsl_qe: Drop common.h In both include/fsl_qe.h and then also remove common.h from the files which had included fsl_qe.h Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
322ca743 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
pg-wcom-ls102xa: Include <config.h> in the board file Given that this file references CFG_* defines, we need to be explicit in our inclusion of config.h, so that these will be defined. Reviewed-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitacienergy.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
5faf66a2 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
fsl_qe: Drop common.h In both include/fsl_qe.h and then also remove common.h from the files which had included fsl_qe.h Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
322ca743 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
pg-wcom-ls102xa: Include <config.h> in the board file Given that this file references CFG_* defines, we need to be explicit in our inclusion of config.h, so that these will be defined. Reviewed-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitacienergy.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
5faf66a2 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
fsl_qe: Drop common.h In both include/fsl_qe.h and then also remove common.h from the files which had included fsl_qe.h Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
322ca743 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
pg-wcom-ls102xa: Include <config.h> in the board file Given that this file references CFG_* defines, we need to be explicit in our inclusion of config.h, so that these will be defined. Reviewed-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitacienergy.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
5faf66a2 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
fsl_qe: Drop common.h In both include/fsl_qe.h and then also remove common.h from the files which had included fsl_qe.h Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
322ca743 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
pg-wcom-ls102xa: Include <config.h> in the board file Given that this file references CFG_* defines, we need to be explicit in our inclusion of config.h, so that these will be defined. Reviewed-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitacienergy.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
5faf66a2 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
fsl_qe: Drop common.h In both include/fsl_qe.h and then also remove common.h from the files which had included fsl_qe.h Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
322ca743 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
pg-wcom-ls102xa: Include <config.h> in the board file Given that this file references CFG_* defines, we need to be explicit in our inclusion of config.h, so that these will be defined. Reviewed-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitacienergy.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
5faf66a2 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
fsl_qe: Drop common.h In both include/fsl_qe.h and then also remove common.h from the files which had included fsl_qe.h Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
322ca743 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
pg-wcom-ls102xa: Include <config.h> in the board file Given that this file references CFG_* defines, we need to be explicit in our inclusion of config.h, so that these will be defined. Reviewed-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitacienergy.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
5faf66a2 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
fsl_qe: Drop common.h In both include/fsl_qe.h and then also remove common.h from the files which had included fsl_qe.h Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
322ca743 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
pg-wcom-ls102xa: Include <config.h> in the board file Given that this file references CFG_* defines, we need to be explicit in our inclusion of config.h, so that these will be defined. Reviewed-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitacienergy.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
5faf66a2 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
fsl_qe: Drop common.h In both include/fsl_qe.h and then also remove common.h from the files which had included fsl_qe.h Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
322ca743 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
pg-wcom-ls102xa: Include <config.h> in the board file Given that this file references CFG_* defines, we need to be explicit in our inclusion of config.h, so that these will be defined. Reviewed-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitacienergy.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
5faf66a2 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
fsl_qe: Drop common.h In both include/fsl_qe.h and then also remove common.h from the files which had included fsl_qe.h Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
322ca743 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
pg-wcom-ls102xa: Include <config.h> in the board file Given that this file references CFG_* defines, we need to be explicit in our inclusion of config.h, so that these will be defined. Reviewed-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitacienergy.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
5faf66a2 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
fsl_qe: Drop common.h In both include/fsl_qe.h and then also remove common.h from the files which had included fsl_qe.h Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
322ca743 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
pg-wcom-ls102xa: Include <config.h> in the board file Given that this file references CFG_* defines, we need to be explicit in our inclusion of config.h, so that these will be defined. Reviewed-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitacienergy.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
5faf66a2 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
fsl_qe: Drop common.h In both include/fsl_qe.h and then also remove common.h from the files which had included fsl_qe.h Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
322ca743 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
pg-wcom-ls102xa: Include <config.h> in the board file Given that this file references CFG_* defines, we need to be explicit in our inclusion of config.h, so that these will be defined. Reviewed-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitacienergy.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
5faf66a2 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
fsl_qe: Drop common.h In both include/fsl_qe.h and then also remove common.h from the files which had included fsl_qe.h Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
322ca743 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
pg-wcom-ls102xa: Include <config.h> in the board file Given that this file references CFG_* defines, we need to be explicit in our inclusion of config.h, so that these will be defined. Reviewed-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitacienergy.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
5faf66a2 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
fsl_qe: Drop common.h In both include/fsl_qe.h and then also remove common.h from the files which had included fsl_qe.h Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
322ca743 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
pg-wcom-ls102xa: Include <config.h> in the board file Given that this file references CFG_* defines, we need to be explicit in our inclusion of config.h, so that these will be defined. Reviewed-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitacienergy.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
5faf66a2 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
fsl_qe: Drop common.h In both include/fsl_qe.h and then also remove common.h from the files which had included fsl_qe.h Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
322ca743 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
pg-wcom-ls102xa: Include <config.h> in the board file Given that this file references CFG_* defines, we need to be explicit in our inclusion of config.h, so that these will be defined. Reviewed-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitacienergy.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
5faf66a2 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
fsl_qe: Drop common.h In both include/fsl_qe.h and then also remove common.h from the files which had included fsl_qe.h Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
322ca743 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
pg-wcom-ls102xa: Include <config.h> in the board file Given that this file references CFG_* defines, we need to be explicit in our inclusion of config.h, so that these will be defined. Reviewed-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitacienergy.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
5faf66a2 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
fsl_qe: Drop common.h In both include/fsl_qe.h and then also remove common.h from the files which had included fsl_qe.h Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
322ca743 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
pg-wcom-ls102xa: Include <config.h> in the board file Given that this file references CFG_* defines, we need to be explicit in our inclusion of config.h, so that these will be defined. Reviewed-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitacienergy.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
5faf66a2 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
fsl_qe: Drop common.h In both include/fsl_qe.h and then also remove common.h from the files which had included fsl_qe.h Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
322ca743 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
pg-wcom-ls102xa: Include <config.h> in the board file Given that this file references CFG_* defines, we need to be explicit in our inclusion of config.h, so that these will be defined. Reviewed-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitacienergy.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
5faf66a2 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
fsl_qe: Drop common.h In both include/fsl_qe.h and then also remove common.h from the files which had included fsl_qe.h Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
322ca743 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
pg-wcom-ls102xa: Include <config.h> in the board file Given that this file references CFG_* defines, we need to be explicit in our inclusion of config.h, so that these will be defined. Reviewed-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitacienergy.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
5faf66a2 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
fsl_qe: Drop common.h In both include/fsl_qe.h and then also remove common.h from the files which had included fsl_qe.h Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
322ca743 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
pg-wcom-ls102xa: Include <config.h> in the board file Given that this file references CFG_* defines, we need to be explicit in our inclusion of config.h, so that these will be defined. Reviewed-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitacienergy.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
5faf66a2 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
fsl_qe: Drop common.h In both include/fsl_qe.h and then also remove common.h from the files which had included fsl_qe.h Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
322ca743 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
pg-wcom-ls102xa: Include <config.h> in the board file Given that this file references CFG_* defines, we need to be explicit in our inclusion of config.h, so that these will be defined. Reviewed-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitacienergy.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
5faf66a2 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
fsl_qe: Drop common.h In both include/fsl_qe.h and then also remove common.h from the files which had included fsl_qe.h Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
322ca743 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
pg-wcom-ls102xa: Include <config.h> in the board file Given that this file references CFG_* defines, we need to be explicit in our inclusion of config.h, so that these will be defined. Reviewed-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitacienergy.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
5faf66a2 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
fsl_qe: Drop common.h In both include/fsl_qe.h and then also remove common.h from the files which had included fsl_qe.h Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
322ca743 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
pg-wcom-ls102xa: Include <config.h> in the board file Given that this file references CFG_* defines, we need to be explicit in our inclusion of config.h, so that these will be defined. Reviewed-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitacienergy.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
5faf66a2 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
fsl_qe: Drop common.h In both include/fsl_qe.h and then also remove common.h from the files which had included fsl_qe.h Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
322ca743 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
pg-wcom-ls102xa: Include <config.h> in the board file Given that this file references CFG_* defines, we need to be explicit in our inclusion of config.h, so that these will be defined. Reviewed-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitacienergy.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
5faf66a2 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
fsl_qe: Drop common.h In both include/fsl_qe.h and then also remove common.h from the files which had included fsl_qe.h Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
322ca743 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
pg-wcom-ls102xa: Include <config.h> in the board file Given that this file references CFG_* defines, we need to be explicit in our inclusion of config.h, so that these will be defined. Reviewed-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitacienergy.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
5faf66a2 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
fsl_qe: Drop common.h In both include/fsl_qe.h and then also remove common.h from the files which had included fsl_qe.h Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
322ca743 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
pg-wcom-ls102xa: Include <config.h> in the board file Given that this file references CFG_* defines, we need to be explicit in our inclusion of config.h, so that these will be defined. Reviewed-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitacienergy.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
5faf66a2 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
fsl_qe: Drop common.h In both include/fsl_qe.h and then also remove common.h from the files which had included fsl_qe.h Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
322ca743 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
pg-wcom-ls102xa: Include <config.h> in the board file Given that this file references CFG_* defines, we need to be explicit in our inclusion of config.h, so that these will be defined. Reviewed-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitacienergy.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
5faf66a2 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
fsl_qe: Drop common.h In both include/fsl_qe.h and then also remove common.h from the files which had included fsl_qe.h Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
322ca743 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
pg-wcom-ls102xa: Include <config.h> in the board file Given that this file references CFG_* defines, we need to be explicit in our inclusion of config.h, so that these will be defined. Reviewed-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitacienergy.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
5faf66a2 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
fsl_qe: Drop common.h In both include/fsl_qe.h and then also remove common.h from the files which had included fsl_qe.h Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
322ca743 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
pg-wcom-ls102xa: Include <config.h> in the board file Given that this file references CFG_* defines, we need to be explicit in our inclusion of config.h, so that these will be defined. Reviewed-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitacienergy.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
5faf66a2 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
fsl_qe: Drop common.h In both include/fsl_qe.h and then also remove common.h from the files which had included fsl_qe.h Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
322ca743 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
pg-wcom-ls102xa: Include <config.h> in the board file Given that this file references CFG_* defines, we need to be explicit in our inclusion of config.h, so that these will be defined. Reviewed-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitacienergy.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
5faf66a2 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
fsl_qe: Drop common.h In both include/fsl_qe.h and then also remove common.h from the files which had included fsl_qe.h Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
322ca743 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
pg-wcom-ls102xa: Include <config.h> in the board file Given that this file references CFG_* defines, we need to be explicit in our inclusion of config.h, so that these will be defined. Reviewed-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitacienergy.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
5faf66a2 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
fsl_qe: Drop common.h In both include/fsl_qe.h and then also remove common.h from the files which had included fsl_qe.h Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
322ca743 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
pg-wcom-ls102xa: Include <config.h> in the board file Given that this file references CFG_* defines, we need to be explicit in our inclusion of config.h, so that these will be defined. Reviewed-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitacienergy.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
5faf66a2 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
fsl_qe: Drop common.h In both include/fsl_qe.h and then also remove common.h from the files which had included fsl_qe.h Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
322ca743 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
pg-wcom-ls102xa: Include <config.h> in the board file Given that this file references CFG_* defines, we need to be explicit in our inclusion of config.h, so that these will be defined. Reviewed-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitacienergy.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
5faf66a2 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
fsl_qe: Drop common.h In both include/fsl_qe.h and then also remove common.h from the files which had included fsl_qe.h Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
322ca743 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
pg-wcom-ls102xa: Include <config.h> in the board file Given that this file references CFG_* defines, we need to be explicit in our inclusion of config.h, so that these will be defined. Reviewed-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitacienergy.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
5faf66a2 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
fsl_qe: Drop common.h In both include/fsl_qe.h and then also remove common.h from the files which had included fsl_qe.h Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
322ca743 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
pg-wcom-ls102xa: Include <config.h> in the board file Given that this file references CFG_* defines, we need to be explicit in our inclusion of config.h, so that these will be defined. Reviewed-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitacienergy.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
5faf66a2 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
fsl_qe: Drop common.h In both include/fsl_qe.h and then also remove common.h from the files which had included fsl_qe.h Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
322ca743 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
pg-wcom-ls102xa: Include <config.h> in the board file Given that this file references CFG_* defines, we need to be explicit in our inclusion of config.h, so that these will be defined. Reviewed-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitacienergy.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
5faf66a2 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
fsl_qe: Drop common.h In both include/fsl_qe.h and then also remove common.h from the files which had included fsl_qe.h Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
322ca743 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
pg-wcom-ls102xa: Include <config.h> in the board file Given that this file references CFG_* defines, we need to be explicit in our inclusion of config.h, so that these will be defined. Reviewed-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitacienergy.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
5faf66a2 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
fsl_qe: Drop common.h In both include/fsl_qe.h and then also remove common.h from the files which had included fsl_qe.h Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
322ca743 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
pg-wcom-ls102xa: Include <config.h> in the board file Given that this file references CFG_* defines, we need to be explicit in our inclusion of config.h, so that these will be defined. Reviewed-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitacienergy.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
5faf66a2 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
fsl_qe: Drop common.h In both include/fsl_qe.h and then also remove common.h from the files which had included fsl_qe.h Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
322ca743 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
pg-wcom-ls102xa: Include <config.h> in the board file Given that this file references CFG_* defines, we need to be explicit in our inclusion of config.h, so that these will be defined. Reviewed-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitacienergy.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
5faf66a2 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
fsl_qe: Drop common.h In both include/fsl_qe.h and then also remove common.h from the files which had included fsl_qe.h Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
322ca743 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
pg-wcom-ls102xa: Include <config.h> in the board file Given that this file references CFG_* defines, we need to be explicit in our inclusion of config.h, so that these will be defined. Reviewed-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitacienergy.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
5faf66a2 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
fsl_qe: Drop common.h In both include/fsl_qe.h and then also remove common.h from the files which had included fsl_qe.h Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
322ca743 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
pg-wcom-ls102xa: Include <config.h> in the board file Given that this file references CFG_* defines, we need to be explicit in our inclusion of config.h, so that these will be defined. Reviewed-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitacienergy.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
5faf66a2 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
fsl_qe: Drop common.h In both include/fsl_qe.h and then also remove common.h from the files which had included fsl_qe.h Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
322ca743 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
pg-wcom-ls102xa: Include <config.h> in the board file Given that this file references CFG_* defines, we need to be explicit in our inclusion of config.h, so that these will be defined. Reviewed-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitacienergy.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
5faf66a2 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
fsl_qe: Drop common.h In both include/fsl_qe.h and then also remove common.h from the files which had included fsl_qe.h Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
322ca743 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
pg-wcom-ls102xa: Include <config.h> in the board file Given that this file references CFG_* defines, we need to be explicit in our inclusion of config.h, so that these will be defined. Reviewed-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitacienergy.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
5faf66a2 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
fsl_qe: Drop common.h In both include/fsl_qe.h and then also remove common.h from the files which had included fsl_qe.h Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
322ca743 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
pg-wcom-ls102xa: Include <config.h> in the board file Given that this file references CFG_* defines, we need to be explicit in our inclusion of config.h, so that these will be defined. Reviewed-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitacienergy.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
5faf66a2 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
fsl_qe: Drop common.h In both include/fsl_qe.h and then also remove common.h from the files which had included fsl_qe.h Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
322ca743 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
pg-wcom-ls102xa: Include <config.h> in the board file Given that this file references CFG_* defines, we need to be explicit in our inclusion of config.h, so that these will be defined. Reviewed-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitacienergy.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
5faf66a2 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
fsl_qe: Drop common.h In both include/fsl_qe.h and then also remove common.h from the files which had included fsl_qe.h Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
322ca743 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
pg-wcom-ls102xa: Include <config.h> in the board file Given that this file references CFG_* defines, we need to be explicit in our inclusion of config.h, so that these will be defined. Reviewed-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitacienergy.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
5faf66a2 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
fsl_qe: Drop common.h In both include/fsl_qe.h and then also remove common.h from the files which had included fsl_qe.h Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
322ca743 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
pg-wcom-ls102xa: Include <config.h> in the board file Given that this file references CFG_* defines, we need to be explicit in our inclusion of config.h, so that these will be defined. Reviewed-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitacienergy.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
5faf66a2 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
fsl_qe: Drop common.h In both include/fsl_qe.h and then also remove common.h from the files which had included fsl_qe.h Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
322ca743 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
pg-wcom-ls102xa: Include <config.h> in the board file Given that this file references CFG_* defines, we need to be explicit in our inclusion of config.h, so that these will be defined. Reviewed-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitacienergy.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
5faf66a2 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
fsl_qe: Drop common.h In both include/fsl_qe.h and then also remove common.h from the files which had included fsl_qe.h Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
322ca743 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
pg-wcom-ls102xa: Include <config.h> in the board file Given that this file references CFG_* defines, we need to be explicit in our inclusion of config.h, so that these will be defined. Reviewed-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitacienergy.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
5faf66a2 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
fsl_qe: Drop common.h In both include/fsl_qe.h and then also remove common.h from the files which had included fsl_qe.h Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
322ca743 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
pg-wcom-ls102xa: Include <config.h> in the board file Given that this file references CFG_* defines, we need to be explicit in our inclusion of config.h, so that these will be defined. Reviewed-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitacienergy.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
5faf66a2 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
fsl_qe: Drop common.h In both include/fsl_qe.h and then also remove common.h from the files which had included fsl_qe.h Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
322ca743 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
pg-wcom-ls102xa: Include <config.h> in the board file Given that this file references CFG_* defines, we need to be explicit in our inclusion of config.h, so that these will be defined. Reviewed-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitacienergy.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
5faf66a2 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
fsl_qe: Drop common.h In both include/fsl_qe.h and then also remove common.h from the files which had included fsl_qe.h Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
322ca743 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
pg-wcom-ls102xa: Include <config.h> in the board file Given that this file references CFG_* defines, we need to be explicit in our inclusion of config.h, so that these will be defined. Reviewed-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitacienergy.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
5faf66a2 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
fsl_qe: Drop common.h In both include/fsl_qe.h and then also remove common.h from the files which had included fsl_qe.h Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
322ca743 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
pg-wcom-ls102xa: Include <config.h> in the board file Given that this file references CFG_* defines, we need to be explicit in our inclusion of config.h, so that these will be defined. Reviewed-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitacienergy.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
5faf66a2 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
fsl_qe: Drop common.h In both include/fsl_qe.h and then also remove common.h from the files which had included fsl_qe.h Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
322ca743 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
pg-wcom-ls102xa: Include <config.h> in the board file Given that this file references CFG_* defines, we need to be explicit in our inclusion of config.h, so that these will be defined. Reviewed-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitacienergy.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
5faf66a2 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
fsl_qe: Drop common.h In both include/fsl_qe.h and then also remove common.h from the files which had included fsl_qe.h Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
322ca743 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
pg-wcom-ls102xa: Include <config.h> in the board file Given that this file references CFG_* defines, we need to be explicit in our inclusion of config.h, so that these will be defined. Reviewed-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitacienergy.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
5faf66a2 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
fsl_qe: Drop common.h In both include/fsl_qe.h and then also remove common.h from the files which had included fsl_qe.h Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
322ca743 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
pg-wcom-ls102xa: Include <config.h> in the board file Given that this file references CFG_* defines, we need to be explicit in our inclusion of config.h, so that these will be defined. Reviewed-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitacienergy.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
5faf66a2 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
fsl_qe: Drop common.h In both include/fsl_qe.h and then also remove common.h from the files which had included fsl_qe.h Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
322ca743 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
pg-wcom-ls102xa: Include <config.h> in the board file Given that this file references CFG_* defines, we need to be explicit in our inclusion of config.h, so that these will be defined. Reviewed-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitacienergy.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
5faf66a2 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
fsl_qe: Drop common.h In both include/fsl_qe.h and then also remove common.h from the files which had included fsl_qe.h Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
322ca743 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
pg-wcom-ls102xa: Include <config.h> in the board file Given that this file references CFG_* defines, we need to be explicit in our inclusion of config.h, so that these will be defined. Reviewed-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitacienergy.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
5faf66a2 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
fsl_qe: Drop common.h In both include/fsl_qe.h and then also remove common.h from the files which had included fsl_qe.h Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
322ca743 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
pg-wcom-ls102xa: Include <config.h> in the board file Given that this file references CFG_* defines, we need to be explicit in our inclusion of config.h, so that these will be defined. Reviewed-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitacienergy.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
5faf66a2 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
fsl_qe: Drop common.h In both include/fsl_qe.h and then also remove common.h from the files which had included fsl_qe.h Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
322ca743 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
pg-wcom-ls102xa: Include <config.h> in the board file Given that this file references CFG_* defines, we need to be explicit in our inclusion of config.h, so that these will be defined. Reviewed-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitacienergy.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
5faf66a2 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
fsl_qe: Drop common.h In both include/fsl_qe.h and then also remove common.h from the files which had included fsl_qe.h Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
322ca743 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
pg-wcom-ls102xa: Include <config.h> in the board file Given that this file references CFG_* defines, we need to be explicit in our inclusion of config.h, so that these will be defined. Reviewed-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitacienergy.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
5faf66a2 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
fsl_qe: Drop common.h In both include/fsl_qe.h and then also remove common.h from the files which had included fsl_qe.h Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
322ca743 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
pg-wcom-ls102xa: Include <config.h> in the board file Given that this file references CFG_* defines, we need to be explicit in our inclusion of config.h, so that these will be defined. Reviewed-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitacienergy.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
5faf66a2 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
fsl_qe: Drop common.h In both include/fsl_qe.h and then also remove common.h from the files which had included fsl_qe.h Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
322ca743 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
pg-wcom-ls102xa: Include <config.h> in the board file Given that this file references CFG_* defines, we need to be explicit in our inclusion of config.h, so that these will be defined. Reviewed-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitacienergy.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
5faf66a2 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
fsl_qe: Drop common.h In both include/fsl_qe.h and then also remove common.h from the files which had included fsl_qe.h Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
322ca743 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
pg-wcom-ls102xa: Include <config.h> in the board file Given that this file references CFG_* defines, we need to be explicit in our inclusion of config.h, so that these will be defined. Reviewed-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitacienergy.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
5faf66a2 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
fsl_qe: Drop common.h In both include/fsl_qe.h and then also remove common.h from the files which had included fsl_qe.h Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
322ca743 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
pg-wcom-ls102xa: Include <config.h> in the board file Given that this file references CFG_* defines, we need to be explicit in our inclusion of config.h, so that these will be defined. Reviewed-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitacienergy.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
5faf66a2 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
fsl_qe: Drop common.h In both include/fsl_qe.h and then also remove common.h from the files which had included fsl_qe.h Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
322ca743 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
pg-wcom-ls102xa: Include <config.h> in the board file Given that this file references CFG_* defines, we need to be explicit in our inclusion of config.h, so that these will be defined. Reviewed-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitacienergy.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
5faf66a2 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
fsl_qe: Drop common.h In both include/fsl_qe.h and then also remove common.h from the files which had included fsl_qe.h Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
322ca743 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
pg-wcom-ls102xa: Include <config.h> in the board file Given that this file references CFG_* defines, we need to be explicit in our inclusion of config.h, so that these will be defined. Reviewed-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitacienergy.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
5faf66a2 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
fsl_qe: Drop common.h In both include/fsl_qe.h and then also remove common.h from the files which had included fsl_qe.h Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
322ca743 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
pg-wcom-ls102xa: Include <config.h> in the board file Given that this file references CFG_* defines, we need to be explicit in our inclusion of config.h, so that these will be defined. Reviewed-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitacienergy.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
5faf66a2 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
fsl_qe: Drop common.h In both include/fsl_qe.h and then also remove common.h from the files which had included fsl_qe.h Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
322ca743 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
pg-wcom-ls102xa: Include <config.h> in the board file Given that this file references CFG_* defines, we need to be explicit in our inclusion of config.h, so that these will be defined. Reviewed-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitacienergy.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
5faf66a2 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
fsl_qe: Drop common.h In both include/fsl_qe.h and then also remove common.h from the files which had included fsl_qe.h Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
322ca743 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
pg-wcom-ls102xa: Include <config.h> in the board file Given that this file references CFG_* defines, we need to be explicit in our inclusion of config.h, so that these will be defined. Reviewed-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitacienergy.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
5faf66a2 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
fsl_qe: Drop common.h In both include/fsl_qe.h and then also remove common.h from the files which had included fsl_qe.h Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
322ca743 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
pg-wcom-ls102xa: Include <config.h> in the board file Given that this file references CFG_* defines, we need to be explicit in our inclusion of config.h, so that these will be defined. Reviewed-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitacienergy.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
5faf66a2 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
fsl_qe: Drop common.h In both include/fsl_qe.h and then also remove common.h from the files which had included fsl_qe.h Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
322ca743 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
pg-wcom-ls102xa: Include <config.h> in the board file Given that this file references CFG_* defines, we need to be explicit in our inclusion of config.h, so that these will be defined. Reviewed-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitacienergy.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
5faf66a2 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
fsl_qe: Drop common.h In both include/fsl_qe.h and then also remove common.h from the files which had included fsl_qe.h Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
322ca743 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
pg-wcom-ls102xa: Include <config.h> in the board file Given that this file references CFG_* defines, we need to be explicit in our inclusion of config.h, so that these will be defined. Reviewed-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitacienergy.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
5faf66a2 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
fsl_qe: Drop common.h In both include/fsl_qe.h and then also remove common.h from the files which had included fsl_qe.h Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
322ca743 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
pg-wcom-ls102xa: Include <config.h> in the board file Given that this file references CFG_* defines, we need to be explicit in our inclusion of config.h, so that these will be defined. Reviewed-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitacienergy.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
5faf66a2 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
fsl_qe: Drop common.h In both include/fsl_qe.h and then also remove common.h from the files which had included fsl_qe.h Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
322ca743 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
pg-wcom-ls102xa: Include <config.h> in the board file Given that this file references CFG_* defines, we need to be explicit in our inclusion of config.h, so that these will be defined. Reviewed-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitacienergy.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
5faf66a2 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
fsl_qe: Drop common.h In both include/fsl_qe.h and then also remove common.h from the files which had included fsl_qe.h Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
322ca743 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
pg-wcom-ls102xa: Include <config.h> in the board file Given that this file references CFG_* defines, we need to be explicit in our inclusion of config.h, so that these will be defined. Reviewed-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitacienergy.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
5faf66a2 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
fsl_qe: Drop common.h In both include/fsl_qe.h and then also remove common.h from the files which had included fsl_qe.h Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
322ca743 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
pg-wcom-ls102xa: Include <config.h> in the board file Given that this file references CFG_* defines, we need to be explicit in our inclusion of config.h, so that these will be defined. Reviewed-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitacienergy.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
5faf66a2 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
fsl_qe: Drop common.h In both include/fsl_qe.h and then also remove common.h from the files which had included fsl_qe.h Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
322ca743 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
pg-wcom-ls102xa: Include <config.h> in the board file Given that this file references CFG_* defines, we need to be explicit in our inclusion of config.h, so that these will be defined. Reviewed-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitacienergy.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
5faf66a2 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
fsl_qe: Drop common.h In both include/fsl_qe.h and then also remove common.h from the files which had included fsl_qe.h Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
322ca743 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
pg-wcom-ls102xa: Include <config.h> in the board file Given that this file references CFG_* defines, we need to be explicit in our inclusion of config.h, so that these will be defined. Reviewed-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitacienergy.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
5faf66a2 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
fsl_qe: Drop common.h In both include/fsl_qe.h and then also remove common.h from the files which had included fsl_qe.h Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
322ca743 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
pg-wcom-ls102xa: Include <config.h> in the board file Given that this file references CFG_* defines, we need to be explicit in our inclusion of config.h, so that these will be defined. Reviewed-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitacienergy.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
5faf66a2 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
fsl_qe: Drop common.h In both include/fsl_qe.h and then also remove common.h from the files which had included fsl_qe.h Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
322ca743 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
pg-wcom-ls102xa: Include <config.h> in the board file Given that this file references CFG_* defines, we need to be explicit in our inclusion of config.h, so that these will be defined. Reviewed-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitacienergy.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
5faf66a2 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
fsl_qe: Drop common.h In both include/fsl_qe.h and then also remove common.h from the files which had included fsl_qe.h Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
322ca743 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
pg-wcom-ls102xa: Include <config.h> in the board file Given that this file references CFG_* defines, we need to be explicit in our inclusion of config.h, so that these will be defined. Reviewed-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitacienergy.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
5faf66a2 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
fsl_qe: Drop common.h In both include/fsl_qe.h and then also remove common.h from the files which had included fsl_qe.h Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
322ca743 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
pg-wcom-ls102xa: Include <config.h> in the board file Given that this file references CFG_* defines, we need to be explicit in our inclusion of config.h, so that these will be defined. Reviewed-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitacienergy.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
5faf66a2 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
fsl_qe: Drop common.h In both include/fsl_qe.h and then also remove common.h from the files which had included fsl_qe.h Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
322ca743 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
pg-wcom-ls102xa: Include <config.h> in the board file Given that this file references CFG_* defines, we need to be explicit in our inclusion of config.h, so that these will be defined. Reviewed-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitacienergy.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
5faf66a2 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
fsl_qe: Drop common.h In both include/fsl_qe.h and then also remove common.h from the files which had included fsl_qe.h Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
322ca743 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
pg-wcom-ls102xa: Include <config.h> in the board file Given that this file references CFG_* defines, we need to be explicit in our inclusion of config.h, so that these will be defined. Reviewed-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitacienergy.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
5faf66a2 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
fsl_qe: Drop common.h In both include/fsl_qe.h and then also remove common.h from the files which had included fsl_qe.h Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
322ca743 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
pg-wcom-ls102xa: Include <config.h> in the board file Given that this file references CFG_* defines, we need to be explicit in our inclusion of config.h, so that these will be defined. Reviewed-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitacienergy.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
5faf66a2 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
fsl_qe: Drop common.h In both include/fsl_qe.h and then also remove common.h from the files which had included fsl_qe.h Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
322ca743 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
pg-wcom-ls102xa: Include <config.h> in the board file Given that this file references CFG_* defines, we need to be explicit in our inclusion of config.h, so that these will be defined. Reviewed-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitacienergy.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
5faf66a2 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
fsl_qe: Drop common.h In both include/fsl_qe.h and then also remove common.h from the files which had included fsl_qe.h Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
322ca743 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
pg-wcom-ls102xa: Include <config.h> in the board file Given that this file references CFG_* defines, we need to be explicit in our inclusion of config.h, so that these will be defined. Reviewed-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitacienergy.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
5faf66a2 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
fsl_qe: Drop common.h In both include/fsl_qe.h and then also remove common.h from the files which had included fsl_qe.h Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
322ca743 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
pg-wcom-ls102xa: Include <config.h> in the board file Given that this file references CFG_* defines, we need to be explicit in our inclusion of config.h, so that these will be defined. Reviewed-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitacienergy.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
5faf66a2 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
fsl_qe: Drop common.h In both include/fsl_qe.h and then also remove common.h from the files which had included fsl_qe.h Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
322ca743 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
pg-wcom-ls102xa: Include <config.h> in the board file Given that this file references CFG_* defines, we need to be explicit in our inclusion of config.h, so that these will be defined. Reviewed-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitacienergy.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
5faf66a2 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
fsl_qe: Drop common.h In both include/fsl_qe.h and then also remove common.h from the files which had included fsl_qe.h Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
322ca743 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
pg-wcom-ls102xa: Include <config.h> in the board file Given that this file references CFG_* defines, we need to be explicit in our inclusion of config.h, so that these will be defined. Reviewed-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitacienergy.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
5faf66a2 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
fsl_qe: Drop common.h In both include/fsl_qe.h and then also remove common.h from the files which had included fsl_qe.h Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
322ca743 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
pg-wcom-ls102xa: Include <config.h> in the board file Given that this file references CFG_* defines, we need to be explicit in our inclusion of config.h, so that these will be defined. Reviewed-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitacienergy.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
5faf66a2 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
fsl_qe: Drop common.h In both include/fsl_qe.h and then also remove common.h from the files which had included fsl_qe.h Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
322ca743 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
pg-wcom-ls102xa: Include <config.h> in the board file Given that this file references CFG_* defines, we need to be explicit in our inclusion of config.h, so that these will be defined. Reviewed-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitacienergy.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
5faf66a2 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
fsl_qe: Drop common.h In both include/fsl_qe.h and then also remove common.h from the files which had included fsl_qe.h Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
322ca743 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
pg-wcom-ls102xa: Include <config.h> in the board file Given that this file references CFG_* defines, we need to be explicit in our inclusion of config.h, so that these will be defined. Reviewed-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitacienergy.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
5faf66a2 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
fsl_qe: Drop common.h In both include/fsl_qe.h and then also remove common.h from the files which had included fsl_qe.h Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
322ca743 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
pg-wcom-ls102xa: Include <config.h> in the board file Given that this file references CFG_* defines, we need to be explicit in our inclusion of config.h, so that these will be defined. Reviewed-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitacienergy.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
5faf66a2 |
|
31-Oct-2023 |
Tom Rini <trini@konsulko.com> |
fsl_qe: Drop common.h In both include/fsl_qe.h and then also remove common.h from the files which had included fsl_qe.h Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91caa3bb |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Use an event to replace last_stage_init() Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
1744ceb6 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_SELI8 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
735b3d19 |
|
05-Feb-2023 |
Simon Glass <sjg@chromium.org> |
Correct SPL use of TARGET_PG_WCOM_EXPU1 This converts 1 usage of this option to the non-SPL form, since there is no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aa6e94de |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
42fdcebf |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert misc_init_f() to use events This hook can be implmented using events, for the three boards that actually use it. Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we can just use CONFIG_EVENT to control this. Since sandbox always enables CONFIG_EVENT, we can drop the defconfig lines there too. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
987b1828 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use unused scratchrw4 address for post word The SCRATCHRW4 is only used in secure boot scenario that is unsupported by our design, so this address can be stolen for storing POST status. The SCRATCHRW4 is initialized to zero at core rest. Using a DDR address was unfortunate choice, the DDR at boot time has a random contend and it happens that sometimes is matching POST magic number. This behavior can lead to undefined POST behavior and u-boot ending in failbootcmd command. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
d1af7ca8 |
|
16-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: fix device disable configuration This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is not Kconfig but whitelisted. It's fine to be without flag as this is always enabled for abec1020 (pg-wcom-ls102xa.h) Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
84f10528 |
|
10-Dec-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: add support for field fail-safe u-boot update Field fail-safe u-boot update procedure for pg-wcom boards is defined and implemented by patch: 59b3403. This patch invokes the update procedure for pg-wcom-ls102x designs during early misc_init_f execution. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
70003e52 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: dbg phy prst depends on piggy presence The PHY for the debug interface was placed on the board for the pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack including magnetics is connected to the MDI of the PHY. Without a piggy the MDI lines are left floating and it does not make sense to have an active debug PHY. In case of expu1 an active PHY without a piggy even led to increased jitter for syncE. This patch only deactivates the prst line of the debug PHY when a piggy is detected persent. Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
8af140d8 |
|
15-Nov-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> |
km/ls102xa: use qrio selftest_pin for reading selftest QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
02802eb8 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
3aea3ddf |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
km/ls102xa: add support for u-boot POST memory test From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a7fd6fa1 |
|
08-Jun-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
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#
91ee5474 |
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22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
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#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
91ee5474 |
|
22-Feb-2021 |
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> |
board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
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