1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2012-2020  ASPEED Technology Inc.
4 *
5 * Copyright 2016 Google, Inc
6 */
7
8#include <common.h>
9#include <clk.h>
10#include <dm.h>
11#include <errno.h>
12#include <log.h>
13#include <ram.h>
14#include <regmap.h>
15#include <reset.h>
16#include <asm/global_data.h>
17#include <asm/io.h>
18#include <asm/arch/scu_ast2500.h>
19#include <asm/arch/sdram_ast2500.h>
20#include <asm/arch/wdt.h>
21#include <linux/err.h>
22#include <linux/kernel.h>
23#include <dt-bindings/clock/aspeed-clock.h>
24
25/* These configuration parameters are taken from Aspeed SDK */
26#define DDR4_MR46_MODE		0x08000000
27#define DDR4_MR5_MODE		0x400
28#define DDR4_MR13_MODE		0x101
29#define DDR4_MR02_MODE		0x410
30#define DDR4_TRFC		0x45457188
31
32#define PHY_CFG_SIZE		15
33
34static const u32 ddr4_ac_timing[3] = {0x63604e37, 0xe97afa99, 0x00019000};
35static const struct {
36	u32 index[PHY_CFG_SIZE];
37	u32 value[PHY_CFG_SIZE];
38} ddr4_phy_config = {
39	.index = {0, 1, 3, 4, 5, 56, 57, 58, 59, 60, 61, 62, 36, 49, 50},
40	.value = {
41		0x42492aae, 0x09002000, 0x55e00b0b, 0x20000000, 0x24,
42		0x03002900, 0x0e0000a0, 0x000e001c, 0x35b8c106, 0x08080607,
43		0x9b000900, 0x0e400a00, 0x00100008, 0x3c183c3c, 0x00631e0e,
44	},
45};
46
47#define SDRAM_MAX_SIZE		(1024 * 1024 * 1024)
48#define SDRAM_MIN_SIZE		(128 * 1024 * 1024)
49
50DECLARE_GLOBAL_DATA_PTR;
51
52/*
53 * Bandwidth configuration parameters for different SDRAM requests.
54 * These are hardcoded settings taken from Aspeed SDK.
55 */
56static const u32 ddr_max_grant_params[4] = {
57	0x88448844, 0x24422288, 0x22222222, 0x22222222
58};
59
60/*
61 * These registers are not documented by Aspeed at all.
62 * All writes and reads are taken pretty much as is from SDK.
63 */
64struct ast2500_ddr_phy {
65	u32 phy[117];
66};
67
68struct dram_info {
69	struct ram_info info;
70	struct clk ddr_clk;
71	struct ast2500_sdrammc_regs *regs;
72	struct ast2500_scu *scu;
73	struct ast2500_ddr_phy *phy;
74	ulong clock_rate;
75};
76
77static int ast2500_sdrammc_init_phy(struct ast2500_ddr_phy *phy)
78{
79	writel(0, &phy->phy[2]);
80	writel(0, &phy->phy[6]);
81	writel(0, &phy->phy[8]);
82	writel(0, &phy->phy[10]);
83	writel(0, &phy->phy[12]);
84	writel(0, &phy->phy[42]);
85	writel(0, &phy->phy[44]);
86
87	writel(0x86000000, &phy->phy[16]);
88	writel(0x00008600, &phy->phy[17]);
89	writel(0x80000000, &phy->phy[18]);
90	writel(0x80808080, &phy->phy[19]);
91
92	return 0;
93}
94
95static void ast2500_ddr_phy_init_process(struct dram_info *info)
96{
97	struct ast2500_sdrammc_regs *regs = info->regs;
98
99	writel(0, &regs->phy_ctrl[0]);
100	writel(0x4040, &info->phy->phy[51]);
101
102	writel(SDRAM_PHYCTRL0_NRST | SDRAM_PHYCTRL0_INIT, &regs->phy_ctrl[0]);
103	while ((readl(&regs->phy_ctrl[0]) & SDRAM_PHYCTRL0_INIT))
104		;
105	writel(SDRAM_PHYCTRL0_NRST | SDRAM_PHYCTRL0_AUTO_UPDATE,
106	       &regs->phy_ctrl[0]);
107}
108
109static void ast2500_sdrammc_set_vref(struct dram_info *info, u32 vref)
110{
111	writel(0, &info->regs->phy_ctrl[0]);
112	writel((vref << 8) | 0x6, &info->phy->phy[48]);
113	ast2500_ddr_phy_init_process(info);
114}
115
116static int ast2500_ddr_cbr_test(struct dram_info *info)
117{
118	struct ast2500_sdrammc_regs *regs = info->regs;
119	int i;
120	const u32 test_params = SDRAM_TEST_EN
121			| SDRAM_TEST_ERRSTOP
122			| SDRAM_TEST_TWO_MODES;
123	int ret = 0;
124
125	writel((1 << SDRAM_REFRESH_CYCLES_SHIFT) |
126	       (0x5c << SDRAM_REFRESH_PERIOD_SHIFT), &regs->refresh_timing);
127	writel((0xfff << SDRAM_TEST_LEN_SHIFT), &regs->test_addr);
128	writel(0xff00ff00, &regs->test_init_val);
129	writel(SDRAM_TEST_EN | (SDRAM_TEST_MODE_RW << SDRAM_TEST_MODE_SHIFT) |
130	       SDRAM_TEST_ERRSTOP, &regs->ecc_test_ctrl);
131
132	while (!(readl(&regs->ecc_test_ctrl) & SDRAM_TEST_DONE))
133		;
134
135	if (readl(&regs->ecc_test_ctrl) & SDRAM_TEST_FAIL) {
136		ret = -EIO;
137	} else {
138		for (i = 0; i <= SDRAM_TEST_GEN_MODE_MASK; ++i) {
139			writel((i << SDRAM_TEST_GEN_MODE_SHIFT) | test_params,
140			       &regs->ecc_test_ctrl);
141			while (!(readl(&regs->ecc_test_ctrl) & SDRAM_TEST_DONE))
142				;
143			if (readl(&regs->ecc_test_ctrl) & SDRAM_TEST_FAIL) {
144				ret = -EIO;
145				break;
146			}
147		}
148	}
149
150	writel(0, &regs->refresh_timing);
151	writel(0, &regs->ecc_test_ctrl);
152
153	return ret;
154}
155
156static int ast2500_sdrammc_ddr4_calibrate_vref(struct dram_info *info)
157{
158	int i;
159	int vref_min = 0xff;
160	int vref_max = 0;
161	int range_size = 0;
162
163	for (i = 1; i < 0x40; ++i) {
164		int res;
165
166		ast2500_sdrammc_set_vref(info, i);
167		res = ast2500_ddr_cbr_test(info);
168		if (res < 0) {
169			if (range_size > 0)
170				break;
171		} else {
172			++range_size;
173			vref_min = min(vref_min, i);
174			vref_max = max(vref_max, i);
175		}
176	}
177
178	/* Pick average setting */
179	ast2500_sdrammc_set_vref(info, (vref_min + vref_max + 1) / 2);
180
181	return 0;
182}
183
184static size_t ast2500_sdrammc_get_vga_mem_size(struct dram_info *info)
185{
186	size_t vga_mem_size_base = 8 * 1024 * 1024;
187	u32 vga_hwconf = (readl(&info->scu->hwstrap) & SCU_HWSTRAP_VGAMEM_MASK)
188	    >> SCU_HWSTRAP_VGAMEM_SHIFT;
189
190	return vga_mem_size_base << vga_hwconf;
191}
192
193/*
194 * Find out RAM size and save it in dram_info
195 *
196 * The procedure is taken from Aspeed SDK
197 */
198static void ast2500_sdrammc_calc_size(struct dram_info *info)
199{
200	/* The controller supports 128/256/512/1024 MB ram */
201	size_t ram_size = SDRAM_MIN_SIZE;
202	const int write_test_offset = 0x100000;
203	u32 test_pattern = 0xdeadbeef;
204	u32 cap_param = SDRAM_CONF_CAP_1024M;
205	u32 refresh_timing_param = DDR4_TRFC;
206	const u32 write_addr_base = CFG_SYS_SDRAM_BASE + write_test_offset;
207
208	for (ram_size = SDRAM_MAX_SIZE; ram_size > SDRAM_MIN_SIZE;
209	     ram_size >>= 1) {
210		writel(test_pattern, write_addr_base + (ram_size >> 1));
211		test_pattern = (test_pattern >> 4) | (test_pattern << 28);
212	}
213
214	/* One last write to overwrite all wrapped values */
215	writel(test_pattern, write_addr_base);
216
217	/* Reset the pattern and see which value was really written */
218	test_pattern = 0xdeadbeef;
219	for (ram_size = SDRAM_MAX_SIZE; ram_size > SDRAM_MIN_SIZE;
220	     ram_size >>= 1) {
221		if (readl(write_addr_base + (ram_size >> 1)) == test_pattern)
222			break;
223
224		--cap_param;
225		refresh_timing_param >>= 8;
226		test_pattern = (test_pattern >> 4) | (test_pattern << 28);
227	}
228
229	clrsetbits_le32(&info->regs->ac_timing[1],
230			(SDRAM_AC_TRFC_MASK << SDRAM_AC_TRFC_SHIFT),
231			((refresh_timing_param & SDRAM_AC_TRFC_MASK)
232			 << SDRAM_AC_TRFC_SHIFT));
233
234	info->info.base = CFG_SYS_SDRAM_BASE;
235	info->info.size = ram_size - ast2500_sdrammc_get_vga_mem_size(info);
236	clrsetbits_le32(&info->regs->config,
237			(SDRAM_CONF_CAP_MASK << SDRAM_CONF_CAP_SHIFT),
238			((cap_param & SDRAM_CONF_CAP_MASK)
239			 << SDRAM_CONF_CAP_SHIFT));
240}
241
242static int ast2500_sdrammc_init_ddr4(struct dram_info *info)
243{
244	int i;
245	const u32 power_control = SDRAM_PCR_CKE_EN
246	    | (1 << SDRAM_PCR_CKE_DELAY_SHIFT)
247	    | (2 << SDRAM_PCR_TCKE_PW_SHIFT)
248	    | SDRAM_PCR_RESETN_DIS
249	    | SDRAM_PCR_RGAP_CTRL_EN | SDRAM_PCR_ODT_EN | SDRAM_PCR_ODT_EXT_EN;
250	const u32 conf = (SDRAM_CONF_CAP_1024M << SDRAM_CONF_CAP_SHIFT)
251#ifdef CONFIG_ASPEED_DDR4_DUALX8
252	    | SDRAM_CONF_DUALX8
253#endif
254	    | SDRAM_CONF_SCRAMBLE | SDRAM_CONF_SCRAMBLE_PAT2 | SDRAM_CONF_DDR4;
255	int ret;
256
257	writel(conf, &info->regs->config);
258	for (i = 0; i < ARRAY_SIZE(ddr4_ac_timing); ++i)
259		writel(ddr4_ac_timing[i], &info->regs->ac_timing[i]);
260
261	writel(DDR4_MR46_MODE, &info->regs->mr46_mode_setting);
262	writel(DDR4_MR5_MODE, &info->regs->mr5_mode_setting);
263	writel(DDR4_MR02_MODE, &info->regs->mr02_mode_setting);
264	writel(DDR4_MR13_MODE, &info->regs->mr13_mode_setting);
265
266	for (i = 0; i < PHY_CFG_SIZE; ++i) {
267		writel(ddr4_phy_config.value[i],
268		       &info->phy->phy[ddr4_phy_config.index[i]]);
269	}
270
271	writel(power_control, &info->regs->power_control);
272
273	ast2500_ddr_phy_init_process(info);
274
275	ret = ast2500_sdrammc_ddr4_calibrate_vref(info);
276	if (ret < 0) {
277		debug("Vref calibration failed!\n");
278		return ret;
279	}
280
281	writel((1 << SDRAM_REFRESH_CYCLES_SHIFT)
282	       | SDRAM_REFRESH_ZQCS_EN | (0x2f << SDRAM_REFRESH_PERIOD_SHIFT),
283	       &info->regs->refresh_timing);
284
285	setbits_le32(&info->regs->power_control,
286		     SDRAM_PCR_AUTOPWRDN_EN | SDRAM_PCR_ODT_AUTO_ON);
287
288	ast2500_sdrammc_calc_size(info);
289
290	setbits_le32(&info->regs->config, SDRAM_CONF_CACHE_INIT_EN);
291	while (!(readl(&info->regs->config) & SDRAM_CONF_CACHE_INIT_DONE))
292		;
293	setbits_le32(&info->regs->config, SDRAM_CONF_CACHE_EN);
294
295	writel(SDRAM_MISC_DDR4_TREFRESH, &info->regs->misc_control);
296
297	/* Enable all requests except video & display */
298	writel(SDRAM_REQ_USB20_EHCI1
299	       | SDRAM_REQ_USB20_EHCI2
300	       | SDRAM_REQ_CPU
301	       | SDRAM_REQ_AHB2
302	       | SDRAM_REQ_AHB
303	       | SDRAM_REQ_MAC0
304	       | SDRAM_REQ_MAC1
305	       | SDRAM_REQ_PCIE
306	       | SDRAM_REQ_XDMA
307	       | SDRAM_REQ_ENCRYPTION
308	       | SDRAM_REQ_VIDEO_FLAG
309	       | SDRAM_REQ_VIDEO_LOW_PRI_WRITE
310	       | SDRAM_REQ_2D_RW
311	       | SDRAM_REQ_MEMCHECK, &info->regs->req_limit_mask);
312
313	return 0;
314}
315
316static void ast2500_sdrammc_unlock(struct dram_info *info)
317{
318	writel(SDRAM_UNLOCK_KEY, &info->regs->protection_key);
319	while (!readl(&info->regs->protection_key))
320		;
321}
322
323static void ast2500_sdrammc_lock(struct dram_info *info)
324{
325	writel(~SDRAM_UNLOCK_KEY, &info->regs->protection_key);
326	while (readl(&info->regs->protection_key))
327		;
328}
329
330static int ast2500_sdrammc_probe(struct udevice *dev)
331{
332	struct reset_ctl reset_ctl;
333	struct dram_info *priv = (struct dram_info *)dev_get_priv(dev);
334	struct ast2500_sdrammc_regs *regs = priv->regs;
335	int i;
336	int ret = clk_get_by_index(dev, 0, &priv->ddr_clk);
337
338	if (ret) {
339		debug("DDR:No CLK\n");
340		return ret;
341	}
342
343	priv->scu = ast_get_scu();
344	if (IS_ERR(priv->scu)) {
345		debug("%s(): can't get SCU\n", __func__);
346		return PTR_ERR(priv->scu);
347	}
348
349	clk_set_rate(&priv->ddr_clk, priv->clock_rate);
350	ret = reset_get_by_index(dev, 0, &reset_ctl);
351	if (ret) {
352		debug("%s(): Failed to get reset signal\n", __func__);
353		return ret;
354	}
355
356	ret = reset_assert(&reset_ctl);
357	if (ret) {
358		debug("%s(): SDRAM reset failed: %u\n", __func__, ret);
359		return ret;
360	}
361
362	ast2500_sdrammc_unlock(priv);
363
364	writel(SDRAM_PCR_MREQI_DIS | SDRAM_PCR_RESETN_DIS,
365	       &regs->power_control);
366	writel(SDRAM_VIDEO_UNLOCK_KEY, &regs->gm_protection_key);
367
368	/* Mask all requests except CPU and AHB during PHY init */
369	writel(~(SDRAM_REQ_CPU | SDRAM_REQ_AHB), &regs->req_limit_mask);
370
371	for (i = 0; i < ARRAY_SIZE(ddr_max_grant_params); ++i)
372		writel(ddr_max_grant_params[i], &regs->max_grant_len[i]);
373
374	setbits_le32(&regs->intr_ctrl, SDRAM_ICR_RESET_ALL);
375
376	ast2500_sdrammc_init_phy(priv->phy);
377	if (readl(&priv->scu->hwstrap) & SCU_HWSTRAP_DDR4) {
378		ast2500_sdrammc_init_ddr4(priv);
379	} else {
380		debug("Unsupported DRAM3\n");
381		return -EINVAL;
382	}
383
384	clrbits_le32(&regs->intr_ctrl, SDRAM_ICR_RESET_ALL);
385	ast2500_sdrammc_lock(priv);
386
387	return 0;
388}
389
390static int ast2500_sdrammc_of_to_plat(struct udevice *dev)
391{
392	struct dram_info *priv = dev_get_priv(dev);
393	struct regmap *map;
394	int ret;
395
396	ret = regmap_init_mem(dev_ofnode(dev), &map);
397	if (ret)
398		return ret;
399
400	priv->regs = regmap_get_range(map, 0);
401	priv->phy = regmap_get_range(map, 1);
402
403	priv->clock_rate = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
404					  "clock-frequency", 0);
405
406	if (!priv->clock_rate) {
407		debug("DDR Clock Rate not defined\n");
408		return -EINVAL;
409	}
410
411	return 0;
412}
413
414static int ast2500_sdrammc_get_info(struct udevice *dev, struct ram_info *info)
415{
416	struct dram_info *priv = dev_get_priv(dev);
417
418	*info = priv->info;
419
420	return 0;
421}
422
423static struct ram_ops ast2500_sdrammc_ops = {
424	.get_info = ast2500_sdrammc_get_info,
425};
426
427static const struct udevice_id ast2500_sdrammc_ids[] = {
428	{ .compatible = "aspeed,ast2500-sdrammc" },
429	{ }
430};
431
432U_BOOT_DRIVER(sdrammc_ast2500) = {
433	.name = "aspeed_ast2500_sdrammc",
434	.id = UCLASS_RAM,
435	.of_match = ast2500_sdrammc_ids,
436	.ops = &ast2500_sdrammc_ops,
437	.of_to_plat = ast2500_sdrammc_of_to_plat,
438	.probe = ast2500_sdrammc_probe,
439	.priv_auto	= sizeof(struct dram_info),
440};
441