1// SPDX-License-Identifier: GPL-2.0 2/* 3 * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH 4 */ 5 6#include <common.h> 7#include <clk.h> 8#include <dm.h> 9#include <hang.h> 10#include <log.h> 11#include <dt-bindings/memory/rk3368-dmc.h> 12#include <dt-structs.h> 13#include <ram.h> 14#include <regmap.h> 15#include <syscon.h> 16#include <asm/arch-rockchip/clock.h> 17#include <asm/arch-rockchip/cru_rk3368.h> 18#include <asm/arch-rockchip/grf_rk3368.h> 19#include <asm/arch-rockchip/hardware.h> 20#include <asm/arch-rockchip/ddr_rk3368.h> 21#include <asm/arch-rockchip/sdram.h> 22#include <asm/arch-rockchip/sdram_rk3288.h> 23#include <linux/bitops.h> 24#include <linux/delay.h> 25#include <linux/err.h> 26#include <linux/printk.h> 27 28struct dram_info { 29 struct ram_info info; 30 struct clk ddr_clk; 31 struct rk3368_cru *cru; 32 struct rk3368_grf *grf; 33 struct rk3368_ddr_pctl *pctl; 34 struct rk3368_ddrphy *phy; 35 struct rk3368_pmu_grf *pmugrf; 36 struct rk3368_msch *msch; 37}; 38 39struct rk3368_sdram_params { 40#if CONFIG_IS_ENABLED(OF_PLATDATA) 41 struct dtd_rockchip_rk3368_dmc of_plat; 42#endif 43 struct rk3288_sdram_pctl_timing pctl_timing; 44 u32 trefi_mem_ddr3; 45 struct rk3288_sdram_channel chan; 46 struct regmap *map; 47 u32 ddr_freq; 48 u32 memory_schedule; 49 u32 ddr_speed_bin; 50 u32 tfaw_mult; 51}; 52 53/* PTCL bits */ 54enum { 55 /* PCTL_DFISTCFG0 */ 56 DFI_INIT_START = BIT(0), 57 DFI_DATA_BYTE_DISABLE_EN = BIT(2), 58 59 /* PCTL_DFISTCFG1 */ 60 DFI_DRAM_CLK_SR_EN = BIT(0), 61 DFI_DRAM_CLK_DPD_EN = BIT(1), 62 ODT_LEN_BL8_W_SHIFT = 16, 63 64 /* PCTL_DFISTCFG2 */ 65 DFI_PARITY_INTR_EN = BIT(0), 66 DFI_PARITY_EN = BIT(1), 67 68 /* PCTL_DFILPCFG0 */ 69 TLP_RESP_TIME_SHIFT = 16, 70 LP_SR_EN = BIT(8), 71 LP_PD_EN = BIT(0), 72 73 /* PCTL_DFIODTCFG */ 74 RANK0_ODT_WRITE_SEL = BIT(3), 75 RANK1_ODT_WRITE_SEL = BIT(11), 76 77 /* PCTL_SCFG */ 78 HW_LOW_POWER_EN = BIT(0), 79 80 /* PCTL_MCMD */ 81 START_CMD = BIT(31), 82 MCMD_RANK0 = BIT(20), 83 MCMD_RANK1 = BIT(21), 84 DESELECT_CMD = 0, 85 PREA_CMD, 86 REF_CMD, 87 MRS_CMD, 88 ZQCS_CMD, 89 ZQCL_CMD, 90 RSTL_CMD, 91 MRR_CMD = 8, 92 DPDE_CMD, 93 94 /* PCTL_POWCTL */ 95 POWER_UP_START = BIT(0), 96 97 /* PCTL_POWSTAT */ 98 POWER_UP_DONE = BIT(0), 99 100 /* PCTL_SCTL */ 101 INIT_STATE = 0, 102 CFG_STATE, 103 GO_STATE, 104 SLEEP_STATE, 105 WAKEUP_STATE, 106 107 /* PCTL_STAT */ 108 LP_TRIG_SHIFT = 4, 109 LP_TRIG_MASK = 7, 110 PCTL_STAT_MSK = 7, 111 INIT_MEM = 0, 112 CONFIG, 113 CFG_REQ, 114 ACCESS, 115 ACCESS_REQ, 116 LOW_POWER, 117 LOW_POWER_ENTRY_REQ, 118 LOW_POWER_EXIT_REQ, 119 120 /* PCTL_MCFG */ 121 DDR2_DDR3_BL_8 = BIT(0), 122 DDR3_EN = BIT(5), 123 TFAW_TRRD_MULT4 = (0 << 18), 124 TFAW_TRRD_MULT5 = (1 << 18), 125 TFAW_TRRD_MULT6 = (2 << 18), 126}; 127 128#define DDR3_MR0_WR(n) \ 129 ((n <= 8) ? ((n - 4) << 9) : (((n >> 1) & 0x7) << 9)) 130#define DDR3_MR0_CL(n) \ 131 ((((n - 4) & 0x7) << 4) | (((n - 4) & 0x8) >> 2)) 132#define DDR3_MR0_BL8 \ 133 (0 << 0) 134#define DDR3_MR0_DLL_RESET \ 135 (1 << 8) 136#define DDR3_MR1_RTT120OHM \ 137 ((0 << 9) | (1 << 6) | (0 << 2)) 138#define DDR3_MR2_TWL(n) \ 139 (((n - 5) & 0x7) << 3) 140 141 142#ifdef CONFIG_TPL_BUILD 143 144static void ddr_set_noc_spr_err_stall(struct rk3368_grf *grf, bool enable) 145{ 146 if (enable) 147 rk_setreg(&grf->ddrc0_con0, NOC_RSP_ERR_STALL); 148 else 149 rk_clrreg(&grf->ddrc0_con0, NOC_RSP_ERR_STALL); 150} 151 152static void ddr_set_ddr3_mode(struct rk3368_grf *grf, bool ddr3_mode) 153{ 154 if (ddr3_mode) 155 rk_setreg(&grf->ddrc0_con0, MSCH0_MAINDDR3_DDR3); 156 else 157 rk_clrreg(&grf->ddrc0_con0, MSCH0_MAINDDR3_DDR3); 158} 159 160static void ddrphy_config(struct rk3368_ddrphy *phy, 161 u32 tcl, u32 tal, u32 tcwl) 162{ 163 int i; 164 165 /* Set to DDR3 mode */ 166 clrsetbits_le32(&phy->reg[1], 0x3, 0x0); 167 168 /* DDRPHY_REGB: CL, AL */ 169 clrsetbits_le32(&phy->reg[0xb], 0xff, tcl << 4 | tal); 170 /* DDRPHY_REGC: CWL */ 171 clrsetbits_le32(&phy->reg[0xc], 0x0f, tcwl); 172 173 /* Update drive-strength */ 174 writel(0xcc, &phy->reg[0x11]); 175 writel(0xaa, &phy->reg[0x16]); 176 /* 177 * Update NRCOMP/PRCOMP for all 4 channels (for details of all 178 * affected registers refer to the documentation of DDRPHY_REG20 179 * and DDRPHY_REG21 in the RK3368 TRM. 180 */ 181 for (i = 0; i < 4; ++i) { 182 writel(0xcc, &phy->reg[0x20 + i * 0x10]); 183 writel(0x44, &phy->reg[0x21 + i * 0x10]); 184 } 185 186 /* Enable write-leveling calibration bypass */ 187 setbits_le32(&phy->reg[2], BIT(3)); 188} 189 190static void copy_to_reg(u32 *dest, const u32 *src, u32 n) 191{ 192 int i; 193 194 for (i = 0; i < n / sizeof(u32); i++) 195 writel(*src++, dest++); 196} 197 198static void send_command(struct rk3368_ddr_pctl *pctl, u32 rank, u32 cmd) 199{ 200 u32 mcmd = START_CMD | cmd | rank; 201 202 debug("%s: writing %x to MCMD\n", __func__, mcmd); 203 writel(mcmd, &pctl->mcmd); 204 while (readl(&pctl->mcmd) & START_CMD) 205 /* spin */; 206} 207 208static void send_mrs(struct rk3368_ddr_pctl *pctl, 209 u32 rank, u32 mr_num, u32 mr_data) 210{ 211 u32 mcmd = START_CMD | MRS_CMD | rank | (mr_num << 17) | (mr_data << 4); 212 213 debug("%s: writing %x to MCMD\n", __func__, mcmd); 214 writel(mcmd, &pctl->mcmd); 215 while (readl(&pctl->mcmd) & START_CMD) 216 /* spin */; 217} 218 219static int memory_init(struct rk3368_ddr_pctl *pctl, 220 struct rk3368_sdram_params *params) 221{ 222 u32 mr[4]; 223 const ulong timeout_ms = 500; 224 ulong tmp; 225 226 /* 227 * Power up DRAM by DDR_PCTL_POWCTL[0] register of PCTL and 228 * wait power up DRAM finish with DDR_PCTL_POWSTAT[0] register 229 * of PCTL. 230 */ 231 writel(POWER_UP_START, &pctl->powctl); 232 233 tmp = get_timer(0); 234 do { 235 if (get_timer(tmp) > timeout_ms) { 236 pr_err("%s: POWER_UP_START did not complete in %ld ms\n", 237 __func__, timeout_ms); 238 return -ETIME; 239 } 240 } while (!(readl(&pctl->powstat) & POWER_UP_DONE)); 241 242 /* Configure MR0 through MR3 */ 243 mr[0] = DDR3_MR0_WR(params->pctl_timing.twr) | 244 DDR3_MR0_CL(params->pctl_timing.tcl) | 245 DDR3_MR0_DLL_RESET; 246 mr[1] = DDR3_MR1_RTT120OHM; 247 mr[2] = DDR3_MR2_TWL(params->pctl_timing.tcwl); 248 mr[3] = 0; 249 250 /* 251 * Also see RK3368 Technical Reference Manual: 252 * "16.6.2 Initialization (DDR3 Initialization Sequence)" 253 */ 254 send_command(pctl, MCMD_RANK0 | MCMD_RANK1, DESELECT_CMD); 255 udelay(1); 256 send_command(pctl, MCMD_RANK0 | MCMD_RANK1, PREA_CMD); 257 send_mrs(pctl, MCMD_RANK0 | MCMD_RANK1, 2, mr[2]); 258 send_mrs(pctl, MCMD_RANK0 | MCMD_RANK1, 3, mr[3]); 259 send_mrs(pctl, MCMD_RANK0 | MCMD_RANK1, 1, mr[1]); 260 send_mrs(pctl, MCMD_RANK0 | MCMD_RANK1, 0, mr[0]); 261 send_command(pctl, MCMD_RANK0 | MCMD_RANK1, ZQCL_CMD); 262 263 return 0; 264} 265 266static void move_to_config_state(struct rk3368_ddr_pctl *pctl) 267{ 268 /* 269 * Also see RK3368 Technical Reference Manual: 270 * "16.6.1 State transition of PCTL (Moving to Config State)" 271 */ 272 u32 state = readl(&pctl->stat) & PCTL_STAT_MSK; 273 274 switch (state) { 275 case LOW_POWER: 276 writel(WAKEUP_STATE, &pctl->sctl); 277 while ((readl(&pctl->stat) & PCTL_STAT_MSK) != ACCESS) 278 /* spin */; 279 280 /* fall-through */ 281 case ACCESS: 282 case INIT_MEM: 283 writel(CFG_STATE, &pctl->sctl); 284 while ((readl(&pctl->stat) & PCTL_STAT_MSK) != CONFIG) 285 /* spin */; 286 break; 287 288 case CONFIG: 289 return; 290 291 default: 292 break; 293 } 294} 295 296static void move_to_access_state(struct rk3368_ddr_pctl *pctl) 297{ 298 /* 299 * Also see RK3368 Technical Reference Manual: 300 * "16.6.1 State transition of PCTL (Moving to Access State)" 301 */ 302 u32 state = readl(&pctl->stat) & PCTL_STAT_MSK; 303 304 switch (state) { 305 case LOW_POWER: 306 if (((readl(&pctl->stat) >> LP_TRIG_SHIFT) & 307 LP_TRIG_MASK) == 1) 308 return; 309 310 writel(WAKEUP_STATE, &pctl->sctl); 311 while ((readl(&pctl->stat) & PCTL_STAT_MSK) != ACCESS) 312 /* spin */; 313 314 /* fall-through */ 315 case INIT_MEM: 316 writel(CFG_STATE, &pctl->sctl); 317 while ((readl(&pctl->stat) & PCTL_STAT_MSK) != CONFIG) 318 /* spin */; 319 320 /* fall-through */ 321 case CONFIG: 322 writel(GO_STATE, &pctl->sctl); 323 while ((readl(&pctl->stat) & PCTL_STAT_MSK) == CONFIG) 324 /* spin */; 325 break; 326 327 case ACCESS: 328 return; 329 330 default: 331 break; 332 } 333} 334 335static void ddrctl_reset(struct rk3368_cru *cru) 336{ 337 const u32 ctl_reset = BIT(3) | BIT(2); 338 const u32 phy_reset = BIT(1) | BIT(0); 339 340 /* 341 * The PHY reset should be released before the PCTL reset. 342 * 343 * Note that the following sequence (including the number of 344 * us to delay between releasing the PHY and PCTL reset) has 345 * been adapted per feedback received from Rockchips, so do 346 * not try to optimise. 347 */ 348 rk_setreg(&cru->softrst_con[10], ctl_reset | phy_reset); 349 udelay(1); 350 rk_clrreg(&cru->softrst_con[10], phy_reset); 351 udelay(5); 352 rk_clrreg(&cru->softrst_con[10], ctl_reset); 353} 354 355static void ddrphy_reset(struct rk3368_ddrphy *ddrphy) 356{ 357 /* 358 * The analog part of the PHY should be release at least 1000 359 * DRAM cycles before the digital part of the PHY (waiting for 360 * 5us will ensure this for a DRAM clock as low as 200MHz). 361 */ 362 clrbits_le32(&ddrphy->reg[0], BIT(3) | BIT(2)); 363 udelay(1); 364 setbits_le32(&ddrphy->reg[0], BIT(2)); 365 udelay(5); 366 setbits_le32(&ddrphy->reg[0], BIT(3)); 367} 368 369static void ddrphy_config_delays(struct rk3368_ddrphy *ddrphy, u32 freq) 370{ 371 u32 dqs_dll_delay; 372 373 setbits_le32(&ddrphy->reg[0x13], BIT(4)); 374 clrbits_le32(&ddrphy->reg[0x14], BIT(3)); 375 376 setbits_le32(&ddrphy->reg[0x26], BIT(4)); 377 clrbits_le32(&ddrphy->reg[0x27], BIT(3)); 378 379 setbits_le32(&ddrphy->reg[0x36], BIT(4)); 380 clrbits_le32(&ddrphy->reg[0x37], BIT(3)); 381 382 setbits_le32(&ddrphy->reg[0x46], BIT(4)); 383 clrbits_le32(&ddrphy->reg[0x47], BIT(3)); 384 385 setbits_le32(&ddrphy->reg[0x56], BIT(4)); 386 clrbits_le32(&ddrphy->reg[0x57], BIT(3)); 387 388 if (freq <= 400000000) 389 setbits_le32(&ddrphy->reg[0xa4], 0x1f); 390 else 391 clrbits_le32(&ddrphy->reg[0xa4], 0x1f); 392 393 if (freq < 681000000) 394 dqs_dll_delay = 3; /* 67.5 degree delay */ 395 else 396 dqs_dll_delay = 2; /* 45 degree delay */ 397 398 writel(dqs_dll_delay, &ddrphy->reg[0x28]); 399 writel(dqs_dll_delay, &ddrphy->reg[0x38]); 400 writel(dqs_dll_delay, &ddrphy->reg[0x48]); 401 writel(dqs_dll_delay, &ddrphy->reg[0x58]); 402} 403 404static int dfi_cfg(struct rk3368_ddr_pctl *pctl) 405{ 406 const ulong timeout_ms = 200; 407 ulong tmp; 408 409 writel(DFI_DATA_BYTE_DISABLE_EN, &pctl->dfistcfg0); 410 411 writel(DFI_DRAM_CLK_SR_EN | DFI_DRAM_CLK_DPD_EN, 412 &pctl->dfistcfg1); 413 writel(DFI_PARITY_INTR_EN | DFI_PARITY_EN, &pctl->dfistcfg2); 414 writel(7 << TLP_RESP_TIME_SHIFT | LP_SR_EN | LP_PD_EN, 415 &pctl->dfilpcfg0); 416 417 writel(1, &pctl->dfitphyupdtype0); 418 419 writel(0x1f, &pctl->dfitphyrdlat); 420 writel(0, &pctl->dfitphywrdata); 421 writel(0, &pctl->dfiupdcfg); /* phyupd and ctrlupd disabled */ 422 423 setbits_le32(&pctl->dfistcfg0, DFI_INIT_START); 424 425 tmp = get_timer(0); 426 do { 427 if (get_timer(tmp) > timeout_ms) { 428 pr_err("%s: DFI init did not complete within %ld ms\n", 429 __func__, timeout_ms); 430 return -ETIME; 431 } 432 } while ((readl(&pctl->dfiststat0) & 1) == 0); 433 434 return 0; 435} 436 437static inline u32 ps_to_tCK(const u32 ps, const ulong freq) 438{ 439 const ulong MHz = 1000000; 440 return DIV_ROUND_UP(ps * freq, 1000000 * MHz); 441} 442 443static inline u32 ns_to_tCK(const u32 ns, const ulong freq) 444{ 445 return ps_to_tCK(ns * 1000, freq); 446} 447 448static inline u32 tCK_to_ps(const ulong tCK, const ulong freq) 449{ 450 const ulong MHz = 1000000; 451 return DIV_ROUND_UP(tCK * 1000000 * MHz, freq); 452} 453 454static int pctl_calc_timings(struct rk3368_sdram_params *params, 455 ulong freq) 456{ 457 struct rk3288_sdram_pctl_timing *pctl_timing = ¶ms->pctl_timing; 458 const ulong MHz = 1000000; 459 u32 tccd; 460 u32 tfaw_as_ps; 461 462 if (params->ddr_speed_bin != DDR3_1600K) { 463 pr_err("%s: unimplemented DDR3 speed bin %d\n", 464 __func__, params->ddr_speed_bin); 465 return -1; 466 } 467 468 /* PCTL is clocked at 1/2 the DRAM clock; err on the side of caution */ 469 pctl_timing->togcnt1u = DIV_ROUND_UP(freq, 2 * MHz); 470 pctl_timing->togcnt100n = DIV_ROUND_UP(freq / 10, 2 * MHz); 471 472 pctl_timing->tinit = 200; /* 200 usec */ 473 pctl_timing->trsth = 500; /* 500 usec */ 474 pctl_timing->trefi = 78; /* 7.8usec = 78 * 100ns */ 475 params->trefi_mem_ddr3 = ns_to_tCK(pctl_timing->trefi * 100, freq); 476 477 if (freq <= (400 * MHz)) { 478 pctl_timing->tcl = 6; 479 pctl_timing->tcwl = 10; 480 } else if (freq <= (533 * MHz)) { 481 pctl_timing->tcl = 8; 482 pctl_timing->tcwl = 6; 483 } else if (freq <= (666 * MHz)) { 484 pctl_timing->tcl = 10; 485 pctl_timing->tcwl = 7; 486 } else { 487 pctl_timing->tcl = 11; 488 pctl_timing->tcwl = 8; 489 } 490 491 pctl_timing->tmrd = 4; /* 4 tCK (all speed bins) */ 492 pctl_timing->trfc = ns_to_tCK(350, freq); /* tRFC: 350 (max) @ 8GBit */ 493 pctl_timing->trp = max(4u, ps_to_tCK(13750, freq)); 494 /* 495 * JESD-79: 496 * READ to WRITE Command Delay = RL + tCCD / 2 + 2tCK - WL 497 */ 498 tccd = 4; 499 pctl_timing->trtw = pctl_timing->tcl + tccd/2 + 2 - pctl_timing->tcwl; 500 pctl_timing->tal = 0; 501 pctl_timing->tras = ps_to_tCK(35000, freq); 502 pctl_timing->trc = ps_to_tCK(48750, freq); 503 pctl_timing->trcd = ps_to_tCK(13750, freq); 504 pctl_timing->trrd = max(4u, ps_to_tCK(7500, freq)); 505 pctl_timing->trtp = max(4u, ps_to_tCK(7500, freq)); 506 pctl_timing->twr = ps_to_tCK(15000, freq); 507 /* The DDR3 mode-register does only support even values for tWR > 8. */ 508 if (pctl_timing->twr > 8) 509 pctl_timing->twr = (pctl_timing->twr + 1) & ~1; 510 pctl_timing->twtr = max(4u, ps_to_tCK(7500, freq)); 511 pctl_timing->texsr = 512; /* tEXSR(max) is tDLLLK */ 512 pctl_timing->txp = max(3u, ps_to_tCK(6000, freq)); 513 pctl_timing->txpdll = max(10u, ps_to_tCK(24000, freq)); 514 pctl_timing->tzqcs = max(64u, ps_to_tCK(80000, freq)); 515 pctl_timing->tzqcsi = 10000; /* as used by Rockchip */ 516 pctl_timing->tdqs = 1; /* fixed for DDR3 */ 517 pctl_timing->tcksre = max(5u, ps_to_tCK(10000, freq)); 518 pctl_timing->tcksrx = max(5u, ps_to_tCK(10000, freq)); 519 pctl_timing->tcke = max(3u, ps_to_tCK(5000, freq)); 520 pctl_timing->tmod = max(12u, ps_to_tCK(15000, freq)); 521 pctl_timing->trstl = ns_to_tCK(100, freq); 522 pctl_timing->tzqcl = max(256u, ps_to_tCK(320000, freq)); /* tZQoper */ 523 pctl_timing->tmrr = 0; 524 pctl_timing->tckesr = pctl_timing->tcke + 1; /* JESD-79: tCKE + 1tCK */ 525 pctl_timing->tdpd = 0; /* RK3368 TRM: "allowed values for DDR3: 0" */ 526 527 528 /* 529 * The controller can represent tFAW as 4x, 5x or 6x tRRD only. 530 * We want to use the smallest multiplier that satisfies the tFAW 531 * requirements of the given speed-bin. If necessary, we stretch out 532 * tRRD to allow us to operate on a 6x multiplier for tFAW. 533 */ 534 tfaw_as_ps = 40000; /* 40ns: tFAW for DDR3-1600K, 2KB page-size */ 535 if (tCK_to_ps(pctl_timing->trrd * 6, freq) < tfaw_as_ps) { 536 /* If tFAW is > 6 x tRRD, we need to stretch tRRD */ 537 pctl_timing->trrd = ps_to_tCK(DIV_ROUND_UP(40000, 6), freq); 538 params->tfaw_mult = TFAW_TRRD_MULT6; 539 } else if (tCK_to_ps(pctl_timing->trrd * 5, freq) < tfaw_as_ps) { 540 params->tfaw_mult = TFAW_TRRD_MULT6; 541 } else if (tCK_to_ps(pctl_timing->trrd * 4, freq) < tfaw_as_ps) { 542 params->tfaw_mult = TFAW_TRRD_MULT5; 543 } else { 544 params->tfaw_mult = TFAW_TRRD_MULT4; 545 } 546 547 return 0; 548} 549 550static void pctl_cfg(struct rk3368_ddr_pctl *pctl, 551 struct rk3368_sdram_params *params, 552 struct rk3368_grf *grf) 553{ 554 /* Configure PCTL timing registers */ 555 params->pctl_timing.trefi |= BIT(31); /* see PCTL_TREFI */ 556 copy_to_reg(&pctl->togcnt1u, ¶ms->pctl_timing.togcnt1u, 557 sizeof(params->pctl_timing)); 558 writel(params->trefi_mem_ddr3, &pctl->trefi_mem_ddr3); 559 560 /* Set up ODT write selector and ODT write length */ 561 writel((RANK0_ODT_WRITE_SEL | RANK1_ODT_WRITE_SEL), &pctl->dfiodtcfg); 562 writel(7 << ODT_LEN_BL8_W_SHIFT, &pctl->dfiodtcfg1); 563 564 /* Set up the CL/CWL-dependent timings of DFI */ 565 writel((params->pctl_timing.tcl - 1) / 2 - 1, &pctl->dfitrddataen); 566 writel((params->pctl_timing.tcwl - 1) / 2 - 1, &pctl->dfitphywrlat); 567 568 /* DDR3 */ 569 writel(params->tfaw_mult | DDR3_EN | DDR2_DDR3_BL_8, &pctl->mcfg); 570 writel(0x001c0004, &grf->ddrc0_con0); 571 572 setbits_le32(&pctl->scfg, HW_LOW_POWER_EN); 573} 574 575static int ddrphy_data_training(struct rk3368_ddr_pctl *pctl, 576 struct rk3368_ddrphy *ddrphy) 577{ 578 const u32 trefi = readl(&pctl->trefi); 579 const ulong timeout_ms = 500; 580 ulong tmp; 581 582 /* disable auto-refresh */ 583 writel(0 | BIT(31), &pctl->trefi); 584 585 clrsetbits_le32(&ddrphy->reg[2], 0x33, 0x20); 586 clrsetbits_le32(&ddrphy->reg[2], 0x33, 0x21); 587 588 tmp = get_timer(0); 589 do { 590 if (get_timer(tmp) > timeout_ms) { 591 pr_err("%s: did not complete within %ld ms\n", 592 __func__, timeout_ms); 593 return -ETIME; 594 } 595 } while ((readl(&ddrphy->reg[0xff]) & 0xf) != 0xf); 596 597 send_command(pctl, MCMD_RANK0 | MCMD_RANK1, PREA_CMD); 598 clrsetbits_le32(&ddrphy->reg[2], 0x33, 0x20); 599 /* resume auto-refresh */ 600 writel(trefi | BIT(31), &pctl->trefi); 601 602 return 0; 603} 604 605static int sdram_col_row_detect(struct udevice *dev) 606{ 607 struct dram_info *priv = dev_get_priv(dev); 608 struct rk3368_sdram_params *params = dev_get_plat(dev); 609 struct rk3368_ddr_pctl *pctl = priv->pctl; 610 struct rk3368_msch *msch = priv->msch; 611 const u32 test_pattern = 0x5aa5f00f; 612 int row, col; 613 uintptr_t addr; 614 615 move_to_config_state(pctl); 616 writel(6, &msch->ddrconf); 617 move_to_access_state(pctl); 618 619 /* Detect col */ 620 for (col = 11; col >= 9; col--) { 621 writel(0, CFG_SYS_SDRAM_BASE); 622 addr = CFG_SYS_SDRAM_BASE + 623 (1 << (col + params->chan.bw - 1)); 624 writel(test_pattern, addr); 625 if ((readl(addr) == test_pattern) && 626 (readl(CFG_SYS_SDRAM_BASE) == 0)) 627 break; 628 } 629 630 if (col == 8) { 631 pr_err("%s: col detect error\n", __func__); 632 return -EINVAL; 633 } 634 635 move_to_config_state(pctl); 636 writel(15, &msch->ddrconf); 637 move_to_access_state(pctl); 638 639 /* Detect row*/ 640 for (row = 16; row >= 12; row--) { 641 writel(0, CFG_SYS_SDRAM_BASE); 642 addr = CFG_SYS_SDRAM_BASE + (1 << (row + 15 - 1)); 643 writel(test_pattern, addr); 644 if ((readl(addr) == test_pattern) && 645 (readl(CFG_SYS_SDRAM_BASE) == 0)) 646 break; 647 } 648 649 if (row == 11) { 650 pr_err("%s: row detect error\n", __func__); 651 return -EINVAL; 652 } 653 654 /* Record results */ 655 debug("%s: col %d, row %d\n", __func__, col, row); 656 params->chan.col = col; 657 params->chan.cs0_row = row; 658 params->chan.cs1_row = row; 659 params->chan.row_3_4 = 0; 660 661 return 0; 662} 663 664static int msch_niu_config(struct rk3368_msch *msch, 665 struct rk3368_sdram_params *params) 666{ 667 int i; 668 const u8 cols = params->chan.col - ((params->chan.bw == 2) ? 0 : 1); 669 const u8 rows = params->chan.cs0_row; 670 671 /* 672 * The DDR address-translation table always assumes a 32bit 673 * bus and the comparison below takes care of adjusting for 674 * a 16bit bus (i.e. one column-address is consumed). 675 */ 676 const struct { 677 u8 rows; 678 u8 columns; 679 u8 type; 680 } ddrconf_table[] = { 681 /* 682 * C-B-R-D patterns are first. For these we require an 683 * exact match for the columns and rows (as there's 684 * one entry per possible configuration). 685 */ 686 [0] = { .rows = 13, .columns = 10, .type = DMC_MSCH_CBRD }, 687 [1] = { .rows = 14, .columns = 10, .type = DMC_MSCH_CBRD }, 688 [2] = { .rows = 15, .columns = 10, .type = DMC_MSCH_CBRD }, 689 [3] = { .rows = 16, .columns = 10, .type = DMC_MSCH_CBRD }, 690 [4] = { .rows = 14, .columns = 11, .type = DMC_MSCH_CBRD }, 691 [5] = { .rows = 15, .columns = 11, .type = DMC_MSCH_CBRD }, 692 [6] = { .rows = 16, .columns = 11, .type = DMC_MSCH_CBRD }, 693 [7] = { .rows = 13, .columns = 9, .type = DMC_MSCH_CBRD }, 694 [8] = { .rows = 14, .columns = 9, .type = DMC_MSCH_CBRD }, 695 [9] = { .rows = 15, .columns = 9, .type = DMC_MSCH_CBRD }, 696 [10] = { .rows = 16, .columns = 9, .type = DMC_MSCH_CBRD }, 697 /* 698 * 11 through 13 are C-R-B-D patterns. These are 699 * matched for an exact number of columns and to 700 * ensure that the hardware uses at least as many rows 701 * as the pattern requires (i.e. we make sure that 702 * there's no gaps up until we hit the device/chip-select; 703 * however, these patterns can accept up to 16 rows, 704 * as the row-address continues right after the CS 705 * switching) 706 */ 707 [11] = { .rows = 15, .columns = 10, .type = DMC_MSCH_CRBD }, 708 [12] = { .rows = 14, .columns = 11, .type = DMC_MSCH_CRBD }, 709 [13] = { .rows = 13, .columns = 10, .type = DMC_MSCH_CRBD }, 710 /* 711 * 14 and 15 are catch-all variants using a C-B-D-R 712 * scheme (i.e. alternating the chip-select every time 713 * C-B overflows) and stuffing the remaining C-bits 714 * into the top. Matching needs to make sure that the 715 * number of columns is either an exact match (i.e. we 716 * can use less the the maximum number of rows) -or- 717 * that the columns exceed what is given in this table 718 * and the rows are an exact match (in which case the 719 * remaining C-bits will be stuffed onto the top after 720 * the device/chip-select switches). 721 */ 722 [14] = { .rows = 16, .columns = 10, .type = DMC_MSCH_CBDR }, 723 [15] = { .rows = 16, .columns = 9, .type = DMC_MSCH_CBDR }, 724 }; 725 726 /* 727 * For C-B-R-D, we need an exact match (i.e. both for the number of 728 * columns and rows), while for C-B-D-R, only the the number of 729 * columns needs to match. 730 */ 731 for (i = 0; i < ARRAY_SIZE(ddrconf_table); i++) { 732 bool match = false; 733 734 /* If this entry if for a different matcher, then skip it */ 735 if (ddrconf_table[i].type != params->memory_schedule) 736 continue; 737 738 /* 739 * Match according to the rules (exact/inexact/at-least) 740 * documented in the ddrconf_table above. 741 */ 742 switch (params->memory_schedule) { 743 case DMC_MSCH_CBRD: 744 match = (ddrconf_table[i].columns == cols) && 745 (ddrconf_table[i].rows == rows); 746 break; 747 748 case DMC_MSCH_CRBD: 749 match = (ddrconf_table[i].columns == cols) && 750 (ddrconf_table[i].rows <= rows); 751 break; 752 753 case DMC_MSCH_CBDR: 754 match = (ddrconf_table[i].columns == cols) || 755 ((ddrconf_table[i].columns <= cols) && 756 (ddrconf_table[i].rows == rows)); 757 break; 758 759 default: 760 break; 761 } 762 763 if (match) { 764 debug("%s: setting ddrconf 0x%x\n", __func__, i); 765 writel(i, &msch->ddrconf); 766 return 0; 767 } 768 } 769 770 pr_err("%s: ddrconf (NIU config) not found\n", __func__); 771 return -EINVAL; 772} 773 774static void dram_all_config(struct udevice *dev) 775{ 776 struct dram_info *priv = dev_get_priv(dev); 777 struct rk3368_pmu_grf *pmugrf = priv->pmugrf; 778 struct rk3368_sdram_params *params = dev_get_plat(dev); 779 const struct rk3288_sdram_channel *info = ¶ms->chan; 780 u32 sys_reg = 0; 781 const int chan = 0; 782 783 sys_reg |= DDR3 << SYS_REG_DDRTYPE_SHIFT; 784 sys_reg |= 0 << SYS_REG_NUM_CH_SHIFT; 785 786 sys_reg |= info->row_3_4 << SYS_REG_ROW_3_4_SHIFT(chan); 787 sys_reg |= 1 << SYS_REG_CHINFO_SHIFT(chan); 788 sys_reg |= (info->rank - 1) << SYS_REG_RANK_SHIFT(chan); 789 sys_reg |= (info->col - 9) << SYS_REG_COL_SHIFT(chan); 790 sys_reg |= info->bk == 3 ? 0 : 1 << SYS_REG_BK_SHIFT(chan); 791 sys_reg |= (info->cs0_row - 13) << SYS_REG_CS0_ROW_SHIFT(chan); 792 sys_reg |= (info->cs1_row - 13) << SYS_REG_CS1_ROW_SHIFT(chan); 793 sys_reg |= (2 >> info->bw) << SYS_REG_BW_SHIFT(chan); 794 sys_reg |= (2 >> info->dbw) << SYS_REG_DBW_SHIFT(chan); 795 796 writel(sys_reg, &pmugrf->os_reg[2]); 797} 798 799static int setup_sdram(struct udevice *dev) 800{ 801 struct dram_info *priv = dev_get_priv(dev); 802 struct rk3368_sdram_params *params = dev_get_plat(dev); 803 804 struct rk3368_ddr_pctl *pctl = priv->pctl; 805 struct rk3368_ddrphy *ddrphy = priv->phy; 806 struct rk3368_cru *cru = priv->cru; 807 struct rk3368_grf *grf = priv->grf; 808 struct rk3368_msch *msch = priv->msch; 809 810 int ret; 811 812 /* The input clock (i.e. DPLL) needs to be 2x the DRAM frequency */ 813 ret = clk_set_rate(&priv->ddr_clk, 2 * params->ddr_freq); 814 if (ret < 0) { 815 debug("%s: could not set DDR clock: %d\n", __func__, ret); 816 return ret; 817 } 818 819 /* Update the read-latency for the RK3368 */ 820 writel(0x32, &msch->readlatency); 821 822 /* Initialise the DDR PCTL and DDR PHY */ 823 ddrctl_reset(cru); 824 ddrphy_reset(ddrphy); 825 ddrphy_config_delays(ddrphy, params->ddr_freq); 826 dfi_cfg(pctl); 827 /* Configure relative system information of grf_ddrc0_con0 register */ 828 ddr_set_ddr3_mode(grf, true); 829 ddr_set_noc_spr_err_stall(grf, true); 830 /* Calculate timings */ 831 pctl_calc_timings(params, params->ddr_freq); 832 /* Initialise the device timings in protocol controller */ 833 pctl_cfg(pctl, params, grf); 834 /* Configure AL, CL ... information of PHY registers */ 835 ddrphy_config(ddrphy, 836 params->pctl_timing.tcl, 837 params->pctl_timing.tal, 838 params->pctl_timing.tcwl); 839 840 /* Initialize DRAM and configure with mode-register values */ 841 ret = memory_init(pctl, params); 842 if (ret) 843 goto error; 844 845 move_to_config_state(pctl); 846 /* Perform data-training */ 847 ddrphy_data_training(pctl, ddrphy); 848 move_to_access_state(pctl); 849 850 /* TODO(prt): could detect rank in training... */ 851#ifdef CONFIG_TARGET_EVB_PX5 852 params->chan.rank = 1; 853#else 854 params->chan.rank = 2; 855#endif 856 /* TODO(prt): bus width is not auto-detected (yet)... */ 857 params->chan.bw = 2; /* 32bit wide bus */ 858 params->chan.dbw = params->chan.dbw; /* 32bit wide bus */ 859 860 /* DDR3 is always 8 bank */ 861 params->chan.bk = 3; 862 /* Detect col and row number */ 863 ret = sdram_col_row_detect(dev); 864 if (ret) 865 goto error; 866 867 /* Configure NIU DDR configuration */ 868 ret = msch_niu_config(msch, params); 869 if (ret) 870 goto error; 871 872 /* set up OS_REG to communicate w/ next stage and OS */ 873 dram_all_config(dev); 874 875 return 0; 876 877error: 878 printf("DRAM init failed!\n"); 879 hang(); 880} 881#endif 882 883static int rk3368_dmc_of_to_plat(struct udevice *dev) 884{ 885 int ret = 0; 886 887 if (CONFIG_IS_ENABLED(OF_REAL)) { 888 struct rk3368_sdram_params *plat = dev_get_plat(dev); 889 890 ret = regmap_init_mem(dev_ofnode(dev), &plat->map); 891 if (ret) 892 return ret; 893 } 894 895 return ret; 896} 897 898#if CONFIG_IS_ENABLED(OF_PLATDATA) 899static int conv_of_plat(struct udevice *dev) 900{ 901 struct rk3368_sdram_params *plat = dev_get_plat(dev); 902 struct dtd_rockchip_rk3368_dmc *of_plat = &plat->of_plat; 903 904 plat->ddr_freq = of_plat->rockchip_ddr_frequency; 905 plat->ddr_speed_bin = of_plat->rockchip_ddr_speed_bin; 906 plat->memory_schedule = of_plat->rockchip_memory_schedule; 907 908 return 0; 909} 910#endif 911 912static int rk3368_dmc_probe(struct udevice *dev) 913{ 914#ifdef CONFIG_TPL_BUILD 915 struct rk3368_sdram_params *plat = dev_get_plat(dev); 916 struct rk3368_ddr_pctl *pctl; 917 struct rk3368_ddrphy *ddrphy; 918 struct rk3368_cru *cru; 919 struct rk3368_grf *grf; 920 struct rk3368_msch *msch; 921 int ret; 922 struct udevice *dev_clk; 923#endif 924 struct dram_info *priv = dev_get_priv(dev); 925 926#if CONFIG_IS_ENABLED(OF_PLATDATA) 927 ret = conv_of_plat(dev); 928 if (ret) 929 return ret; 930#endif 931 932 priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF); 933 debug("%s: pmugrf=%p\n", __func__, priv->pmugrf); 934 935#ifdef CONFIG_TPL_BUILD 936 pctl = (struct rk3368_ddr_pctl *)plat->of_plat.reg[0]; 937 ddrphy = (struct rk3368_ddrphy *)plat->of_plat.reg[2]; 938 msch = syscon_get_first_range(ROCKCHIP_SYSCON_MSCH); 939 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 940 941 priv->pctl = pctl; 942 priv->phy = ddrphy; 943 priv->msch = msch; 944 priv->grf = grf; 945 946 ret = rockchip_get_clk(&dev_clk); 947 if (ret) 948 return ret; 949 priv->ddr_clk.id = CLK_DDR; 950 ret = clk_request(dev_clk, &priv->ddr_clk); 951 if (ret) 952 return ret; 953 954 cru = rockchip_get_cru(); 955 priv->cru = cru; 956 if (IS_ERR(priv->cru)) 957 return PTR_ERR(priv->cru); 958 959 ret = setup_sdram(dev); 960 if (ret) 961 return ret; 962#endif 963 964 priv->info.base = 0; 965 priv->info.size = 966 rockchip_sdram_size((phys_addr_t)&priv->pmugrf->os_reg[2]); 967 968 /* 969 * we use the 0x00000000~0xfdffffff space since 0xff000000~0xffffffff 970 * is SoC register space (i.e. reserved), and 0xfe000000~0xfeffffff is 971 * inaccessible for some IP controller. 972 */ 973 priv->info.size = min(priv->info.size, (size_t)0xfe000000); 974 975 return 0; 976} 977 978static int rk3368_dmc_get_info(struct udevice *dev, struct ram_info *info) 979{ 980 struct dram_info *priv = dev_get_priv(dev); 981 982 *info = priv->info; 983 return 0; 984} 985 986static struct ram_ops rk3368_dmc_ops = { 987 .get_info = rk3368_dmc_get_info, 988}; 989 990 991static const struct udevice_id rk3368_dmc_ids[] = { 992 { .compatible = "rockchip,rk3368-dmc" }, 993 { } 994}; 995 996U_BOOT_DRIVER(rockchip_rk3368_dmc) = { 997 .name = "rockchip_rk3368_dmc", 998 .id = UCLASS_RAM, 999 .of_match = rk3368_dmc_ids, 1000 .ops = &rk3368_dmc_ops, 1001 .probe = rk3368_dmc_probe, 1002 .priv_auto = sizeof(struct dram_info), 1003 .of_to_plat = rk3368_dmc_of_to_plat, 1004 .probe = rk3368_dmc_probe, 1005 .priv_auto = sizeof(struct dram_info), 1006 .plat_auto = sizeof(struct rk3368_sdram_params), 1007}; 1008