1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2010-2017 CS Systemes d'Information
4 * Florent Trinh Thai <florent.trinh-thai@c-s.fr>
5 * Christophe Leroy <christophe.leroy@c-s.fr>
6 *
7 * Board specific routines for the MCR3000 board
8 */
9
10#include <env.h>
11#include <hwconfig.h>
12#include <init.h>
13#include <mpc8xx.h>
14#include <fdt_support.h>
15#include <serial.h>
16#include <spi.h>
17#include <asm/global_data.h>
18#include <asm/io.h>
19#include <dm/uclass.h>
20#include <wdt.h>
21#include <linux/delay.h>
22
23#include "fpga_code.h"
24
25DECLARE_GLOBAL_DATA_PTR;
26
27#define SDRAM_MAX_SIZE			(32 * 1024 * 1024)
28
29static const uint cs1_dram_table_66[] = {
30	/* DRAM - single read. (offset 0 in upm RAM) */
31	0x0F3DFC04, 0x0FEFBC04, 0x00BE7804, 0x0FFDF400,
32	0x1FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
33
34	/* DRAM - burst read. (offset 8 in upm RAM) */
35	0x0F3DFC04, 0x0FEFBC04, 0x00BF7C04, 0x00FFFC00,
36	0x00FFFC00, 0x00FEF800, 0x0FFDF400, 0x1FFFFC05,
37	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
38	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
39
40	/* DRAM - single write. (offset 18 in upm RAM) */
41	0x0F3DFC04, 0x0FEFB800, 0x00BF7404, 0x0FFEF804,
42	0x0FFDF404, 0x1FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF,
43
44	/* DRAM - burst write. (offset 20 in upm RAM) */
45	0x0F3DFC04, 0x0FEFB800, 0x00BF7400, 0x00FFFC00,
46	0x00FFFC00, 0x00FFFC04,	0x0FFEF804, 0x0FFDF404,
47	0x1FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
48	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
49
50	/* refresh  (offset 30 in upm RAM) */
51	0x0FFDF404, 0x0FFEBC04, 0x0FFD7C84, 0x0FFFFC04,
52	0x0FFFFC04, 0x0FFFFC04, 0x1FFFFC85, 0xFFFFFFFF,
53
54	/* init */
55	0x0FEEB874, 0x0FBD7474, 0x1FFFFC45, 0xFFFFFFFF,
56
57	/* exception. (offset 3c in upm RAM) */
58	0xFFFFFC05, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
59};
60
61int ft_board_setup(void *blob, struct bd_info *bd)
62{
63	ft_cpu_setup(blob, bd);
64
65	/* BRG */
66	do_fixup_by_path_u32(blob, "/soc/cpm", "brg-frequency",
67			     bd->bi_busfreq, 1);
68
69	/* MAC addr */
70	fdt_fixup_ethernet(blob);
71
72	/* Bus Frequency for CPM */
73	do_fixup_by_path_u32(blob, "/soc", "bus-frequency", bd->bi_busfreq, 1);
74
75	return 0;
76}
77
78int checkboard(void)
79{
80	serial_puts("BOARD: MCR3000 CSSI\n");
81
82	return 0;
83}
84
85int dram_init(void)
86{
87	immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
88	memctl8xx_t __iomem *memctl = &immap->im_memctl;
89
90	printf("UPMA init for SDRAM (CAS latency 2), ");
91	printf("init address 0x%08x, size ", (int)dram_init);
92	/* Configure UPMA for cs1 */
93	upmconfig(UPMA, (uint *)cs1_dram_table_66,
94		  sizeof(cs1_dram_table_66) / sizeof(uint));
95	udelay(10);
96	out_be16(&memctl->memc_mptpr, 0x0200);
97	out_be32(&memctl->memc_mamr, 0x14904000);
98	udelay(10);
99	out_be32(&memctl->memc_or1, CONFIG_SYS_OR1_PRELIM);
100	out_be32(&memctl->memc_br1, CONFIG_SYS_BR1_PRELIM);
101	udelay(10);
102	out_be32(&memctl->memc_mcr, 0x80002830);
103	out_be32(&memctl->memc_mar, 0x00000088);
104	out_be32(&memctl->memc_mcr, 0x80002038);
105	udelay(200);
106
107	gd->ram_size = get_ram_size((long *)CFG_SYS_SDRAM_BASE,
108				    SDRAM_MAX_SIZE);
109
110	return 0;
111}
112
113static int load_fpga(void)
114{
115	immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
116	struct udevice *master;
117	struct spi_slave *slave;
118	int ret;
119
120	ret = uclass_get_device(UCLASS_SPI, 0, &master);
121	if (ret)
122		return ret;
123
124	ret = _spi_get_bus_and_cs(0, 1, 10000000, 0, "spi_generic_drv",
125				  "generic_0:0", &master, &slave);
126	if (ret)
127		return ret;
128
129	ret = spi_claim_bus(slave);
130
131	printf("FPGA Init ... ");
132
133	clrbits_be32(&immr->im_cpm.cp_pbdat, 0x20000);
134	while ((in_be32(&immr->im_cpm.cp_pbdat) & 0x8000))
135		;
136	setbits_be32(&immr->im_cpm.cp_pbdat, 0x20000);
137	while (!(in_be32(&immr->im_cpm.cp_pbdat) & 0x8000))
138		;
139
140	printf("Loading ... ");
141
142	ret = spi_xfer(slave, sizeof(fpga_code) * BITS_PER_BYTE, fpga_code, NULL, 0);
143
144	spi_release_bus(slave);
145
146	if ((in_be32(&immr->im_cpm.cp_pbdat) & 0x4000)) {
147		printf("Done\n");
148	} else {
149		printf("FAILED\n");
150		ret = -EINVAL;
151	}
152
153	return ret;
154}
155
156int misc_init_r(void)
157{
158	immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
159	iop8xx_t __iomem *iop = &immr->im_ioport;
160
161	/* Set port C13 as GPIO (BTN_ACQ_AL) */
162	clrbits_be16(&iop->iop_pcpar, 0x4);
163	clrbits_be16(&iop->iop_pcdir, 0x4);
164
165	/* Activate SPI */
166	clrsetbits_be32(&immr->im_cpm.cp_pbpar, 0x1, 0xe);
167	setbits_be32(&immr->im_cpm.cp_pbdir, 0xf);
168	clrbits_be32(&immr->im_cpm.cp_pbdat, 0x1);
169
170	if (!load_fpga()) {
171		u8 addr = in_be16((void *)0x1400009c);
172
173		printf("Board address: 0x%2.2x (System %d Rack %d Slot %d)\n",
174		       addr, addr >> 7, (addr >> 4) & 7, addr & 15);
175	}
176
177	/* if BTN_ACQ_AL is pressed then bootdelay is changed to 60 second */
178	if ((in_be16(&iop->iop_pcdat) & 0x0004) == 0)
179		env_set("bootdelay", "60");
180
181	return 0;
182}
183
184int board_early_init_f(void)
185{
186	immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
187
188	/*
189	 * Erase FPGA(s) for reboot
190	 */
191	clrbits_be32(&immr->im_cpm.cp_pbdat, 0x00020000); /* PROGFPGA down */
192	setbits_be32(&immr->im_cpm.cp_pbdir, 0x00020000); /* PROGFPGA output */
193	udelay(1);				/* Wait more than 300ns */
194	setbits_be32(&immr->im_cpm.cp_pbdat, 0x00020000); /* PROGFPGA up */
195
196	return 0;
197}
198