1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. 4 * Copyright (C) 2016 Grinn 5 */ 6 7#include <init.h> 8#include <asm/arch/clock.h> 9#include <asm/arch/iomux.h> 10#include <asm/arch/imx-regs.h> 11#include <asm/arch/crm_regs.h> 12#include <asm/arch/mx6ul_pins.h> 13#include <asm/arch/mx6-pins.h> 14#include <asm/arch/sys_proto.h> 15#include <asm/global_data.h> 16#include <asm/gpio.h> 17#include <asm/mach-imx/iomux-v3.h> 18#include <asm/mach-imx/boot_mode.h> 19#include <asm/io.h> 20#include <common.h> 21#include <fsl_esdhc_imx.h> 22#include <linux/delay.h> 23#include <linux/sizes.h> 24#include <mmc.h> 25 26DECLARE_GLOBAL_DATA_PTR; 27 28#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 29 PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \ 30 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) 31 32int dram_init(void) 33{ 34 gd->ram_size = imx_ddr_size(); 35 36 return 0; 37} 38 39static iomux_v3_cfg_t const emmc_pads[] = { 40 MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 41 MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 42 MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 43 MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 44 MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 45 MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 46 MX6_PAD_NAND_DATA04__USDHC2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 47 MX6_PAD_NAND_DATA05__USDHC2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 48 MX6_PAD_NAND_DATA06__USDHC2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 49 MX6_PAD_NAND_DATA07__USDHC2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 50 51 /* RST_B */ 52 MX6_PAD_NAND_ALE__GPIO4_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL), 53}; 54 55#ifdef CONFIG_FSL_ESDHC_IMX 56static struct fsl_esdhc_cfg emmc_cfg = {USDHC2_BASE_ADDR, 0, 8}; 57 58#define EMMC_PWR_GPIO IMX_GPIO_NR(4, 10) 59 60int litesom_mmc_init(struct bd_info *bis) 61{ 62 int ret; 63 64 /* eMMC */ 65 imx_iomux_v3_setup_multiple_pads(emmc_pads, ARRAY_SIZE(emmc_pads)); 66 gpio_direction_output(EMMC_PWR_GPIO, 0); 67 udelay(500); 68 gpio_direction_output(EMMC_PWR_GPIO, 1); 69 emmc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); 70 71 ret = fsl_esdhc_initialize(bis, &emmc_cfg); 72 if (ret) { 73 printf("Warning: failed to initialize mmc dev 1 (eMMC)\n"); 74 return ret; 75 } 76 77 return 0; 78} 79#endif 80 81#ifdef CONFIG_SPL_BUILD 82#include <linux/libfdt.h> 83#include <spl.h> 84#include <asm/arch/mx6-ddr.h> 85 86 87static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = { 88 .grp_addds = 0x00000030, 89 .grp_ddrmode_ctl = 0x00020000, 90 .grp_b0ds = 0x00000030, 91 .grp_ctlds = 0x00000030, 92 .grp_b1ds = 0x00000030, 93 .grp_ddrpke = 0x00000000, 94 .grp_ddrmode = 0x00020000, 95 .grp_ddr_type = 0x000c0000, 96}; 97 98static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = { 99 .dram_dqm0 = 0x00000030, 100 .dram_dqm1 = 0x00000030, 101 .dram_ras = 0x00000030, 102 .dram_cas = 0x00000030, 103 .dram_odt0 = 0x00000030, 104 .dram_odt1 = 0x00000030, 105 .dram_sdba2 = 0x00000000, 106 .dram_sdclk_0 = 0x00000030, 107 .dram_sdqs0 = 0x00000030, 108 .dram_sdqs1 = 0x00000030, 109 .dram_reset = 0x00000030, 110}; 111 112static struct mx6_mmdc_calibration mx6_mmcd_calib = { 113 .p0_mpwldectrl0 = 0x00000000, 114 .p0_mpdgctrl0 = 0x41570155, 115 .p0_mprddlctl = 0x4040474A, 116 .p0_mpwrdlctl = 0x40405550, 117}; 118 119struct mx6_ddr_sysinfo ddr_sysinfo = { 120 .dsize = 0, 121 .cs_density = 20, 122 .ncs = 1, 123 .cs1_mirror = 0, 124 .rtt_wr = 2, 125 .rtt_nom = 1, /* RTT_Nom = RZQ/2 */ 126 .walat = 0, /* Write additional latency */ 127 .ralat = 5, /* Read additional latency */ 128 .mif3_mode = 3, /* Command prediction working mode */ 129 .bi_on = 1, /* Bank interleaving enabled */ 130 .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ 131 .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ 132 .ddr_type = DDR_TYPE_DDR3, 133 .refsel = 0, /* Refresh cycles at 64KHz */ 134 .refr = 1, /* 2 refresh commands per refresh cycle */ 135}; 136 137static struct mx6_ddr3_cfg mem_ddr = { 138 .mem_speed = 800, 139 .density = 4, 140 .width = 16, 141 .banks = 8, 142 .rowaddr = 15, 143 .coladdr = 10, 144 .pagesz = 2, 145 .trcd = 1375, 146 .trcmin = 4875, 147 .trasmin = 3500, 148}; 149 150static void ccgr_init(void) 151{ 152 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 153 154 writel(0xFFFFFFFF, &ccm->CCGR0); 155 writel(0xFFFFFFFF, &ccm->CCGR1); 156 writel(0xFFFFFFFF, &ccm->CCGR2); 157 writel(0xFFFFFFFF, &ccm->CCGR3); 158 writel(0xFFFFFFFF, &ccm->CCGR4); 159 writel(0xFFFFFFFF, &ccm->CCGR5); 160 writel(0xFFFFFFFF, &ccm->CCGR6); 161 writel(0xFFFFFFFF, &ccm->CCGR7); 162} 163 164static void spl_dram_init(void) 165{ 166 unsigned long ram_size; 167 168 mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs); 169 mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr); 170 171 /* 172 * Get actual RAM size, so we can adjust DDR row size for <512M 173 * memories 174 */ 175 ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, SZ_512M); 176 if (ram_size < SZ_512M) { 177 mem_ddr.rowaddr = 14; 178 mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr); 179 } 180} 181 182void litesom_init_f(void) 183{ 184 ccgr_init(); 185 186 /* setup AIPS and disable watchdog */ 187 arch_cpu_init(); 188 189#ifdef CONFIG_BOARD_EARLY_INIT_F 190 board_early_init_f(); 191#endif 192 193 /* setup GP timer */ 194 timer_init(); 195 196 /* UART clocks enabled and gd valid - init serial console */ 197 preloader_console_init(); 198 199 /* DDR initialization */ 200 spl_dram_init(); 201} 202#endif 203