1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright 2014 Freescale Semiconductor, Inc. 4 */ 5 6#include <common.h> 7#include <fsl_ddr_sdram.h> 8#include <fsl_ddr_dimm_params.h> 9#include <init.h> 10#include <log.h> 11#include <asm/global_data.h> 12#include <asm/io.h> 13#include <asm/arch/clock.h> 14#include <linux/delay.h> 15#include "ddr.h" 16 17DECLARE_GLOBAL_DATA_PTR; 18 19void fsl_ddr_board_options(memctl_options_t *popts, 20 dimm_params_t *pdimm, 21 unsigned int ctrl_num) 22{ 23 const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; 24 ulong ddr_freq; 25 26 if (ctrl_num > 3) { 27 printf("Not supported controller number %d\n", ctrl_num); 28 return; 29 } 30 if (!pdimm->n_ranks) 31 return; 32 33 pbsp = udimms[0]; 34 35 /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr 36 * freqency and n_banks specified in board_specific_parameters table. 37 */ 38 ddr_freq = get_ddr_freq(0) / 1000000; 39 while (pbsp->datarate_mhz_high) { 40 if (pbsp->n_ranks == pdimm->n_ranks) { 41 if (ddr_freq <= pbsp->datarate_mhz_high) { 42 popts->clk_adjust = pbsp->clk_adjust; 43 popts->wrlvl_start = pbsp->wrlvl_start; 44 popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; 45 popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; 46 popts->cpo_override = pbsp->cpo_override; 47 popts->write_data_delay = 48 pbsp->write_data_delay; 49 goto found; 50 } 51 pbsp_highest = pbsp; 52 } 53 pbsp++; 54 } 55 56 if (pbsp_highest) { 57 printf("Error: board specific timing not found for %lu MT/s\n", 58 ddr_freq); 59 printf("Trying to use the highest speed (%u) parameters\n", 60 pbsp_highest->datarate_mhz_high); 61 popts->clk_adjust = pbsp_highest->clk_adjust; 62 popts->wrlvl_start = pbsp_highest->wrlvl_start; 63 popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; 64 popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; 65 } else { 66 panic("DIMM is not supported by this board"); 67 } 68found: 69 debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n", 70 pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb); 71 72 /* force DDR bus width to 32 bits */ 73 popts->data_bus_width = 1; 74 popts->otf_burst_chop_en = 0; 75 popts->burst_length = DDR_BL8; 76 77 /* 78 * Factors to consider for half-strength driver enable: 79 * - number of DIMMs installed 80 */ 81 popts->half_strength_driver_enable = 1; 82 /* 83 * Write leveling override 84 */ 85 popts->wrlvl_override = 1; 86 popts->wrlvl_sample = 0xf; 87 88 /* 89 * Rtt and Rtt_WR override 90 */ 91 popts->rtt_override = 0; 92 93 /* Enable ZQ calibration */ 94 popts->zq_en = 1; 95 96#ifdef CONFIG_SYS_FSL_DDR4 97 popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm); 98 popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) | 99 DDR_CDR2_VREF_OVRD(70); /* Vref = 70% */ 100#else 101 popts->cswl_override = DDR_CSWL_CS0; 102 103 /* optimize cpo for erratum A-009942 */ 104 popts->cpo_sample = 0x58; 105 106 /* DHC_EN =1, ODT = 75 Ohm */ 107 popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm); 108 popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm); 109#endif 110} 111 112#ifdef CONFIG_SYS_DDR_RAW_TIMING 113dimm_params_t ddr_raw_timing = { 114 .n_ranks = 1, 115 .rank_density = 1073741824u, 116 .capacity = 1073741824u, 117 .primary_sdram_width = 32, 118 .ec_sdram_width = 0, 119 .registered_dimm = 0, 120 .mirrored_dimm = 0, 121 .n_row_addr = 15, 122 .n_col_addr = 10, 123 .n_banks_per_sdram_device = 8, 124 .edc_config = 0, 125 .burst_lengths_bitmask = 0x0c, 126 127 .tckmin_x_ps = 1071, 128 .caslat_x = 0xfe << 4, /* 5,6,7,8 */ 129 .taa_ps = 13125, 130 .twr_ps = 15000, 131 .trcd_ps = 13125, 132 .trrd_ps = 7500, 133 .trp_ps = 13125, 134 .tras_ps = 37500, 135 .trc_ps = 50625, 136 .trfc_ps = 160000, 137 .twtr_ps = 7500, 138 .trtp_ps = 7500, 139 .refresh_rate_ps = 7800000, 140 .tfaw_ps = 37500, 141}; 142 143int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, 144 unsigned int controller_number, 145 unsigned int dimm_number) 146{ 147 static const char dimm_model[] = "Fixed DDR on board"; 148 149 if (((controller_number == 0) && (dimm_number == 0)) || 150 ((controller_number == 1) && (dimm_number == 0))) { 151 memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t)); 152 memset(pdimm->mpart, 0, sizeof(pdimm->mpart)); 153 memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1); 154 } 155 156 return 0; 157} 158#endif 159 160#if defined(CONFIG_DEEP_SLEEP) 161void board_mem_sleep_setup(void) 162{ 163 void __iomem *qixis_base = (void *)QIXIS_BASE; 164 165 /* does not provide HW signals for power management */ 166 clrbits_8(qixis_base + 0x21, 0x2); 167 udelay(1); 168} 169#endif 170 171int fsl_initdram(void) 172{ 173 phys_size_t dram_size; 174 175#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SPL) 176 puts("Initializing DDR....using SPD\n"); 177 dram_size = fsl_ddr_sdram(); 178#else 179 dram_size = fsl_ddr_sdram_size(); 180#endif 181 182#if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD) 183 fsl_dp_resume(); 184#endif 185 186 erratum_a008850_post(); 187 188 gd->ram_size = dram_size; 189 190 return 0; 191} 192 193int dram_init_banksize(void) 194{ 195 gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; 196 gd->bd->bi_dram[0].size = gd->ram_size; 197 198 return 0; 199} 200