1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Bluewater Systems Snapper 9260/9G20 modules 4 * 5 * (C) Copyright 2011 Bluewater Systems 6 * Author: Andre Renaud <andre@bluewatersys.com> 7 * Author: Ryan Mallon <ryan@bluewatersys.com> 8 */ 9 10#include <common.h> 11#include <atmel_lcd.h> 12#include <atmel_lcdc.h> 13#include <atmel_mci.h> 14#include <dm.h> 15#include <env.h> 16#include <init.h> 17#include <net.h> 18#ifndef CONFIG_DM_ETH 19#include <netdev.h> 20#endif 21#include <asm/global_data.h> 22#include <asm/gpio.h> 23#include <asm/io.h> 24#include <asm/mach-types.h> 25#include <asm/arch/at91sam9g45_matrix.h> 26#include <asm/arch/at91sam9_smc.h> 27#include <asm/arch/at91_common.h> 28#include <asm/arch/at91_emac.h> 29#include <asm/arch/at91_rstc.h> 30#include <asm/arch/at91_rtc.h> 31#include <asm/arch/at91_sck.h> 32#include <asm/arch/atmel_serial.h> 33#include <asm/arch/clk.h> 34#include <asm/arch/gpio.h> 35#include <dm/uclass-internal.h> 36#include <linux/delay.h> 37 38#ifdef CONFIG_GURNARD_SPLASH 39#include "splash_logo.h" 40#endif 41 42DECLARE_GLOBAL_DATA_PTR; 43 44/* IO Expander pins */ 45#define IO_EXP_ETH_RESET (0 << 1) 46#define IO_EXP_ETH_POWER (1 << 1) 47 48#ifdef CONFIG_MACB 49static void gurnard_macb_hw_init(void) 50{ 51 struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA; 52 53 at91_periph_clk_enable(ATMEL_ID_EMAC); 54 55 /* 56 * Enable pull-up on: 57 * RXDV (PA12) => MODE0 - PHY also has pull-up 58 * ERX0 (PA13) => MODE1 - PHY also has pull-up 59 * ERX1 (PA15) => MODE2 - PHY also has pull-up 60 */ 61 writel(pin_to_mask(AT91_PIN_PA15) | 62 pin_to_mask(AT91_PIN_PA12) | 63 pin_to_mask(AT91_PIN_PA13), 64 &pioa->puer); 65 66 at91_phy_reset(); 67 68 at91_macb_hw_init(); 69} 70#endif 71 72#ifdef CONFIG_CMD_NAND 73static int gurnard_nand_hw_init(void) 74{ 75 struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX; 76 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; 77 ulong flags; 78 int ret; 79 80 /* Enable CS3 as NAND/SmartMedia */ 81 setbits_le32(&matrix->ebicsa, AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA); 82 83 /* Configure SMC CS3 for NAND/SmartMedia */ 84 writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) | 85 AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0), 86 &smc->cs[3].setup); 87 writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(4) | 88 AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(4), 89 &smc->cs[3].pulse); 90 writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(7), 91 &smc->cs[3].cycle); 92#ifdef CONFIG_SYS_NAND_DBW_16 93 flags = AT91_SMC_MODE_DBW_16; 94#else 95 flags = AT91_SMC_MODE_DBW_8; 96#endif 97 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | 98 AT91_SMC_MODE_EXNW_DISABLE | 99 flags | 100 AT91_SMC_MODE_TDF_CYCLE(3), 101 &smc->cs[3].mode); 102 103 ret = gpio_request(CFG_SYS_NAND_READY_PIN, "nand_rdy"); 104 if (ret) 105 return ret; 106 gpio_direction_input(CFG_SYS_NAND_READY_PIN); 107 108 /* Enable NandFlash */ 109 ret = gpio_request(CFG_SYS_NAND_ENABLE_PIN, "nand_ce"); 110 if (ret) 111 return ret; 112 gpio_direction_output(CFG_SYS_NAND_ENABLE_PIN, 1); 113 114 return 0; 115} 116#endif 117 118#ifdef CONFIG_GURNARD_SPLASH 119static void lcd_splash(int width, int height) 120{ 121 u16 colour; 122 int x, y; 123 u16 *base_addr = (u16 *)gd->video_bottom; 124 125 memset(base_addr, 0xff, width * height * 2); 126 /* 127 * Blit the logo to the center of the screen 128 */ 129 for (y = 0; y < BMP_LOGO_HEIGHT; y++) { 130 for (x = 0; x < BMP_LOGO_WIDTH; x++) { 131 int posx, posy; 132 colour = bmp_logo_palette[bmp_logo_bitmap[ 133 y * BMP_LOGO_WIDTH + x]]; 134 posx = x + (width - BMP_LOGO_WIDTH) / 2; 135 posy = y; 136 base_addr[posy * width + posx] = colour; 137 } 138 } 139} 140#endif 141 142#ifdef CONFIG_VIDEO 143static void at91sam9g45_lcd_hw_init(void) 144{ 145 at91_set_A_periph(AT91_PIN_PE0, 0); /* LCDDPWR */ 146 at91_set_A_periph(AT91_PIN_PE2, 0); /* LCDCC */ 147 at91_set_A_periph(AT91_PIN_PE3, 0); /* LCDVSYNC */ 148 at91_set_A_periph(AT91_PIN_PE4, 0); /* LCDHSYNC */ 149 at91_set_A_periph(AT91_PIN_PE5, 0); /* LCDDOTCK */ 150 151 at91_set_A_periph(AT91_PIN_PE7, 0); /* LCDD0 */ 152 at91_set_A_periph(AT91_PIN_PE8, 0); /* LCDD1 */ 153 at91_set_A_periph(AT91_PIN_PE9, 0); /* LCDD2 */ 154 at91_set_A_periph(AT91_PIN_PE10, 0); /* LCDD3 */ 155 at91_set_A_periph(AT91_PIN_PE11, 0); /* LCDD4 */ 156 at91_set_A_periph(AT91_PIN_PE12, 0); /* LCDD5 */ 157 at91_set_A_periph(AT91_PIN_PE13, 0); /* LCDD6 */ 158 at91_set_A_periph(AT91_PIN_PE14, 0); /* LCDD7 */ 159 at91_set_A_periph(AT91_PIN_PE15, 0); /* LCDD8 */ 160 at91_set_A_periph(AT91_PIN_PE16, 0); /* LCDD9 */ 161 at91_set_A_periph(AT91_PIN_PE17, 0); /* LCDD10 */ 162 at91_set_A_periph(AT91_PIN_PE18, 0); /* LCDD11 */ 163 at91_set_A_periph(AT91_PIN_PE19, 0); /* LCDD12 */ 164 at91_set_B_periph(AT91_PIN_PE20, 0); /* LCDD13 */ 165 at91_set_A_periph(AT91_PIN_PE21, 0); /* LCDD14 */ 166 at91_set_A_periph(AT91_PIN_PE22, 0); /* LCDD15 */ 167 at91_set_A_periph(AT91_PIN_PE23, 0); /* LCDD16 */ 168 at91_set_A_periph(AT91_PIN_PE24, 0); /* LCDD17 */ 169 at91_set_A_periph(AT91_PIN_PE25, 0); /* LCDD18 */ 170 at91_set_A_periph(AT91_PIN_PE26, 0); /* LCDD19 */ 171 at91_set_A_periph(AT91_PIN_PE27, 0); /* LCDD20 */ 172 at91_set_B_periph(AT91_PIN_PE28, 0); /* LCDD21 */ 173 at91_set_A_periph(AT91_PIN_PE29, 0); /* LCDD22 */ 174 at91_set_A_periph(AT91_PIN_PE30, 0); /* LCDD23 */ 175 176 at91_periph_clk_enable(ATMEL_ID_LCDC); 177} 178#endif 179 180#ifdef CONFIG_GURNARD_FPGA 181/** 182 * Initialise the memory bus settings so that we can talk to the 183 * memory mapped FPGA 184 */ 185static int fpga_hw_init(void) 186{ 187 struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX; 188 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; 189 int i; 190 191 setbits_le32(&matrix->ebicsa, AT91_MATRIX_EBI_CS1A_SDRAMC); 192 193 at91_set_a_periph(2, 4, 0); /* EBIA21 */ 194 at91_set_a_periph(2, 5, 0); /* EBIA22 */ 195 at91_set_a_periph(2, 6, 0); /* EBIA23 */ 196 at91_set_a_periph(2, 7, 0); /* EBIA24 */ 197 at91_set_a_periph(2, 12, 0); /* EBIA25 */ 198 for (i = 15; i <= 31; i++) /* EBINWAIT & EBID16 - 31 */ 199 at91_set_a_periph(2, i, 0); 200 201 /* configure SMC cs0 for FPGA access timing */ 202 writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(2) | 203 AT91_SMC_SETUP_NRD(0) | AT91_SMC_SETUP_NCS_RD(2), 204 &smc->cs[0].setup); 205 writel(AT91_SMC_PULSE_NWE(5) | AT91_SMC_PULSE_NCS_WR(4) | 206 AT91_SMC_PULSE_NRD(6) | AT91_SMC_PULSE_NCS_RD(4), 207 &smc->cs[0].pulse); 208 writel(AT91_SMC_CYCLE_NWE(6) | AT91_SMC_CYCLE_NRD(6), 209 &smc->cs[0].cycle); 210 writel(AT91_SMC_MODE_BAT | 211 AT91_SMC_MODE_EXNW_DISABLE | 212 AT91_SMC_MODE_DBW_32 | 213 AT91_SMC_MODE_TDF | 214 AT91_SMC_MODE_TDF_CYCLE(2), 215 &smc->cs[0].mode); 216 217 /* Do a write to within EBI_CS1 to enable the SDCK */ 218 writel(0, ATMEL_BASE_CS1); 219 220 return 0; 221} 222#endif 223 224#ifdef CONFIG_CMD_USB 225 226#define USB0_ENABLE_PIN AT91_PIN_PB22 227#define USB1_ENABLE_PIN AT91_PIN_PB23 228 229void gurnard_usb_init(void) 230{ 231 at91_set_gpio_output(USB0_ENABLE_PIN, 1); 232 at91_set_gpio_value(USB0_ENABLE_PIN, 0); 233 at91_set_gpio_output(USB1_ENABLE_PIN, 1); 234 at91_set_gpio_value(USB1_ENABLE_PIN, 0); 235} 236#endif 237 238#ifdef CONFIG_GENERIC_ATMEL_MCI 239int cpu_mmc_init(struct bd_info *bis) 240{ 241 return atmel_mci_init((void *)ATMEL_BASE_MCI0); 242} 243#endif 244 245static void gurnard_enable_console(int enable) 246{ 247 at91_set_gpio_output(AT91_PIN_PB14, 1); 248 at91_set_gpio_value(AT91_PIN_PB14, enable ? 0 : 1); 249} 250 251void at91sam9g45_slowclock_init(void) 252{ 253 /* 254 * On AT91SAM9G45 revC CPUs, the slow clock can be based on an 255 * internal impreciseRC oscillator or an external 32kHz oscillator. 256 * Switch to the latter. 257 */ 258 unsigned i, tmp; 259 ulong *reg = (ulong *)ATMEL_BASE_SCKCR; 260 261 tmp = readl(reg); 262 if ((tmp & AT91SAM9G45_SCKCR_OSCSEL) == AT91SAM9G45_SCKCR_OSCSEL_RC) { 263 timer_init(); 264 tmp |= AT91SAM9G45_SCKCR_OSC32EN; 265 writel(tmp, reg); 266 for (i = 0; i < 1200; i++) 267 udelay(1000); 268 tmp |= AT91SAM9G45_SCKCR_OSCSEL_32; 269 writel(tmp, reg); 270 udelay(200); 271 tmp &= ~AT91SAM9G45_SCKCR_RCEN; 272 writel(tmp, reg); 273 } 274} 275 276int board_early_init_f(void) 277{ 278 at91_seriald_hw_init(); 279 gurnard_enable_console(1); 280 281 return 0; 282} 283 284int board_init(void) 285{ 286 const char *rev_str; 287#ifdef CONFIG_CMD_NAND 288 int ret; 289#endif 290 291 at91_periph_clk_enable(ATMEL_ID_PIOA); 292 at91_periph_clk_enable(ATMEL_ID_PIOB); 293 at91_periph_clk_enable(ATMEL_ID_PIOC); 294 at91_periph_clk_enable(ATMEL_ID_PIODE); 295 296 at91sam9g45_slowclock_init(); 297 298 /* 299 * Clear the RTC IDR to disable all IRQs. Avoid issues when Linux 300 * boots with spurious IRQs. 301 */ 302 writel(0xffffffff, AT91_RTC_IDR); 303 304 /* Make sure that the reset signal is attached properly */ 305 setbits_le32(AT91_ASM_RSTC_MR, AT91_RSTC_KEY | AT91_RSTC_MR_URSTEN); 306 307 gd->bd->bi_arch_number = MACH_TYPE_SNAPPER_9260; 308 309 /* Address of boot parameters */ 310 gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; 311 312#ifdef CONFIG_CMD_NAND 313 ret = gurnard_nand_hw_init(); 314 if (ret) 315 return ret; 316#endif 317#ifdef CONFIG_ATMEL_SPI 318 at91_spi0_hw_init(1 << 4); 319#endif 320 321#ifdef CONFIG_MACB 322 gurnard_macb_hw_init(); 323#endif 324 325#ifdef CONFIG_GURNARD_FPGA 326 fpga_hw_init(); 327#endif 328 329#ifdef CONFIG_CMD_USB 330 gurnard_usb_init(); 331#endif 332 333#ifdef CONFIG_CMD_MMC 334 at91_set_A_periph(AT91_PIN_PA12, 0); 335 at91_set_gpio_output(AT91_PIN_PA8, 1); 336 at91_set_gpio_value(AT91_PIN_PA8, 0); 337 at91_mci_hw_init(); 338#endif 339 340#ifdef CONFIG_VIDEO 341 at91sam9g45_lcd_hw_init(); 342 at91_set_A_periph(AT91_PIN_PE6, 1); /* power up */ 343 344 /* Select the second timing index for board rev 2 */ 345 rev_str = env_get("board_rev"); 346 if (rev_str && !strncmp(rev_str, "2", 1)) { 347 struct udevice *dev; 348 349 uclass_find_first_device(UCLASS_VIDEO, &dev); 350 if (dev) { 351 struct atmel_lcd_plat *plat = dev_get_plat(dev); 352 353 plat->timing_index = 1; 354 } 355 } 356#endif 357 358 return 0; 359} 360 361int board_late_init(void) 362{ 363 u_int8_t env_enetaddr[8]; 364 char *env_str; 365 char *end; 366 int i; 367 368 /* 369 * Set MAC address so we do not need to init Ethernet before Linux 370 * boot 371 */ 372 env_str = env_get("ethaddr"); 373 if (env_str) { 374 struct at91_emac *emac = (struct at91_emac *)ATMEL_BASE_EMAC; 375 /* Parse MAC address */ 376 for (i = 0; i < 6; i++) { 377 env_enetaddr[i] = env_str ? 378 hextoul(env_str, &end) : 0; 379 if (env_str) 380 env_str = (*end) ? end+1 : end; 381 } 382 383 /* Set hardware address */ 384 writel(env_enetaddr[0] | env_enetaddr[1] << 8 | 385 env_enetaddr[2] << 16 | env_enetaddr[3] << 24, 386 &emac->sa2l); 387 writel((env_enetaddr[4] | env_enetaddr[5] << 8), &emac->sa2h); 388 389 printf("MAC: %s\n", env_get("ethaddr")); 390 } else { 391 /* Not set in environment */ 392 printf("MAC: not set\n"); 393 } 394#ifdef CONFIG_GURNARD_SPLASH 395 lcd_splash(480, 272); 396#endif 397 398 return 0; 399} 400 401#ifndef CONFIG_DM_ETH 402int board_eth_init(struct bd_info *bis) 403{ 404 return macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0); 405} 406#endif 407 408int dram_init(void) 409{ 410 gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, 411 CFG_SYS_SDRAM_SIZE); 412 return 0; 413} 414 415void reset_phy(void) 416{ 417} 418 419static struct atmel_serial_plat at91sam9260_serial_plat = { 420 .base_addr = ATMEL_BASE_DBGU, 421}; 422 423U_BOOT_DRVINFO(at91sam9260_serial) = { 424 .name = "serial_atmel", 425 .plat = &at91sam9260_serial_plat, 426}; 427