- Copy stable/10@296371 to releng/10.3 in preparation for 10.3-RC1
builds.
- Update newvers.sh to reflect RC1.
- Update __FreeBSD_version to reflect 10.3.
- Update default pkg(8) configuration to use the quarterly branch.

Approved by: re (implicit)

MFC 278320,278336,278830,285621:
Add devctl(8): a utility for manipulating new-bus devices. Note that
this version does not include the 'suspend' and 'resume' commands
present in HEAD as those depend on larger changes to the suspend and
resume code in the kernel.

278320:
Add a new device control utility for new-bus devices called devctl. This
allows the user to request administrative changes to individual devices
such as attach or detaching drivers or disabling and re-enabling devices.
- Add a new /dev/devctl2 character device which uses ioctls for device
requests. The ioctls use a common 'struct devreq' which is somewhat
similar to 'struct ifreq'.
- The ioctls identify the device to operate on via a string. This
string can either by the device's name, or it can be a bus-specific
address. (For unattached devices, a bus address is the only way to
locate a device.) Bus drivers register an eventhandler to claim
unrecognized device names that the driver recognizes as a valid address.
Two buses currently support addresses: ACPI recognizes any device
in the ACPI namespace via its full path starting with "\" and
the PCI bus driver recognizes an address specification of
'pci[<domain>:]<bus>:<slot>:<func>' (identical to the PCI selector
strings supported by pciconf).
- To make it easier to cut and paste, change the PnP location string
in the PCI bus driver to output a full PCI selector string rather
than 'slot=<slot> function=<func>'.
- Add a devctl(3) interface in libdevctl which provides a wrapper around
the ioctls and is the preferred interface for other userland code.
- Add a devctl(8) program which is a simple wrapper around the requests
supported by devctl(3).
- Add a resource_unset_value() function that can be used to remove a
hint from the kernel environment. This is used to clear a
hint.<driver>.<unit>.disabled hint when re-enabling a boot-time
disabled device.

278336:
Unbreak the build (memchr is explicitly required by devctl(9) after r278320)

278830:
install the man page...

285621:
Fix formatting.

Approved by: re (marius)

MFC 292669:
Add accessor methods to fetch the BAR holding the MSI-X table and PBA.

While here, explicitly note the requirement that the BAR(s) must be
allocated prior to calling pci_alloc_msix().

MFC r278860:
r278860 (by jmg):

remove NULL check as M_WAITOK will not return NULL

Reviewed by: jhb
Sponsored by: FreeBSD Foundation

MFC r270212,r270332:

This helps reduce the diff in pci(4) between head and stable/10 to help pave
the way for bringing in IOV/nv(9) more cleanly

Differential Revision: https://reviews.freebsd.org/D4728
Relnotes: yes
Reviewed by: hselasky (ofed piece), royger (overall change)
Sponsored by: EMC / Isilon Storage Division

r270212 (by royger):

pci: make MSI(-X) enable and disable methods of the PCI bus

Make the functions pci_disable_msi, pci_enable_msi and pci_enable_msix
methods of the newbus PCI bus. This code should not include any
functional change.

Sponsored by: Citrix Systems R&D
Reviewed by: imp, jhb
Differential Revision: https://reviews.freebsd.org/D354

dev/pci/pci.c:
- Convert the mentioned functions to newbus methods.
- Fix the callers of the converted functions.

sys/dev/pci/pci_private.h:
dev/pci/pci_if.m:
- Declare the new methods.

dev/pci/pcivar.h:
- Add helpers to call the newbus methods.

ofed/include/linux/pci.h:
- Add define to prevent the ofed version of pci_enable_msix from
clashing with the FreeBSD native version.

r270332 (by royger):

pci: add a new pci_child_added newbus method.

This is needed so when running under Xen the calls to pci_child_added
can be intercepted and a custom Xen method can be used to register
those devices with Xen. This should not include any functional
change, since the Xen implementation will be added in a following
patch and the native implementation is a noop.

Sponsored by: Citrix Systems R&D
Reviewed by: jhb

dev/pci/pci.c:
dev/pci/pci_if.m:
dev/pci/pci_private.h:
dev/pci/pcivar.h:
- Add the pci_child_added newbus method.

MFC 290414,290415:
Additional PCI helper functions.

290414:
Add helper routines for PCI device drivers to read, write, and modify
PCI-Express capability registers (that is, PCI config registers in the
standard PCI config space belonging to the PCI-Express capability
register set).

Note that all of the current PCI-e registers are either 16 or 32-bits,
so only widths of 2 or 4 bytes are supported.

290415:
Add a new helper function for PCI devices to locate the upstream
PCI-express root port of a given PCI device.

Partially revert r284034. In particular, revert the final change in this
MFC (281874). It broke suspend and resume on several Thinkpads (though not
all) in 10 even though it works fine on the same laptops in HEAD.

PR: 201239
Reported by: Kevin Oberman and several others

MFC 274633,274639,274663,277233-277235,281870,281871,281873,281874:
Various fixes for suspend and resume of PCI to PCI and PCI to Cardbus
bridges.

274633:

Remove stray empty comment. The code is adequately explained in the
block comment above, so there's nothing to add here.

274639:

Modernize comments about BIOSes being lame since in this detail they
aren't lame, the rules changed along the way. Catch up to 1999 or so
with the new rules.

274663:

Fix typo pointed out by avg@ and Joerg Sonnenberger. Add a clarifying
sentence too.

277233:

Suspend and resume were the only two functions not to follow the brdev
convention here, so fix that.

277234:

Move the suspsned and resume functions to the bus attachment. They
were accessing PCI config registers, which won't work for the ISA
version.

277235:

Always enable I/O, memory and dma cycles. Some BIOSes don't enable
them, sometimes they are reset for power state transitions or during
whatever happens while suspended. Also, it is good practice to always
do this.

281870:

Cosmetic change: use PCIR_SECLAT_2 rather than PCIR_SECLAT_1.

281871:

The minimim grant and maximum latency PCI config registers are only valid
for type 0 devices, not type 1 or 2 bridges. Don't read them for bridge
devices during bus scans and return an error when attempting to read them
as ivars for bridge devices.

281873:

Don't explicitly manage power states for PCI-PCI bridge devices in the
driver's suspend and resume routines. These have been redundant no-ops
since r214065 changed the PCI bus driver to manage power states for
all devices (including type 1/2 bridge devices) during suspend and resume.

281874:

Update the pci_cfg_save/restore routines to operate on bridge devices
(type 1 and type 2) as well as leaf devices (type 0). In particular,
this allows the existing PCI bus logic to save and restore capability
registers such as MSI and PCI-express work for bridge devices rather than
requiring that code to be duplicated in bridge drivers. It also means
that bridge drivers no longer need to save and restore basic registers
such as the PCI command register or BARs nor manage powerstates for the
bridge device.

While here, pci_setup_secbus() has been changed to initialize the 'sec'
and 'sub' fields in the 'secbus' structure instead of requiring the pcib
and pccbb drivers to do this in the NEW_PCIB + PCI_RES_BUS case.

MFC r283735:
Remove several write-only variables.

MFC 261790:
Add support for managing PCI bus numbers. As with BARs and PCI-PCI bridge
I/O windows, the default is to preserve the firmware-assigned resources.
PCI bus numbers are only managed if NEW_PCIB is enabled and the architecture
defines a PCI_RES_BUS resource type.
- Add a helper API to create top-level PCI bus resource managers for each
PCI domain/segment. Host-PCI bridge drivers use this API to allocate
bus numbers from their associated domain.
- Change the PCI bus and CardBus drivers to allocate a bus resource for
their bus number from the parent PCI bridge device.
- Change the PCI-PCI and PCI-CardBus bridge drivers to allocate the
full range of bus numbers from secbus to subbus from their parent bridge.
The drivers also always program their primary bus register. The bridge
drivers also support growing their bus range by extending the bus resource
and updating subbus to match the larger range.
- Add support for managing PCI bus resources to the Host-PCI bridge drivers
used for amd64 and i386 (acpi_pcib, mptable_pcib, legacy_pcib, and qpi_pcib).
- Define a PCI_RES_BUS resource type for amd64 and i386.

PR: 197076

MFC r271889, 272799, 272800, 274976
This brings in bus_get_domain() and the related reporting via devinfo,
dmesg, and sysctl.

Obtained from: adrian, jhb
Sponsored by: Netflix, Inc.

MFC r264091

Correct a PCI enumeration bug introduced in r264011

Ensure that first_func is set to 0 on every iteration of the PCI slot
enumeration loop after the first. There is a continue statement that would
cause first_func to stay at 1 any PCI device where slot 0 has no functions
until we find a slot that does have a function. This would cause us to
not enumerate the first PCI function on the device.

Credit to markj@ for spotting the bug.

X-MFC-With: r264011

MFC r264007,r264008,r264009,r264011,r264012,r264013

MFC support for PCI Alternate RID Interpretation. ARI is an optional PCIe
feature that allows PCI devices to present up to 256 functions on a bus.
This is effectively a prerequisite for PCI SR-IOV support.

r264007:
Add a method to get the PCI RID for a device.

Reviewed by: kib
MFC after: 2 months
Sponsored by: Sandvine Inc.

r264008:
Re-implement the DMAR I/O MMU code in terms of PCI RIDs

Under the hood the VT-d spec is really implemented in terms of
PCI RIDs instead of bus/slot/function, even though the spec makes
pains to convert back to bus/slot/function in examples. However
working with bus/slot/function is not correct when PCI ARI is
in use, so convert to using RIDs in most cases. bus/slot/function
will only be used when reporting errors to a user.

Reviewed by: kib
MFC after: 2 months
Sponsored by: Sandvine Inc.

r264009:
Re-write bhyve's I/O MMU handling in terms of PCI RID.

Reviewed by: neel
MFC after: 2 months
Sponsored by: Sandvine Inc.

r264011:
Add support for PCIe ARI

PCIe Alternate RID Interpretation (ARI) is an optional feature that
allows devices to have up to 256 different functions. It is
implemented by always setting the PCI slot number to 0 and
re-purposing the 5 bits used to encode the slot number to instead
contain the function number. Combined with the original 3 bits
allocated for the function number, this allows for 256 functions.

This is enabled by default, but it's expected to be a no-op on currently
supported hardware. It's a prerequisite for supporting PCI SR-IOV, and
I want the ARI support to go in early to help shake out any bugs in it.
ARI can be disabled by setting the tunable hw.pci.enable_ari=0.

Reviewed by: kib
MFC after: 2 months
Sponsored by: Sandvine Inc.

r264012:
Print status of ARI capability in pciconf -c

Teach pciconf how to print out the status (enabled/disabled) of the ARI
capability on PCI Root Complexes and Downstream Ports.

MFC after: 2 months
Sponsored by: Sandvine Inc.

r264013:
Add missing copyright date.

MFC after: 2 months

MFC: r276299

- Make PCI_QUIRK_MSI_INTX_BUG work by using the ID of the actual PCI device
for the lookup.
- For devices affected by PCI_QUIRK_MSI_INTX_BUG, ensure PCIM_CMD_INTxDIS
is cleared when using MSI/MSI-X.
- Employ PCI_QUIRK_MSI_INTX_BUG for BCM5714(S)/BCM5715(S)/BCM5780(S) rather
than clearing PCIM_CMD_INTxDIS unconditionally for all devices in bge(4).

MFC r272729,272732:
Add new quirk PCI_QUIRK_MSI_INTX_BUG to pci(4).
QAC AR816x/E2200 controller has a silicon bug that MSI interrupt
does not assert if PCIM_CMD_INTxDIS bit of command register is set.

MFC r266468:
Add IOMMU PCI subclass, found on Tyan S8236 motherboard.

Submitted by: Dmitry Luhtionov <dmitryluhtionov@gmail.com>

MFC r265149

Make uninteresting PCI devices with no attached drivers only print out
on a verbose boot.

Sponsored by: Multiplay

MFC 261524,261526,261527:
- Properly set the alignment flags when allocating the initial range for a
BAR. This only really matters when pci_do_realloc_bars is enabled and
the initial allocation of a specific range fails.
- Simplify pci_reserve_map() by calling resource_list_reserve() to allocate
the resource after creating a resource list entry rather than reimplementing
it by hand.
- Add two tunables to ignore certain firmware-assigned resources. These
are mostly useful for debugging.
- hw.pci.clear_bars ignores all firmware-assigned ranges for BARs when
set.
- hw.pci.clear_pcib ignores all firmware-assigned ranges for PCI-PCI
bridge I/O windows when set.

MFC 260926:
Add support for displaying VPD for PCI devices via pciconf.
- Store the length of each read-only VPD value since not all values are
guaranteed to be ASCII values (though most are).
- Add a new pciio ioctl to fetch VPD for a single PCI device. The values
are returned as a list of variable length records, one for the device
name and each keyword.
- Add a new -V flag to pciconf's list mode which displays VPD data for
each device.

MFC r257072:
Make pci_get_dma_tag() non-static.

Approved by: re (glebius)

MFC r257070:
Move the PCI_DMA_BOUNDARY definition into the pcivar.h.

Approved by: re (glebius)

Copy head (r256279) to stable/10 as part of the 10.0-RELEASE cycle.

Approved by: re (implicit)
Sponsored by: The FreeBSD Foundation

Properly handle I/O windows in bridges with the ISA enable bit set. These
beasts still exist unfortunately. More details can be found in other
references, but the short version is that bridges with this bit set ignore
I/O port ranges that alias to valid ISA I/O port ranges. In the driver
this requires not allocating these alias regions from the parent device
(so they are free to be acquired by ISA devices), and ensuring no child
devices use resources from these alias regions.
- Change the pcib_window structure to allow for an array of backing
resources rather than a single resource and update the existing code
to cope with this. Some of the coping requires using the saved
base and limit values in pcib_window instead of using rman operations
on the backing resource.
- Add special handling for allocating and adjusting the I/O port window
of an ISA-enabled bridge to only allocate the non-alias ranges and
add those to the associated resource manager.
- Reject I/O port allocations for a fixed request that conflicts with an
ISA alias range.
- Remove the "no prefected decode" verbose printf during boot. The absence
of a "prefetched decode" line is sufficient.
- Replace the "subtractively decoded bridge" verbose printf with a single
printf that lists all the "special" decoding modes of a bridge: ISA,
subtractive, and VGA.
- Add a custom bus_release_resource() method to the PCI bus driver so that
it can properly free resources for I/O windows of PCI-PCI bridges.
(These resources are not stored in the bridge device's resource list.)

PR: misc/179033
MFC after: 2 weeks

- As it turns out, not only MSI-X is broken for devices passed through by
VMware up to at least ESXi 5.1. Actually, using INTx in that case instead
may still result in interrupt storms, with MSI being the only working
option in some configurations. So introduce a PCI_QUIRK_DISABLE_MSIX quirk
which only blacklists MSI-X but not also MSI and use it for the VMware
PCI-PCI-bridges. Note that, currently, we still assume that if MSI doesn't
work, MSI-X won't work either - but that's part of the internal logic and
not guaranteed as part of the API contract. While at it, add and employ
a pci_has_quirk() helper.
Reported and tested by: Paul Bucher
- Use NULL instead of 0 for pointers.

Submitted by: jhb (mostly)
Approved by: jhb
MFC after: 3 days

Make detaching drivers from PCI devices more robust. While here, fix a
bug where a PCI device would be powered down if it failed to probe, but
not when its driver was detached (e.g. via kldunload).
- Add a new helper method resource_list_release_active() which forcefully
releases any active resources of a specified type from a resource list.
- Add a bus_child_detached method for the PCI bus driver which forces any
active resources to be released (and whines to the console if it finds
any) and then powers the device down.
- Call pci_child_detached() if we fail to probe a device when a driver
is kldloaded. This isn't perfect but can avoid leaking resources
from a probe() routine in the kldload case.

Reviewed by: imp, brooks
MFC after: 1 month

Disable hw.pci.realloc_bars by default. It wasn't needed for the original
tester of this fix, and realloc_bars breaks some other cases as a small
BAR that is reallocated can end up grabbing space needed by a much larger
BAR in the existing window of a PCI-PCI bridge.

MFC after: 3 days

Revision 233677 broke certain machines. Specifically, if the firmware/BIOS
assigned conflicting ranges to BARs then leaving the BARs alone could
result in one device stealing mmio accesses intended to go to a second
device. Prior to 233677 the PCI bus driver attempted to handle this case
by clearing the BAR to 0 depending on BARs based at 0 not decoding (which
is not guaranteed to be true). Now when a conflicting BAR is detected the
following steps are taken:

1) If hw.pci.realloc_bars (a new tunable) is enabled (default is enabled),
then ignore the current BAR setting from the firmware and attempt to
allocate a fresh resource range for the BAR.

2) If 1) failed (or was disabled), disable decoding for the relevant
BAR type (e.g. disable mem decoding for a memory BAR) and emit a
warning if booting verbose.

Tested by: Alex Keda <admin@lissyara.su>
MFC after: 1 week

- Complete r231621 by also blacklisting the bridge used by VMware for PCIe
devices. While at it, update the comment now that we know that MSI-X
doesn't work with ESXi 5.1 for Intel 82576 either and the underlying issue
is a bug in the MSI-X allocation code of the hypervisor.
Reported by: Harald Schmalzbauer
- Make the nomatch table const.

MFC after: 1 week

Remove the quirk to allow use of MSI when the guest is running inside bhyve.

This became redundant after the hostbridge presented to the guest started
advertising the PCI-E capability (r246846).

Obtained from: NetApp

Add quirk to indicate that the bhyve hostbridge is capable of supporting
MSI and MSI-X even though it does not advertise the PCI-E capability
itself.

Obtained from: NetApp

Remove duplicate const specifiers in many drivers (I hope I got all of
them, please let me know if not). Most of these are of the form:

static const struct bzzt_type {
[...list of members...]
} const bzzt_devs[] = {
[...list of initializers...]
};

The second const is unnecessary, as arrays cannot be modified anyway,
and if the elements are const, the whole thing is const automatically
(e.g. it is placed in .rodata).

I have verified this does not change the binary output of a full kernel
build (except for build timestamps embedded in the object files).

Reviewed by: yongari, marius
MFC after: 1 week

The correct generic term for PCIS_STORAGE_NVM is "NVM" not "NVM Express".

Submitted by: jimharris
MFC after: 6 days

Recognise NVM Express devices and pretty-print their name.

MFC after: 1 week

Align the PCI Express #defines with the style used for the PCI-X
#defines. This also has the advantage that it makes the names more
compact, iand also allows us to correct the non-uniform naming of
the PCIM_LINK_* defines, making them all consistent amongst themselves.

This is a mostly mechanical rename:
s/PCIR_EXPRESS_/PCIER_/g
s/PCIM_EXP_/PCIEM_/g
s/PCIM_LINK_/PCIEM_LINK_/g

When this is MFC'd, #defines will be added for the old names to assist
out-of-tree drivers.

Discussed with: jhb
MFC after: 1 week

Only check to see if a memory resource is a PCI ROM BAR when activating
and deactivating PCI resources. Previously, if a device had more than
48 MSI interrupts, then activating message 48 (which has a rid == PCIR_BIOS)
would incorrectly try to enable the PCI ROM BAR.

Tested by: Olivier Cinquin ocinquin uci edu
MFC after: 3 days

Fix couple of style nits.

Revert r233662 and generalize the hack. Writing zero to BAR actually does
not disable it and it is even harmful as hselasky found out. Historically,
this code was originated from (OLDCARD) CardBus driver and later leaked into
PCI driver when CardBus was newbus'ified and refactored with PCI driver.
However, it is not really necessary even for CardBus.

Reviewed by: hselasky, imp, jhb

Use a more proper fix for enabling HT MSI mapping windows on Host-PCI
bridges. Rather than blindly enabling the windows on all of them, only
enable the window when an MSI interrupt is enabled for a device behind
the bridge, similar to what already happens for HT PCI-PCI bridges.

To implement this, each x86 Host-PCI bridge driver has to be able to
locate it's actual backing device on bus 0. For ACPI, use the _ADR
method to find the slot and function of the device. For the non-ACPI
case, the legacy(4) driver already scans bus 0 looking for Host-PCI
bridge devices. Now it saves the slot and function of each bridge that
it finds as ivars that the Host-PCI bridge driver can then use in its
pcib_map_msi() method.

This fixes machines where non-MSI interrupts were broken by the previous
round of HT MSI changes.

Tested by: bapt
MFC after: 1 week

Fix for boot issue: Don't disable BARs on AGP devices. In general:
Don't disable BARs on any PCI display devices, because doing that can
sometimes cause the main memory bus to stop working, causing all
memory reads to return nothing but 0xFFFFFFFF, even though the memory
location was previously written. After a while a privileged
instruction fault will appear and then nothing more can be debugged.
The reason for this behaviour is unknown.

MFC after: 1 week

Add a PCI quirk to ignore PCI map registers from configuration space.
For example, some BIOS for AMD SB600 south bridge may map HPET MMIO base
address as a memory BAR for SMBus controller depending on a PM register
configuration. Before r231161 (and r232086, subsequent MFC to stable/9),
it was not fatal but hpet(4) just failed to attach. Since we probe and
attach HPET earlier than PCI devices now, it caused unfortunate hard lockup.
With this patch, it does not hang any more and HPET works at the same time.
Clean up some style nits while I am in the neighborhood.

PR: kern/165647
Reviewed by: jhb
MFC after: 3 days

Save more of config space for PCI Express and PCI-X devices.

Expand pci_save_state and pci_restore_state to save more of
the config state for PCI Express and PCI-X devices. Various
writable control registers are present in PCI Express that
can potentially be lost over suspend/resume cycle.

This change is modeled after similar functionality in Linux.

Reviewed by: wlosh,jhb
MFC after: 1 month

Remove the PAE-specific 2GB DMA boundary since HEAD now supports a proper 4G
boundary for PAE.

Simplify the PCI bus dma tag code a bit. First, don't create a tag at
all for platforms that only have 32-bit bus addresses. Second, remove
the 'tag_valid' flag from the softc. Instead, if we don't create a
tag in pci_attach_common(), just cache the value of our parent's tag
so that we always have a valid tag to return.

Expand the set of APIs available for locating PCI capabilities:
- pci_find_extcap() is repurposed to be used for fetching PCI-express
extended capabilities (PCIZ_* constants in <dev/pci/pcireg.h>).
- pci_find_htcap() can be used to locate a specific HyperTransport
capability (PCIM_HTCAP_* constants in <dev/pci/pcireg.h>).
- Cache the starting location of the PCI-express capability for PCI-express
devices in PCI device ivars.

Fix a typo.

- Add a bus_dma tag to each PCI bus that is a child of a Host-PCI bridge.
The tag enforces a single restriction that all DMA transactions must not
cross a 4GB boundary. Note that while this restriction technically only
applies to PCI-express, this change applies it to all PCI devices as it
is simpler to implement that way and errs on the side of caution.
- Add a softc structure for PCI bus devices to hold the bus_dma tag and
a new pci_attach_common() routine that performs actions common to the
attach phase of all PCI bus drivers. Right now this only consists of
a bootverbose printf and the allocate of a bus_dma tag if necessary.
- Adjust all PCI bus drivers to allocate a PCI bus softc and to call
pci_attach_common() from their attach routines.

MFC after: 2 weeks

Add pci_save_state() and pci_restore_state() wrappers around
pci_cfg_save() and pci_cfg_restore() for device drivers to use when
saving and restoring state (e.g. to handle device-specific resets).

Reviewed by: imp
MFC after: 2 weeks

Use pci_printf() instead of a home-rolled version in the VPD parsing code.

- As it turns out, MSI-X is broken for at least LSI SAS1068E when passed
through by VMware so blacklist their PCI-PCI bridge for MSI/MSI-X here.
Note that besides currently there not being a quirk type that disables
MSI-X only and there's no evidence that MSI doesn't work with the VMware
pass-through, it's really questionable whether MSI generally works in
that setup as VMware only mention three know working devices [1, p. 4].
Also not that this quirk entry currently doesn't affect the devices
emulated by VMware in any way as these don't claim support MSI/MSI-X to
begin with. [2]
While at it, make the PCI quirk table const and static.
- Remove some duplicated empty lines.
- Use DEVMETHOD_END.

PR: 163812, http://forums.freebsd.org/showthread.php?t=27899 [2]
Reviewed by: jhb
MFC after: 3 days

Properly return success once a matching VPD entry is found in
pci_get_vpd_readonly_method(). Previously the loop was always running
to completion and falling through to failing with ENXIO.

PR: kern/164313
Submitted by: Chuck Tuffli chuck tuffli net
MFC after: 1 week

Add missing XHCI early takeover code. The XHCI takeover code
is supposed to disable the BIOS from using the XHCI controller
after bootup.

Approved by: re (kib)
Reported by: Mike Tancsa
MFC after: 1 week

PCIB_ALLOC_MSIX() may already fail on the first pass, f.e. when the PCI-PCI
bridge is blacklisted. In that case just return from pci_alloc_msix_method(),
otherwise we continue without a single MSI-X resource, causing subsequent
attempts to use the seemingly available resource to fail or when booting
verbose a NULL-pointer dereference of rle->start when trying to print the
IRQ in pci_alloc_msix_method().

Reviewed by: jhb
MFC after: 1 week

Implement pci_find_class(9), the function to find a pci device by its class.

Sponsored by: The FreeBSD Foundation
Reviewed by: jhb
MFC after: 1 week

Minor whitespace and style fixes.

More properly handle Cardbus cards that that store their CIS in a BAR after
the recent changes to track BAR state explicitly. The code would now
attempt to add the same BAR twice in this case. Instead, change this so
that it recognizes this case and only adds it once and do not delete the
BAR outright after parsing the CIS.

Tested by: bschmidt

Reimplement how PCI-PCI bridges manage their I/O windows. Previously the
driver would verify that requests for child devices were confined to any
existing I/O windows, but the driver relied on the firmware to initialize
the windows and would never grow the windows for new requests. Now the
driver actively manages the I/O windows.

This is implemented by allocating a bus resource for each I/O window from
the parent PCI bus and suballocating that resource to child devices. The
suballocations are managed by creating an rman for each I/O window. The
suballocated resources are mapped by passing the bus_activate_resource()
call up to the parent PCI bus. Windows are grown when needed by using
bus_adjust_resource() to adjust the resource allocated from the parent PCI
bus. If the adjust request succeeds, the window is adjusted and the
suballocation request for the child device is retried.

When growing a window, the rman_first_free_region() and
rman_last_free_region() routines are used to determine if the front or
end of the existing I/O window is free. From using that, the smallest
ranges that need to be added to either the front or back of the window
are computed. The driver will first try to grow the window in whichever
direction requires the smallest growth first followed by the other
direction if that fails.

Subtractive bridges will first attempt to satisfy requests for child
resources from I/O windows (including attempts to grow the windows). If
that fails, the request is passed up to the parent PCI bus directly
however.

The PCI-PCI bridge driver will try to use firmware-assigned ranges for
child BARs first and only allocate a "fresh" range if that specific range
cannot be accommodated in the I/O window. This allows systems where the
firmware assigns resources during boot but later wipes the I/O windows
(some ACPI BIOSen are known to do this) to "rediscover" the original I/O
window ranges.

The ACPI Host-PCI bridge driver has been adjusted to correctly honor
hw.acpi.host_mem_start and the I/O port equivalent when a PCI-PCI bridge
makes a wildcard request for an I/O window range.

The new PCI-PCI bridge driver is only enabled if the NEW_PCIB kernel option
is enabled. This is a transition aide to allow platforms that do not
yet support bus_activate_resource() and bus_adjust_resource() in their
Host-PCI bridge drivers (and possibly other drivers as needed) to use the
old driver for now. Once all platforms support the new driver, the
kernel option and old driver will be removed.

PR: kern/143874 kern/149306
Tested by: mav

Add implementations of BUS_ADJUST_RESOURCE() to the PCI bus driver,
generic PCI-PCI bridge driver, x86 nexus driver, and x86 Host to PCI bridge
drivers.

Only align MSI message groups based on the number of messages being
allocated, not the maximum number of messages the device supports. The
spec only requires the former, and I believe I implemented the latter due
to misunderstanding an e-mail. In particular, this fixes an issue where
having several devices that all support 16 messages can run out of
IDT vectors on x86 even though the driver only uses a single message.

Submitted by: Bret Ketchum bcketchum of gmail
MFC after: 1 week

Explicitly track the state of all known BARs for each PCI device. The PCI
bus driver will now remember the size of a BAR obtained during the initial
bus scan and use that size when doing lazy resource allocation rather than
resizing the BAR. The bus driver will now also report unallocated BARs to
userland for display by 'pciconf -lb'. Psuedo-resources that are not BARs
(such as the implicit I/O port resources for master/slave ATA controllers)
will no longer be listed as BARs in 'pciconf -lb'. During resume, BARs are
restored from their new saved state instead of having the raw registers
saved and restored across resume. This also fixes restoring BARs at
unusual loactions if said BAR has been allocated by a driver.

Add a constant for the offset of the ROM BIOS BAR in PCI-PCI bridges and
properly handle ROM BIOS BARs in PCI-PCI bridges. The PCI bus now also
properly handles the lack of a ROM BIOS BAR in a PCI-Cardbus bridge.

Tested by: jkim

Rename pci_find_extcap() to pci_find_cap(). PCI now uses the term
"extended capabilities" to refer to the new set of capability structures
starting at offset 0x100 in config space for PCI-express devices. For now
both function names will still work. I will merge this to older branches
to ease driver portability, but 9.0 will ship with a new pci_find_extcap()
function that locates extended capabilities instead.

Reviewed by: imp
MFC after: 1 week

Partially revert previous change. Drop the quirk to disable MSI for HT
chipsets that do not have an HT slave at 0:0:0:0. The Linux quirk is
actually specific to Nvidia chipsets and the check I had added was in
the wrong place.

Prodded by: nathanw

Fix a few issues with HyperTransport devices and MSI interrupts:
- Always enable the HyperTransport MSI mapping window for HyperTransport
to PCI bridges (these show up as HyperTransport slave devices).
The mapping windows in PCI-PCI bridges are enabled by existing code
in the PCI-PCI bridge driver as MSI requests propagate up the device
tree, but Host-PCI bridges don't really show up in that tree.
- If the PCI device at domain 0 bus 0 slot 0 function 0 is not a
HyperTransport device, then blacklist MSI on any other HT devices in
the system. Linux has a similar quirk.

PR: kern/155442
Tested by: Zack Dannar zdannar of gmail
MFC after: 1 week

Properly handle BARs bigger than 4G. The '1' was treated as an int
causing the size calculation to be truncated to the size of an int
(32-bits on all current architectures).

Submitted by: Anish akgupt3 of gmail
MFC after: 1 week

Use the preload_fetch_addr() and preload_fetch_size() convenience
functions to obtain the address and size of the PCI vendor data.

Sponsored by: Juniper Networks.

Resume critical PCI devices (and their children) first, then everything else
later. This give us better chance to catch device driver problems.

The EHCI_CAPLENGTH and EHCI_HCIVERSION registers are actually sub-registers
within the first 4 bytes of the EHCI memory space. For controllers that
use big-endian MMIO, reading them with 1- and 2-byte reads would then
return the wrong values. Instead, read the combined register with a 4-byte
read and mask out the interesting quantities.

- Add a new PCI quirk to whitelist an old chipset that doesn't support
PCI-express or PCI-X capabilities if we are running in a virtual machine.
- Whitelist the Intel 82440 chipset used by QEMU.

Tested by: jfv
MFC after: 1 week

Clarify a misleading comment. The test in pci_reserve_map() was meant to
ignore BARs that are invalid due to having a size of zero, not to ignore
BARs with an existing base of zero. While here, reorganize the code
slightly to make the intent clearer.

Reported by: avg
MFC after: 1 week

Update PCI power management registers per PCI Bus Power Management Interface
Specification Rev. 1.2. Rename pp_pcmcsr field of PM capabilities to pp_bse
to avoid further confusions and adjust some comments accordingly. The real
PMCSR (Power Management Control/Status Register) is PCIR_POWER_STATUS and
it is actually BSE (PCI-to-PCI Bridge Support Extensions) register.

Introduce a new tunable 'hw.pci.do_power_suspend'. This tunable lets you
avoid PCI power state transition from D0 to D3 for suspending case. Default
is 1 or enabled.

Remove PCI header type 0 restriction from power state changes. PCI config.
registers for bridges are saved and restored since r200341.

OK'ed by: imp, jhb

Do not apply do_power_resume for suspending case. When do_powerstate was
splitted into do_power_resume and do_power_nodriver, it became stale.

Remove unnecessary castings and fix couple of style(9) nits.

Move setting power state for children into a separate function as they were
essentially the same. This also restores hw.pci.do_power_resume tunable,
which was broken since r211430.

Reviewed by: jhb

Add a new method to the PCI bridge interface, PCIB_POWER_FOR_SLEEP(). This
method is used by the PCI bus driver to query the power management system
to determine the proper device state to be used for a device during suspend
and resume. For the ACPI PCI bridge drivers this calls
acpi_device_pwr_for_sleep(). This removes ACPI-specific knowledge from
the PCI and PCI-PCI bridge drivers.

Reviewed by: jkim

Consistently check header type after reading PCIR_HDRTYPE register.
While I'm here use defined macro instead of using magic numbers for
header type.

Reviewed by: jhb

Virtualize pci_remap_msi_irq() call from general MSI code. It allows MSI
(FSB interrupts) to be used by non-PCI devices, such as HPET.

Honor hw.pci.do_power_nodriver on resume. Power-down devices without
driver attached.

Add support for the U4 PCI-Express bridge chipset used in late-generation
Powermac G5 systems. MSI and several other things are not presently
supported.

The U3/U4 internal device support portions of this change were contributed
by Andreas Tobler.

MFC after: 1 week

Add pci_get|set_max_read_req() helper functions to control maximum PCIe
read request size.

Reviewed by: jhb@

Move the PCI-specific logic of removing a cardbus device into a
pci_delete_child() function called by the cardbus driver. The new function
uses resource_list_unreserve() to release the BARs decoded by the device
being removed.

Reviewed by: imp
Tested by: brooks

Teach the PCI bus driver to handle PCIR_BIOS BARs properly and remove special
handling for the PCIR_BIOS decoding enable bit from the cardbus driver.
The PCIR_BIOS BAR does include type bits like other BARs. Instead, it is
always a 32-bit non-prefetchable memory BAR where the low bit is used as a
flag to enable decoding.

Reviewed by: imp

Remove no longer used pci_release_resource().

Implement a rudimentary suspend/resume methods for PCI P2P bridge.

Reviewed by: jhb, imp

For some buses, devices may have active resources assigned even though they
are not allocated by the device driver. These resources should still appear
allocated from the system's perspective so that their assigned ranges are
not reused by other resource requests. The PCI bus driver has used a hack
to effect this for a while now where it uses rman_set_device() to assign
devices to the PCI bus when they are first encountered and later assigns
them to the actual device when a driver allocates a BAR. A few downsides of
this approach is that it results in somewhat confusing devinfo -r output as
well as not being very easily portable to other bus drivers.

This commit adds generic support for "reserved" resources to the resource
list API used by many bus drivers to manage the resources of child devices.
A resource may be reserved via resource_list_reserve(). This will allocate
the resource from the bus' parent without activating it.
resource_list_alloc() recognizes an attempt to allocate a reserved resource.
When this happens it activates the resource (if requested) and then returns
the reserved resource. Similarly, when a reserved resource is released via
resource_list_release(), it is deactivated (if it is active) and the
resource is then marked reserved again, but is left allocated from the
bus' parent. To completely remove a reserved resource, a bus driver may
use resource_list_unreserve(). A bus driver may use resource_list_busy()
to determine if a reserved resource is allocated by a child device or if
it can be unreserved.

The PCI bus driver has been changed to use this framework instead of
abusing rman_set_device() to keep track of reserved vs allocated resources.

Submitted by: imp (an older version many moons ago)
MFC after: 1 month

Disable interrupts after doing early takeover of the usb controller in case usb
isnt actually compiled in (or kldloaded) as the controller could cause spurious
interrupts.

Tested by: Florian Smeets

BIOSes, buggy or otherwise, are i386 or amd64 specific.
Have the early USB takeover enabled for i386 and amd64
by default.
This also avoids a panic on PowerPC where the resource
isn't released properly and we find a busy resource
when the USB host controller wants to allocate it...

Workaround buggy BIOS code in USB regard. By doing the BIOS to OS handover for
all host controllers at the same time, we avoid problems where the BIOS will
actually write to the USB registers of all the USB host controllers every time
we handover one of them, and consequently reset the OS programmed values.

Submitted by: avg
Reviewed by: jhb

Don't reread the command register to see if enabling I/O or memory
decoding "took". Other OS's that I checked do not do this and it breaks
some amdpm(4) devices. Prior to 7.2 we did not honor the error returned
when this failed anyway, so this in effect restores previous behavior.

PR: kern/137668
Tested by: Aurelien Mere aurelien.mere amc-os.com
MFC after: 3 days

Add a MD __PCI_BAR_ZERO_VALID which denotes that BARs containing 0
actually specify valid bases that should be treated just as normal.
The PCI specifications have no indication that 0 would be a magic value
indicating a disabled BAR as commonly used on at least amd64 and i386
but not sparc64. It's unclear what to do in pci_delete_resource()
instead of writing 0 to a BAR though as there's no (other) way do
disable individual BARs so its decoding is left enabled in case of
__PCI_BAR_ZERO_VALID for now.

Approved by: re (kib), jhb
MFC after: 1 week

Enable MSI in the MSI capability registers any time that the first message
in an MSI group is enabled, not just if the address/data pair are not
initialized.

Reported by: rnoland
MFC after: 1 week

Import ACPICA 20090521.

Include <machine/stdarg.h> for va_*(). I'm not sure how this compiled
on amd64 without this.

Add an internal pci_printf() routine similar to device_printf() except
that it prefixes the output with 'pci<domain>:<bus>:<device>:<function>: '.

Revert junk from last commit. These are WIP and not ready (and don't
match the description of the last commit).

We no longer need to use d_thread_t, migrate to struct thread *.

- Consolidate duplicated code for reading and sizing BARs and writing base
addresses to BARs into new pci_read_bar() and pci_write_bar() routines.
pci_add_map(), pci_alloc_map(), and pci_delete_resource() now use these
routines to work with BARs.
- Just pass the device_t for the new PCI device to various routines instead
of passing the device, bus, slot, and function.

Reviewed by: imp

- Fix spacing in the comment.

Reported by: jhb

- Correct the comment.

MFC after: 3 days

Fix a buglet in revision 189401: when restoring a 64-bit BAR,
write the upper 32-bits in the adjacent bar. The consequences
of the buglet were severe enough though: a machine check.

Invert the logic error for the MSI/MSIX vs INTx case.

Pointyhat to: me

MFC after: 3 days

Always read/write the full 64-bit value of 64-bit BARs. Specifically,
when determining the size of a BAR by writing all 1's to the BAR and
reading back the result, always operate on the full 64-bit size.

Reviewed by: imp
MFC after: 1 month

Honor the prefetchable flag in memory BARs by setting the RF_PREFETCHABLE
flag when calling bus_alloc_resource() to allocate resources from a parent
PCI bridge. For PCI-PCI bridges this asks the bridge to satisfy the
request using the prefetchable memory range rather than the normal
memory range.

Reviewed by: imp
Reported by: scottl
MFC after: 1 week

Extend the management of PCIM_CMD_INTxDIS.

We now explicitly enable INTx during bus_setup_intr() if it is needed.
Several of the ata drivers were managing this bit internally. This is
better handled in pci and it should work for all drivers now.

We also mask INTx during bus_teardown_intr() by setting this bit.

Reviewed by: jhb
MFC after: 3 days

Further refine the handling of resources for BARs in the PCI bus driver.

A while back, Warner changed the PCI bus code to reserve resources when
enumerating devices and simply give devices the previously allocated
resources when they call bus_alloc_resource(). This ensures that address
ranges being decoded by a BAR are always allocated in the nexus0 device
(or whatever device the PCI bus gets its address space from) even if a
device driver is not attached to the device. This patch extends this
behavior further:
- To let the PCI bus distinguish between a resource being allocated by
a device driver vs. merely being allocated by the bus, use
rman_set_device() to assign the device to the bus when it is owned
by the bus and to the child device when it is allocated by the child
device's driver. We can now prevent a device driver from allocating
the same device twice. Doing so could result in odd things like
allocating duplicate virtual memory to map the resource on some
archs and leaking the original mapping.
- When a PCI device driver releases a resource, don't pass the request
all the way up the tree and release it in the nexus (or similar device)
since the BAR is still active and decoding. Otherwise, another device
could later allocate the same range even though it is still in use.
Instead, deactivate the resource and assign it back to the PCI bus
using rman_set_device().
- pci_delete_resource() will actually completely free a BAR including
attemping to disable it.
- Disable BAR decoding via the command register when sizing a BAR in
pci_alloc_map() which is used to allocate resources for a BAR when
the BIOS/firmware did not assign a usable resource range during boot.
This mirrors an earlier fix to pci_add_map() which is used when to
size BARs during boot.
- Move the activation of I/O decoding in the PCI command register into
pci_activate_resource() instead of doing it in pci_alloc_resource().
Previously we could actually enable decoding before a BAR was
initialized via pci_alloc_map().

Glanced at by: bsdimp

Disable INTx when enabling MSI/MSIX

This addresses interrupt storms that were noticed after enabling MSI
in drm. I think this is due to a loose interpretation of the PCI 2.3
spec, which states that a function using MSI is prohibitted from using
INTx. It appears that some vendors interpretted that to mean that they
should handle it in hardware, while others felt it was the drivers
responsibility.

This fix will also likely resolve interrupt storm related issues with
devices other than drm.

Reviewed by: jhb@
MFC after: 3 days

Don't throw away upper 32-bits of the HT MSI address window. In practice
this is harmless since the address window for MSI on x86 is in the lower
4 GB.

Submitted by: mav
MFC after: 1 week

Change the probe priority for PCI and I2C generic bus modules from
numerical constants to BUS_PROBE_GENERIC.

Suggested by: jhb

Disable decoding of BARs by devices before we trash the value in the BAR
by writing all 1's to it to determine its length. This fixes issues with
MCFG on at least some machines where a trashed BAR claimed subsequent
attempts at PCI config transactions because the addresses in the MCFG
window fell in the decoding range of the BAR.

In general it is a bad idea to leave the BARs enabled while we are
frobbing with them in this manner.

Sleuthing by: tegge
MFC after: 1 week

Add ADMA, SATA and SAS mass storage subclasses reporting.

Add HDA multimedia subclass.

Add "SD host controller" subclass name.

Cope with errors from device_get_children(). These errors can happen
only in low memory situations, so the error fork of these fixes is
lightly tested, but they should do the least-wrong thing...

Submitted by: Hans Petter Selasky

Cosmetic nit.

Change -1 to 0xfffffffful since the interface returns uint32_t.

Remove the second check for a 64-bit BAR value on a 32-bit system in
pci_add_map(). First, this condition is already handled earlier in
the function. Second, as written the check would never fire as the
'start' value was overwritten with a long value (rman_get_start() returns
long) before the comparison was done.

Discussed with: imp
MFC after: 2 weeks

If the kernel fails to allocate resources for the initial value of a BAR
for a PCI device during the boot-time probe of the parent PCI bus, then
zero the BAR and clear the resource list entry for that BAR. This forces
the PCI bus driver to request a valid resource range from the parent bridge
driver when the device driver tries to allocate the BAR. Similarly, if the
initial value of a BAR is a valid range but it is > 4GB and the current OS
only has 32-bit longs, then do a full teardown of the initial value of the
BAR to force a reallocation.

Reviewed by: imp
MFC after: 1 week

SATA device on some nForce based boards could get confused if MSI is not
used but MSI to HyperTransport IRQ mapping is enabled, and would act as
if MSI is turned on, resulting in interrupt loss.

This commit will,
1. enable MSI mapping on a device only when MSI is enabled for that
device and the MSI address matches the HT mapping window.
2. enable MSI mapping on a bridge only when a downstream device is
allocated an MSI address in the mapping window

PR: kern/118842
Reviewed by: jhb
MFC after: 1 week

Relax the check for a PCI-express chipset by assuming the system is a
PCI-express chipset (and thus has functional MSI) if there are any
PCI-express devices in the system, not requiring a root port device.

With PCI-X the chipset detection has to be very conservative because there
are known systems with PCI-X devices that do not appear to have PCI-X
chipsets. However, with PCI-express I'm not sure it is possible to have
a PCI-express device in a system with a non-PCI-express chipset. If we
assume that is the case then this change is valid. It is also required
for at least some PCI-express systems that don't have any devices with
a root port capability (some ICH9 systems).

MFC after: 1 week
Reported by: jfv

Make VPD register access more robust:

- Implement timing out of VPD register access.[1]
- Fix an off-by-one error of freeing malloc'd space when checksum is invalid.
- Fix style(9) bugs, i.e., sizeof cannot be followed by space.
- Retire now obsolete 'hw.pci.enable_vpd' tunable.

Submitted by: cokane (initial revision)[1]
Reviewed by: marius (intermediate revision)
Silence from: jhb, jmg, rwatson
Tested by: cokane, jkim
MFC after: 3 days

Make the PCI code aware of PCI domains (aka PCI segments) so we can
support machines having multiple independently numbered PCI domains
and don't support reenumeration without ambiguity amongst the
devices as seen by the OS and represented by PCI location strings.
This includes introducing a function pci_find_dbsf(9) which works
like pci_find_bsf(9) but additionally takes a domain number argument
and limiting pci_find_bsf(9) to only search devices in domain 0 (the
only domain in single-domain systems). Bge(4) and ofw_pcibus(4) are
changed to use pci_find_dbsf(9) instead of pci_find_bsf(9) in order
to no longer report false positives when searching for siblings and
dupe devices in the same domain respectively.
Along with this change the sole host-PCI bridge driver converted to
actually make use of PCI domain support is uninorth(4), the others
continue to use domain 0 only for now and need to be converted as
appropriate later on.
Note that this means that the format of the location strings as used
by pciconf(8) has been changed and that consumers of <sys/pciio.h>
potentially need to be recompiled.

Suggested by: jhb
Reviewed by: grehan, jhb, marcel
Approved by: re (kensmith), jhb (PCI maintainer hat)

In pci_alloc_map(), restore the original value of the BAR for
the duration of the function. The device we would otherwise
have left in an useless state may just as well be the low-level
console. When booting verbose, we do need it addressable if we
want to avoid a MCA.

Approved by: re (kensmith)

Don't completely skip pci_cfg_save() in the PCI nomatch routine if
the power_nodriver tunable is off. pci_cfg_save() already checks the
tunable internally, and no other callers of pci_cfg_save() check the
tunable.

Reviewed by: imp

Fix a typo in a bootverbose printf.

MFC after: 3 days
Submitted by: yongari

Revamp the MSI/MSI-X code a bit to achieve two main goals:
- Simplify the amount of work that has be done for each architecture by
pushing more of the truly MI code down into the PCI bus driver.
- Don't bind MSI-X indicies to IRQs so that we can allow a driver to map
multiple MSI-X messages into a single IRQ when handling a message
shortage.

The changes include:
- Add a new pcib_if method: PCIB_MAP_MSI() which is called by the PCI bus
to calculate the address and data values for a given MSI/MSI-X IRQ.
The x86 nexus drivers map this into a call to a new 'msi_map()' function
in msi.c that does the mapping.
- Retire the pcib_if method PCIB_REMAP_MSIX() and remove the 'index'
parameter from PCIB_ALLOC_MSIX(). MD code no longer has any knowledge
of the MSI-X index for a given MSI-X IRQ.
- The PCI bus driver now stores more MSI-X state in a child's ivars.
Specifically, it now stores an array of IRQs (called "message vectors" in
the code) that have associated address and data values, and a small
virtual version of the MSI-X table that specifies the message vector
that a given MSI-X table entry uses. Sparse mappings are permitted in
the virtual table.
- The PCI bus driver now configures the MSI and MSI-X address/data
registers directly via custom bus_setup_intr() and bus_teardown_intr()
methods. pci_setup_intr() invokes PCIB_MAP_MSI() to determine the
address and data values for a given message as needed. The MD code
no longer has to call back down into the PCI bus code to set these
values from the nexus' bus_setup_intr() handler.
- The PCI bus code provides a callout (pci_remap_msi_irq()) that the MD
code can call to force the PCI bus to re-invoke PCIB_MAP_MSI() to get
new values of the address and data fields for a given IRQ. The x86
MSI code uses this when an MSI IRQ is moved to a different CPU, requiring
a new value of the 'address' field.
- The x86 MSI psuedo-driver loses a lot of code, and in fact the separate
MSI/MSI-X pseudo-PICs are collapsed down into a single MSI PIC driver
since the only remaining diff between the two is a substring in a
bootverbose printf.
- The PCI bus driver will now restore MSI-X state (including programming
entries in the MSI-X table) on device resume.
- The interface for pci_remap_msix() has changed. Instead of accepting
indices for the allocated vectors, it accepts a mini-virtual table
(with a new length parameter). This table is an array of u_ints, where
each value specifies which allocated message vector to use for the
corresponding MSI-X message. A vector of 0 forces a message to not
have an associated IRQ. The device may choose to only use some of the
IRQs assigned, in which case the unused IRQs must be at the "end" and
will be released back to the system. This allows a driver to use the
same remap table for different shortage values. For example, if a driver
wants 4 messages, it can use the same remap table (which only uses the
first two messages) for the cases when it only gets 2 or 3 messages and
in the latter case the PCI bus will release the 3rd IRQ back to the
system.

MFC after: 1 month

Use more specific local variable pointers to narrow some expressions.

MFC after: 1 week

- HT 2.00b added a new flag to the MSI mapping HT capability to indicate
that the MSI mapping window is fixed at 0xfee00000 and the capability
does not include two more dwords used to program the address. Supporting
this mostly results in quieting spurious warnings during boot about
non-default MSI mapping windows.
- HT 2.00b also added a new HT capability type, so support that in pciconf.

MFC after: 3 days
Tested by: jmg

Add constants for the fields in a BAR. Also, add two new macros
PCI_BAR_(IO|MEM)() that return true if the passed in value from a BAR
is for an IO or memory BAR, respectively.

Reviewed by: imp

- Add missing constants for subclasses.
- Add a few progif constants as well.

Change the VPD code to read the VPD data on-demand when a driver asks for
it via pci_get_vpd_*() rather than always reading it for each device during
boot. I've left the tunable so that it can still be turned off if a device
driver causes a lockup via a query to a broken device, but devices whose
drivers do not use VPD (the vast majority) should no longer result in
lockups during boot, and most folks should not need to tweak the tunable
now.

Tested on: bge(4)
Silence from: jmg

- Use constants for VPD capability register offsets.
- Add missing ()'s around return values.

Add support for chipsets that has NULL'd BAR's for legacy ports.
This allows DMA to be used on a fine little geode system I got here and
most like on lots of older systems like that.

HW donated by: Paul Ghering

Adjust the global MSI blacklisting strategy so we don't have to explicitly
blacklist a bunch of old chipsets. If a system contains a PCI-PCI bridge
that supports PCI-X, assume the chipset supports PCI-X. If a system
contains a PCI-express root port, assume the chipset supports PCI-express.
If the chipset doesn't support either PCI-X or PCI-express, then blacklist
it by default. We should now only need to explicitly blacklist PCI-X or
PCI-express chipsets that don't properly handle MSI.

- Fix an off by one error in pci_remap_msix_method() that effectively
broke the method as all the MSI-X table indices were off by one in
the backend MD code.
- Fix a cosmetic nit in the bootverbose printf in pci_alloc_msix_method().

Add missing 'break' that in this case is harmless.

As VPD support still causes hard hangs on boot with some hardware, add a
tunable allowing automatic parsing of VPD data to be disabled. The
default is left as-is; if you are having problems with hard hangs at boot
due to VPD, try setting hw.pci.enable_vpd=0. A proper architectural
solution has been under discussion for some time, but this allows me to
boot my test machines in the mean time.

Submitted by: bz
Head nod: jmg

Expand the MSI/MSI-X API to address some deficiencies in the MSI-X support.
- First off, device drivers really do need to know if they are allocating
MSI or MSI-X messages. MSI requires allocating powerof2() messages for
example where MSI-X does not. To address this, split out the MSI-X
support from pci_msi_count() and pci_alloc_msi() into new driver-visible
functions pci_msix_count() and pci_alloc_msix(). As a result,
pci_msi_count() now just returns a count of the max supported MSI
messages for the device, and pci_alloc_msi() only tries to allocate MSI
messages. To get a count of the max supported MSI-X messages, use
pci_msix_count(). To allocate MSI-X messages, use pci_alloc_msix().
pci_release_msi() still handles both MSI and MSI-X messages, however.
As a result of this change, drivers using the existing API will only
use MSI messages and will no longer try to use MSI-X messages.
- Because MSI-X allows for each message to have its own data and address
values (and thus does not require all of the messages to have their
MD vectors allocated as a group), some devices allow for "sparse" use
of MSI-X message slots. For example, if a device supports 8 messages
but the OS is only able to allocate 2 messages, the device may make the
best use of 2 IRQs if it enables the messages at slots 1 and 4 rather
than default of using the first N slots (or indicies) at 1 and 2. To
support this, add a new pci_remap_msix() function that a driver may call
after a successful pci_alloc_msix() (but before allocating any of the
SYS_RES_IRQ resources) to allow the allocated IRQ resources to be
assigned to different message indices. For example, from the earlier
example, after pci_alloc_msix() returned a value of 2, the driver would
call pci_remap_msix() passing in array of integers { 1, 4 } as the
new message indices to use. The rid's for the SYS_RES_IRQ resources
will always match the message indices. Thus, after the call to
pci_remap_msix() the driver would be able to access the first message
in slot 1 at SYS_RES_IRQ rid 1, and the second message at slot 4 at
SYS_RES_IRQ rid 4. Note that the message slots/indices are 1-based
rather than 0-based so that they will always correspond to the rid
values (SYS_RES_IRQ rid 0 is reserved for the legacy INTx interrupt).
To support this API, a new PCIB_REMAP_MSIX() method was added to the
pcib interface to change the message index for a single IRQ.

Tested by: scottl

Disable MSI for the Intel 845 and 865 chipsets and update comment for
E7210 to note it is the same devid as the 875 chipset.

Fix the subvendor ID for PCI-PCI bridges.
- Retire the PCI_SUB*_1 constants and don't try to read a subvendor ID out
of them. There isn't a standard subvendor ID field for PCI-PCI bridges.
Instead, the dword at offset 0x34 is actually mostly reserved except for
the LSB which is the capabilities pointer.
- Add support for the PCI-PCI bridge subvendor ID capability (13) and use
it to set the subvendor ID for PCI-PCI bridges.

MFC after: 1 month

- Add a new flag to the PCI-PCI driver to disable MSI on devices behind the
bridge if it doesn't pass MSI messages up correctly. We set the flag
in pcib_attach() if the device ID is disabled via a PCI quirk.
- Disable MSI for devices behind the AMD 8131 HT-PCIX bridge. Linux has
the same quirk.

Tested by: no one despite repeated calls for testers

Disable MSI for two ServerWorks chipsets. The first is based on a user
report. The second is blacklisted in Linux.

Blacklist a few more Intel chipsets re: MSI based on user reports:
E7500 and 855.

- Condense the comment for Intel chipset MSI blacklist entries.
- Blacklist the E7210.

PR: kern/105768 (2)
Reported by: marcus (2)

Disable MSI on the Intel E7505 chipset. It is reported broken on a Tyan
S2665ANF motherboard.

Reported by: "Eugene M. Kim" <blue at white lv>

Disable MSI for the Intel E7501 chipset.

Reported by: jdp

Add a first pass at a way to blacklist MSI on systems where it doesn't
work:
- A new PCI quirk (PCI_QUIRK_DISABLE_MSI) is added to the quirk table.
- A new pci_msi_device_blacklisted() determines if a passed in device
matches an MSI quirk in the quirk table. This can be overridden (all
quirks ignored) by setting the hw.pci.honor_msi_blacklist to 0.
- A global blacklist check is performed in the MI PCI bus code by checking
to see if the device at 0:0:0 is blacklisted.

Tested by: jdp

Replace #define<space> with #define<tab> so the code is consistent with
style(9) and avoids mixing the two formats.

- Add constants for HT PCI capability registers including the various
subtypes of HT capabilities.
- Add constants for the MSI mapping window HT PCI capability.
- On i386 and amd64, enable the MSI mapping window on any HT bridges we
encounter and report any non-standard mapping window addresses.

Give the WREG() macro the same lifetime as the REG() macro.

Add some bootverbose printf's to detail how many MSI messages are allocated
and to which IRQs.

Requested by: scottl

don't mark the cksum as invalid here... off is incorrect when we get
here, it's either unset, or it's valid, so we don't need to do anything
different...

Reported by: Neterion (via rwatson)

Look for capabilities in PCI-PCI bridges using the same CAP PTR register
as for type 0 devices.

Submitted by: grehan
MFC after: 1 week

First cut at MI support for PCI Message Signalled Interrupts (MSI):
- Add 3 new functions to the pci_if interface along with suitable wrappers
to provide the device driver visible API:
- pci_alloc_msi(dev, int *count) backed by PCI_ALLOC_MSI(). '*count'
here is an in and out parameter. The driver stores the desired number
of messages in '*count' before calling the function. On success,
'*count' holds the number of messages allocated to the device. Also on
success, the driver can access the messages as SYS_RES_IRQ resources
starting at rid 1. Note that the legacy INTx interrupt resource will
not be available when using MSI. Note that this function will allocate
either MSI or MSI-X messages depending on the devices capabilities and
the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. Also note
that the driver should activate the memory resource that holds the
MSI-X table and pending bit array (PBA) before calling this function
if the device supports MSI-X.
- pci_release_msi(dev) backed by PCI_RELEASE_MSI(). This function
releases the messages allocated for this device. All of the
SYS_RES_IRQ resources need to be released for this function to succeed.
- pci_msi_count(dev) backed by PCI_MSI_COUNT(). This function returns
the maximum number of MSI or MSI-X messages supported by this device.
MSI-X is preferred if present, but this function will honor the
'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. This function
should return the largest value that pci_alloc_msi() can return
(assuming the MD code is able to allocate sufficient backing resources
for all of the messages).
- Add default implementations for these 3 methods to the pci_driver generic
PCI bus driver. (The various other PCI bus drivers such as for ACPI and
OFW will inherit these default implementations.) This default
implementation depends on 4 new pcib_if methods that bubble up through
the PCI bridges to the MD code to allocate IRQ values and perform any
needed MD setup code needed:
- PCIB_ALLOC_MSI() attempts to allocate a group of MSI messages.
- PCIB_RELEASE_MSI() releases a group of MSI messages.
- PCIB_ALLOC_MSIX() attempts to allocate a single MSI-X message.
- PCIB_RELEASE_MSIX() releases a single MSI-X message.
- Add default implementations for these 4 methods that just pass the
request up to the parent bus's parent bridge driver and use the
default implementation in the various MI PCI bridge drivers.
- Add MI functions for use by MD code when managing MSI and MSI-X
interrupts:
- pci_enable_msi(dev, address, data) programs the MSI capability address
and data registers for a group of MSI messages
- pci_enable_msix(dev, index, address, data) initializes a single MSI-X
message in the MSI-X table
- pci_mask_msix(dev, index) masks a single MSI-X message
- pci_unmask_msix(dev, index) unmasks a single MSI-X message
- pci_pending_msix(dev, index) returns true if the specified MSI-X
message is currently pending
- Save the MSI capability address and data registers in the pci_cfgreg
block in a PCI devices ivars and restore the values when a device is
resumed. Note that the MSI-X table is not currently restored during
resume.
- Add constants for MSI-X register offsets and fields.
- Record interesting data about any MSI-X capability blocks we come
across in the pci_cfgreg block in the ivars for PCI devices.

Tested on: em (i386, MSI), bce (amd64/i386, MSI), mpt (amd64, MSI-X)
Reviewed by: scottl, grehan, jfv
MFC after: 2 months

fix hanging on invalid data... (This doesn't fix hanging due to broken
hardware)...

Tested by: Ian Dowse, Adam K Kirchhoff and Vladimir Kushnir

Various whitespace cleanups.

Doh! Actually commit checking against NULL for res.

Noticed by: dougb@

Assign start to the value we were able to allocate and use that to
write out the BAR. Otherwise, we were trying to shift a 32-bit
quantity on 32-bit platforms. Also, 'start' check sanity to where it
is known.

More fully support 64-bit bars. Prior to this commit, we supported
only those bars that had addresses assigned by the BIOS and where the
bridges were properly programmed. Now even unprogrammed ones work.
This was needed for sun4v. We still only implement up to 2GB memory
ranges, even for 64-bit bars. PCI standards at least through 2.2 say
that this is the max (or 1GB is, I only know it is < 32bits).

o Always define pci_addr_t as uint64_t. A pci address is always 64-bits,
but some hosts can't address all of them.
o Preserve the upper half of the 64-bit word during resource probing.
o Test to make sure that 64-bit values can fit in a u_long (true on some
platforms, but not others). Don't use those that can't.
o minor pedantry about data sizes.
o Better bridge resource reporting in bootverbose case.
o Minor formatting changes to cope with different data types on different
platforms.

Submitted by: jmg, with many changes by me to fully support 64-bit
addresses.

fix tab indentation for CP and RV...

If the length is zero, catch this early, instead of making dflen go negative
and letting bad things happen... We also check to see if RV (checksum) is
0, and handle that has a checksum failure...

Properly handle checksum failures by not processing read-write VPD data,
and removing all the found read-only data...

Tested by: oleg (dflen going negative)

provide routines to access VPD data at the PCI layer...

remove sk's own implementation, and use the new calls to get the data...

Reviewed by: -arch

spell PCIS_CRYPTO_ENTERTAIN properly...

MFC after: 3 days

Simplify the pager support in DDB. Allowing different db commands to
install custom pager functions didn't actually happen in practice (they
all just used the simple pager and passed in a local quit pointer). So,
just hardcode the simple pager as the only pager and make it set a global
db_pager_quit flag that db commands can check when the user hits 'q' (or a
suitable variant) at the pager prompt. Also, now that it's easy to do so,
enable paging by default for all ddb commands. Any command that wishes to
honor the quit flag can do so by checking db_pager_quit. Note that the
pager can also be effectively disabled by setting $lines to 0.

Other fixes:
- 'show idt' on i386 and pc98 now actually checks the quit flag and
terminates early.
- 'show intr' now actually checks the quit flag and terminates early.

Fixup some comments to allow for the fact that PCI domains are not specific
to Alpha hoses.

The size of I/O ranges can be anything from 16 bytes to 2G bytes.
Lower the minimum for memory mapped I/O from 32 bytes to 16 bytes.
This fixes bus enumeration on ia64 now that the Diva auxiliary
serial port is attached to.

Make the 'pci_devclass' pointer variable private (drivers really shouldn't
share devclass pointers, a mistake I've encouraged in the past) and
move the declaration of the pci_driver kobj class from cardbus.c to
pci_private.h so that other drivers can inherit from pci_driver.

Use __HAVE_ACPI and __PCI_REROUTE_INTERRUPT as appropriate rather than
the complicated #ifdefs.

Remove stray debug from p4 integration.

Remove debug now that I've looped back the big changes into my p4 tree.

Expose pci_add_resources to the outside world, add a 'force' flag to
force allocation of unallocated BARs (cardbus uses this to preallocate
everything). Add a prefetchmask to allow for busses that get prefetch
hints to set them. Addjust pci_add_map and pci_ata_maps to take a new
force flag which pci_add_resources will pass in. Implement 'force' in
pci_add_map. Write new value of allocated resource into the bar, if
the allocation succeeded (we should have done this before, but with
the new force the bug was very obvious).

Add a new method PCI_FIND_EXTCAP() to the pci bus interface that is used
to search for a specific extended capability. If the specified capability
is found for the given device, then the function returns success and
optionally returns the offset of that capability. If the capability is
not found, the function returns an error.

Improve diagnostic message.

MFp4: When doing lazy allocation, it turns out that we need to record the
actual resource values we received from the system rather than the range
we requested. Since we request a range starting at 0, we would record
that number. Later, since this == 0, we'd allocate again. However,
we wouldn't write the new resource into the BAR. This resulted in
a resource leak as well as a BAR that couldn't access the resource at
all since rman_get_start, et al, were wrong.

MFC After: 1 week (assuming RELENG_6 is open for business)

Use symbolic name rather thanhard coding the cap pointer offset for
type two devices.

Minor style(9) nitage.

Add a 1 microsecond delay in pci_add_children(), right before the read
of the PCIR_HDRTYPE register. It's the value returned from this
read access that determines whether or not we decide a device is
present at the current slot index. For some reason that I can't
adequately explain, this read fails on my machine when probing the
USB controller on my machine (which happens a multifunction device
at slot index 3 hung off the PCI-PCI bridge on the AMD8111 (bus
index 1)). The read will return 0xFF even though it should return
0x80 to indicate the presence of a multifunction device.

As near as I can tell, there's some timing issue involved with reading
the 'dead' slot indexes 0 through 2 that causes the read of the actual
device at slot 3 to fail. I tried a couple of different tricks to
correct the problem (the patch to amd64/pci/pci_cfgreg.c fixes it
for the amd64 arch), but adding this delay is the only thing that
always allows the USB controllers to be correctly probed 100% of the
time. Whatever the problem is, it's likely confined to the AMD8111
chipset. However, a simple 1us delay is fairly harmless and should
have no side effects for other hardware. I consider this to be
voodoo, but it's fairly benign voodoo and it makes my USB keyboard
and mouse work again.

Note that this is the second time that I've had to resort to a
1us delay to fix a PCI-related problem with this AMD8111/Opteron
system (the first being a fix I made a while back to the NDISulator).
It's possible the delay really belongs in the cfgreg code itself,
or that pci_cfgreg needs some custom hackery for an errata in the
8111. (I checked but couldn't find any documented errata on AMD's
site that could account for these problems.)

- Consolidate duplicated code for assigning interrupts to PCI devices via
routing, etc. in a static pci_assign_interrupt() function.
- Add a sledgehammer that allows the user to override the interrupt
assignment of any PCI device via a tunable (e.g. "hw.pci0.7.INTB=5" would
force any functions on the pci device in slot 7 of bus 0 that use B# to
use IRQ 5). This should be used with great caution! Generally, if the
interrupt routing in use provides specific tunables (such as hard-wiring
the IRQ for a given $PIR or ACPI PCI link device), then those should be
used instead. One instance where this tunable might be useful is if a
box has an MPTable with duplicate entries for the same PCI device with
different IRQs.

MFC after: 1 week

Split power state control into two variables. hw.pci.do_powerstate
has been removed. It has been replaced by hw.pci.do_power_nodriver
and hw.pci.do_power_resume. The former defaults to 0 while the latter
defaults to 1.

When do_powerstate was set to 0, it broke suspend/resume for a lot of
people as an unintended consequence. This change will only affect the
areas that were intended to affect. This change will have no effect on
servers, but will help laptops quite a bit.

MFC After: 3 days.

Change hw.pci.do_powerstate from a boolean to a range. 0 means the
same as today: do no power management. 1 means be conservative about
what you power down (any device class that has caused problems gets
added here). 2 means be agressive about what gets powered down (any
device class that's fundamental to the system is here). 3 means power
them all down, reguardless. The default is 1.

The effect in the default system is to add mass storage devices to the
list that we don't power down. From all the pciconf -l lists that
I've seen for the aac and amr issue, the bad device has been a mass
storage device class.

This is an attempt at a compromise between the very small number of
systems that have extreme issues with powerdown, and the very large
number of systems that gain real benefits from powerdown (I get about
20% more battery life when I attach a minimal set of drivers on my
Sony). Hopefully it will strike the proper balance.

MFC After: 3 days (before next beta)

Allow one to access the cached values for CMDREG, CACHELNSZ, MINGNT,
MAXLAT and LATTIMER.

Improve error message when a bogus RID type is requested for a bar.

More consistantly return the correct BAR size. Before, we'd only
return the correct bar size if we encountered a 64-bit BAR that had
its resources already assigned. If the resources weren't yet
assigned, we'd bogusly assume it was a 32-bit bar and return 1.

Typo in comment.

Treat resources that are 0xfffff.... as being 'unassigned'.

Reviewed by: jhb
Tested by: Mark Kirkwood
MFC After: 3 days

Mask off the bar's value after the probe test write before testing
against 0 in pci_alloc_map, just like we do in pci_add_map. Also,
make sure that we restore the value to the BAR that was there before
if the bar is 0. Chances are that it was 0 before the write too and
that the restoration is a nop, but better safe than sorry.

Notice by: dwhite

Typo.

Submitted by: njl

Don't enable I/O or memory mode in a device's command register if the BAR
we are processing has a base address of zero. Note that this will only
change behavior for devices where all the BARs of a given type have a base
address of 0 since we will enable the appropriate access when we encounter
the first BAR with a base that is not 0. Specifically, this allows certain
Toshiba laptops to no longer require 'hw.pci.enable_io_modes=0' to avoid
hangs during boot.

PR: kern/20040
PR: i386/63776 (possibly)
PR: i386/68900 (possibly)
PR: i386/74532 (possibly)
MFC after: 1 week

Add a detach for pci bridge and pci bus drivers. This allows one to
theoretically unload pci bridges or pci drivers. It will also allow
detach to work if one needed to detach a subtree.

This is inspired by looking at the p4 commits from bms to his 5.4
tree, but I didn't look at the final results.

Call pci_print_verbose() before pci_add_resources() so that the order of
printf's during a verbose boot is more intuitive (the BAR listings and
interrupt routing info now comes after the config header dump rather than
just before it).

It isn't a whinable offence to want memory when the bar says ioport.
Put that behind bootverbose to make the ata driver less chatty on
advanced hardware.

Requested by: sos

Go ahead and try to allocate PCI_BAR(5) for ata devices.

move the statement about switching power states to just before we do it, so
we don't print a false statement if the destination powerstate is
unsupported...

add some additional pci classes and sub-classes..

Reviewed by: imp (almost 6 months ago)

relocate the power state transition statements to the
pci_set_powerstate_method function...

Reviewed by: imp
MFC after: 1 week

Use STAILQ in preference to SLIST for the resources. Insert new resources
last in the list rather than first.

This makes the resouces print in the 4.x order rather than the 5.x order
(eg fdc0 at 0x3f0-0x3f5,0x3f7 is 4.x, but 0x3f7,0x3f0-0x3f5 is 5.x). This
also means that the pci code will once again print the resources in BAR
ascending order.

If bus_generic_susped returns an error, devlist is not freed. Free it.

Submitted by: Ted Unangst (using the Coverity Prevent analysis tool)

Expose pci_cfg_safe/restore for subclasses of pci to use.

kill unused variable

Noticed by: Coverity Prevent analysis tool

Enable interrupt routing as first choice on alpha.
The alpha default handler knows how to trigger a fallback.

Fix typo.

Start each of the license/copyright comments with /*-, minor shuffle of lines

Fix last second typos that crept in :-(.

Implement mimimum system software delays, per PCI PM 1.1 spec, as
suggested by Peter Edwards. This seems to fix my fxp problems and
likely will fix his as well. Use DELAY rather than *sleep because we
can be called from any context.

Fix comments to match last commit, and minor reformatting...

It turns out that a lot of newer systems have 'base peripherals' on
the PCI bus. We presently have no drivers for these devices, so they
are powered down. This is undesirable behavior since it breaks the
system when the base peripherals go away suddenly in the middle of
boot.

# if we ever get generic drivers for memory and/or base peripherals, then
# we can remove the tests here.

ACPI is not on pc98 either.

Informed by: nyan

Non-x86 platforms cannot use the ACPI includes. This should be fixed but
for now, only include the headers for i386, amd64, or ia64.

Pointed out by: grehan

Turn ACPI and PCI devices off or to a lower power state in suspend and
back on again in resume. Override the default of D3 with the value the
BIOS specifies in _SxD, if present. Skip serial devices (PNP05xx) since
they seem to hang when set to D3 and may require special driver support.
Also, skip non-type 0 PCI devices (i.e., bridges) since our we don't yet
save/restore their config space and that seems to be necessary.

If this gives you trouble with suspend/resume, you can disable the new
ACPI and PCI power behavior separately with these tunables & sysctls:
debug.acpi.do_powerstate
hw.pci.do_powerstate

Approved by: imp (pci)
Tested by: acpi@ (numerous)

Make pci_do_powerstate default to 1 now that we've done the release to
get more testing. This should help things a little.

- Change the ddb paging "support" to use a variable (db_lines_per_page) to
control the number of lines per page rather than a constant. The variable
can be examined and changed in ddb as '$lines'. Setting the variable to
0 will effectively turn off paging.
- Change db_putchar() to force out pending whitespace before outputting
newlines and carriage returns so that one can rub out content on the
current line via '\r \r' type strings.
- Change the simple pager to rub out the --More-- prompt explicitly when
the routine exits.
- Add some aliases to the simple pager to make it more compatible with
more(1): 'e' and 'j' do a single line. 'd' does half a page, and
'f' does a full page.

MFC after: 1 month
Inspired by: kris

Fix a spelling error in a panic string.

Re-route interrupts on arm as well.

Disable native ata support for now, too much breaks

Update the special handling code for ATA devices to allow usage of
PCI native addressing. That means that if the HW says that using "real"
addresses instead of the hardwired legacy compat ones is allowed, we will
use them.

Do the dreaded s/dev_t/struct cdev */
Bump __FreeBSD_version accordingly.

Use PCI_BAR() in preference to PCI_MAPS + x * 4.

Submitted by: jhb

Do not write to those config registers that are unambiguously defined
in the various pci specifications as readonly. vendor, subvendor,
device and subdevice are required to be loaded in hardware by some
means that isn't the system BIOS or other system software (although
some devices do have ways of accomplishing this). class and subclass
are defined to be read-only in section 6.2.1 (v2.2). Apart from the
status register, which we weren't touching, these are the only
read-only registers I could find in the 2.2 spec.

progif is also defined as being read-only in section 6.2.1. However,
the PCI IDE programming document specifically states that some of the
bits are read/write. Since we may have to restore registers before we
have a driver attached, go ahead and restore this one byte when
transitioning between D3 and D0.

The PCI spec also says that writes to reserved and unimplemented
registers must be completed normally. It makes no statements about
writes to read-only registers, so be as conservative as possible,
while covering the exception to the rule that is documented in a
subpart of the standard.

Requested by: socttl

Fix cutNpasto in last commit.

ifdef writing to registers that the base pci standard says are
read-only on D3->D0 power state transition. Add a define to enable
them, but include a comment to contact me if there's a problem.

Compeletely rewrite the description of hw.pci.do_powerstate to sound
better.

Improve the English somewhat.

Prodded by: ru@

Ooops, forgot to commit the updated definition for hw.pci.do_powerstate
when I committed code that changed its meaning.

MFp4:

Split the baby. For idepci devices, now both legacy mode bits need
not be set. We can run an idepci in a split mode. However, it only
works better than before, not works. It works better in that when one
device is legacy and the other isn't and disabled, we now operate
correctly.

sos submitted a version of this patch.

Move pci_do_powerstate up a level. Now it just means 'do not turn devices
off into d3 state when there's no driver for the device'. This should
help suspend/resume in the default case.

MFp4: o save/restore subvendor, subdevice, vendor, device, baseclass,
subclass, progif and revid. While these are typically read
only fields, they aren't always read-only. progif is writable
for ata devices, for example. It does no harm when they are
read only, and helps when they aren't.

make the pci power state and resource code a lot less chatty. The
chattiness was left in for debugging, but now that nearly all of the
problems relating to the changes have been fixed, it is only annoying. It
is still available via bootverbose.

Prodded by: jhb

Remove the EBus stopgap of r1.248; a proper fix is in place now.

Fix two typos from PR: 65694

1) In pci.c, we need to check the child device's state, not the parent
device's state.
2) In acpi_pci.c, we have to run the power state change after the acpi
method when the old_state is > new state, not the other way around.

Submitted by: Dmitry Remesov
PR: 65694

Add a stopgap for the EBus breakage on sparc64 since the PCI code does
resource pre-allocation. The problem is that the BARs of the EBus bridges
contain the ranges for the resources for the EBus devices beyond the bridge.
So when the EBus code tries to allocate the resource for an EBus device
it's already allocated by the PCI code.
To be removed again as soon as we have a proper solution in the EBus Code.

Reviewed by: tmm
Approved by: marcel (mentor)

ata devices in legacy are special, and we must treat them as such.
While I would have prefered to have a solution that didn't move
knowledge of this into the pci layer. However, this is literally the
only exception that's listed in the PCI standard to the usual way of
decoding BARs. atapci devices in legacy mode now ignore the first 4
bars and hard code the values to the legacy ide values (well, for each
of the controllers that are in legacy mode). The 5th bar is handled
normally.

Remove the zero bar handling. zero bars should be ignored at all
other times, and since we handle that specially, we don't need the
older workaround.

Do not pre-allocate resources for BAR's on ATA MASTERDEV's thats on
the standard ATA primary and secondary addresses.

Reintroduce the size 1 ALTIO space so that we can have both ATA and
floppies back working.

ooops. I disabled pci_enable_io_modes not pci_do_powerstate in the last
commit. That was in error.

Noticed by: sos

make the bad bar warning less scary, and toss it behind a bootverbose.
It is harmless, but freaking people out.

Turn off the power stuff for a little while longer. There appears to be
something subtle wrong with it.

Now that the dust has settled on the resource issues, turn on the
power parts of my patches and see what breaks. Don't (yet) throw
the chatty messages behind a if (bootverbose).

Some devices have what appear to be invalid BARs. They are invalid in
the sense that any write to them reads back as a 0. This presents a
problem to our resource allocation scheme. If we encounter such vars,
the code now treats them as special, allowing any allocation against
them to succeed. I've not seen anything in the standard to clearify
what host software should do when it encounters these sorts of BARs.

Also cleaned up some output while I'm here and add commmented out
bootverbose lines until I'm ready to reduce the verbosity of boot
messages.

This gets a number of south bridges and ata controllers made mostly by
VIA, AMD and nVidia working again. Thanks to Soren Schmidt for his
help in coming up with this patch.

Add system tunable to turn off power state changes. Default to off until
we get the resource allocation stuff hammered out.

Fix and off by one error that caused unnecessary filtering of valid
BARs for only 4 bytes than ICH3 and other PCI IDE controllers have.
Andrew Gallatin submitted this, although it doesn't solve the problems
ICH3 controllers have with the new code, it does restore the former
resource list on the probe line.

Only print state change message for real state changes. When we set a
device in D0 to D0, that's a no-op, however the messages seem to be
confusing some people. Eventually, these messages will be parked
behind a if (bootverbose).

# I don't think this will fix any real bugs...

Omnibus PCI commit:
o Save and restore bars for suspend/resume as well as for D3->D0
transitions.
o preallocate resources that the PCI devices use to avoid resource
conflicts
o lazy allocation of resources not allocated by the BIOS.
o set unattached drivers to state D3. Set power state to D0
before probe/attach. Right now there's two special cases
for this (display and memory devices) that need work in other
areas of the tree.

Please report any bugs to me.

Minor whitespace changes to conform better to stlye(9) and reduce diffs
with uncommitted changes I have in p4.

Initial landing of SMP support for FreeBSD/amd64.

- This is heavily derived from John Baldwin's apic/pci cleanup on i386.
- I have completely rewritten or drastically cleaned up some other parts.
(in particular, bootstrap)
- This is still a WIP. It seems that there are some highly bogus bioses
on nVidia nForce3-150 boards. I can't stress how broken these boards
are. I have a workaround in mind, but right now the Asus SK8N is broken.
The Gigabyte K8NPro (nVidia based) is also mind-numbingly hosed.
- Most of my testing has been with SCHED_ULE. SCHED_4BSD works.
- the apic and acpi components are 'standard'.
- If you have an nVidia nForce3-150 board, you are stuck with 'device
atpic' in addition, because they somehow managed to forget to connect the
8254 timer to the apic, even though its in the same silicon! ARGH!
This directly violates the ACPI spec.

Enable PCI interrupt routing for i386 SMP kernels.

Make the cardbus driver a derived class of the pci driver. In theory, this
should allow many of the pci methods to be re-staticised.

Add pci_resume() to reestablish interrupt routing after
suspend/resume.
Especially after hibernation, interrupt routing went back to initial
status on some machines.

Teach the PCI code to parse MSI extended capabilities. Re-arrange the
pcicfg struct a bit to hold extcap structures instead of structure members.

Remove most of the magic constants from the extcap parsing code.

Replace another instance of PCIR_MAPS with PCIR_BAR(x).

Reminded by: dfr

Use PCIR_BAR(x) instead of PCIR_MAPS.

Glanced over by: imp, gibbs
Tested by: i386 LINT

Don't try to enable io or memory access for non-standard resource
addresses. This stops resource allocations for e.g. amdpm failing - this
has its own special ways of enabling access.

- Rename PCIx_HEADERTYPE* to PCIx_HDRTYPE* so the constants aren't so long.
- Add a new PCIM_HDRTYPE constant for the field in PCIR_HDRTYPE that holds
the header type.
- Replace several magic numbers with appropriate constants for the header
type register and a couple of PCI_FUNCMAX.
- Merge to amd64 the fix to the i386 bridge code to skip devices with
unknown header types.

Requested by: imp (1, 2)

Prefer the uintXX_t to the u_intXX_t names.

Define PCI_MAXHDRTYPE to be 2. We know about header types 0, 1 and 2.
Update the MI device scanning code to use PCI_MAXHDRTYPE rather than
the hard coded 2.

Update the 'ps', 'show pci', and 'show ktr' ddb commands to use the new
pager callout instead of homerolling their own paging facility.

Add a new PCI interface method, assign_interrupt, to determine the
interrupt to be used for a device. This is intended solely for internal
use of PCI bus implementations, and exists so that PCI bus drivers
implementing special interrupt assignment methods which require
additional work at the bus level to work right can be easily derived
from the generic driver (or any other one) without resorting to hacks.

It will be used in the sparc64 ofw_pcibus driver, which will be
committed shortly.

Make use of this method in the generic implementation, and add it to
the method table of bus drivers derived from the PCI one.

Reviewed by: imp, -hackers

Allow to write the intpin ivar using the pci_set_intpin() accessor. There
are some Sun PCI devices around which bogusly set intpin to 0, although
they use the intline mechanism; this allows the device driver to correct
that.

Reviewed by: imp

Re-enabled PCI irq routing on pc98.

use a REG macro that was already defined.

Reorder how the pci probing in handled. before adding devices, check to
see if the slot is a multi-function device to see if we should probe all
the functions.

Original idea by: imp

When we re-route a PCI interrupt, write the new IRQ value into the intline
register.

Reviewed by: imp

Don't route PCI irq on pc98.

- Adjust the comment about re-routing PCI interrupts to be less
ia64-specific.
- When trying to re-route interrupts, don't change cfg->intline if the
re-route fails by returning an invalid vector. This fixes machines
without any way of routing interrupts such as older PC's without a
$PIR table.

We do not currently write the new intline value back to the hardware, but
we should. That will likely be added in a later commit.

Batton down the hatches!!!

Always route PCI interrupts on i386 UP machines. I was planning to enable
this for i386 anyways once SMP support is done. Having this enabled fixes
problems on many people's laptops.

Requested by: imp

Remove unused variable(s).
Remove break after return;

Found by: FlexeLint

Return status for PCI methods '{enable,disable}_{io,busmaster}'.

Reviewed by: imp

When the driver allocates memory or I/O ports, enable that bit in the
command config register. At the present, this represents a nop
because these bits should have been set earlier in the process. In
the future, we'll only set these bits when the driver requests the
resource, not when the bus code detects the resource.

Reviewed by: mdodd

Back out M_* changes, per decision of the TRB.

Approved by: trb

Include class designation in pnpinfo for generic driver loading

Move the pnp and location info into the common pci bus. Make all known
pci busses implement this.

Also minor comment smithing in cardbus. Fix copyright to this year
with my name on it since I've been doing a lot to this file.

Reviewed by: jhb

These don't need to be semi-public after all.

Use rman_get_device rather than rle->resl->r_dev.
make pci_hdrtypedata and pci_read_extcap accessible (but maybe in the end
we'll make them private again).

Remove M_TRYWAIT/M_WAITOK/M_WAIT. Callers should use 0.
Merge M_NOWAIT/M_DONTWAIT into a single flag M_NOWAIT.

Add a new cardbus specific ivar: PCI_IVAR_ETHADDR. Some pci-like
buses support querying the MAC address in a standard-for-that-bus way.
The base pci bus returns NULL for this IVAR always.

Submitted by: sam
Approved by: re (blanket for NEWCARD)

Staticize local variable.

Submitted by: Hiten Pandya <hiten@angelica.unixdaemons.com>
Obtained from: re (murray)

Whitespace.

Removed the only PCI_DEBUG ifdef in the kernel. PCI_DEBUG was not a
supported option and it disabled a whole 2 lines of bootverbose messages.
I wanted to see 1 of the messages (about the latency timers). This
is a wrong place to decode pci configurations, but the code is already
here and handles more details than pciconf(8).

The bus number is unsigned, it cannot be less than zero.

Found by: FlexeLint

Don't use GCC shorthand for ?: unless it really matters.

Fix up a comment.

- Make pci_load_vendor_data() static and do it during MOD_LOAD instead of
when the first PCI bus attaches.
- Create /dev/pci during MOD_LOAD as well.
- Destroy /dev/pci during MOD_UNLOAD (not that you can kldunload pci, but
might as well get the code right)

Add a new command: show pciregs, equivalent to pciconf -l

Reviewed by: Doug Rabson (quite some time ago)
MFC after: 1 week

Overhaul the ACPI PCI bridge driver a bit:
- Add an ACPI PCI-PCI bridge driver (the previous driver just handled
Host-PCI bridges) that is a PCI driver that is a subclass of the generic
PCI-PCI bridge driver. It overrides probe, attach, read_ivar, and
pci_route_interrupt.
- The probe routine only succeeds if our parent is an ACPI PCI bus which
we test for by seeing if we can read our ACPI_HANDLE as an ivar.
- The attach routine saves a copy of our handle and calls the new
acpi_pcib_attach_common() function described below.
- The read_ivar routine handles normal PCI-PCI bridge ivars and adds an
ivar to return the ACPI_HANDLE of the bus this bridge represents.
- The route_interrupt routine fetches the _PRT (PCI Interrupt Routing
Table) from the bridge device's softc and passes it off to
acpi_pcib_route_interrupt() to route the interrupt.
- Split the old ACPI Host-PCI bridge driver into two pieces. Part of
the attach routine and most of the route_interrupt routine remain in
acpi_pcib.c and are shared by both ACPI PCI bridge drivers.
- The attach routine verifies the PCI bridge is present, reads in
the _PRT for the bridge, and attaches the child PCI bus.
- The route_interrupt routine uses the passed in _PRT to route a PCI
interrupt.
The rest of the driver is the ACPI Host-PCI bridge specific bits that
live in acpi_pcib_acpi.c.
- We no longer duplicate pcib_maxslots but use it directly.
- The driver now uses the pcib devclass instead of its own devclass.
This means that PCI busses are now only children of pcib devices.
- Allow the ACPI_HANDLE for the child PCI bus to be read as an ivar
of the child bus.
- Fetch the _PRT for routing PCI interrupts directly from our softc
instead of walking the devclass to find ourself and then fetch our
own softc.

With this change and the new ACPI PCI bus driver, ACPI can now properly
route interrupts for devices behind PCI-PCI bridges. That is, the
Itanium2 with like 10 PCI busses can now boot ok and route all the PCI
interrupts. Hopefully this will also fix problems people are having with
CardBus bridges behind PCI-PCI bridges not properly routing interrupts
when ACPI is used.

Tested on: i386, ia64

Various changes to make it easier to subclass the PCI bus device.
- Make the pci devclass a global variable.
- Add child devices in pci_attach() instead of pci_probe(). Change
pci_probe() to just check for a valid bus number from the associated
bridge and return -1000 if successful. This allows subclasses of the
PCI bus driver to override the generic driver.
- Move the code to load the vendor data into its own public function.
Really though, doing this at attach is just plain wrong. This should
really be done in the module load routine instead. As a side effect,
the 'busno' variable in pci_attach() is now no longer static (minor
bug that was harmless so far.)
- Change pci_add_children() to take an extra argument that is the size of
the device info structure passed to pci_read_device() and make it public
so subclasses of the PCI bus can call it in their attach routines.
- Move the bits to attach a probed PCI child to a PCI bus into a global
pci_add_child() function. This will allow subclasses that can detect
a PCI device not found in the normal PCI probe to add those devices in
their own attach routine. (I have seen this in the ACPI tree on my
laptop for example.) As a side effect, change the static function
pci_add_resources() to get the busno, slot, and func from the passed
in dinfo structure instead of requiring them as function arguments.

Tested on: i386, alpha, ia64, sparc64

While PCI interrupts are shareable, this should not have been committed just
yet.

Make PCI_ENABLE_IO_MODES a sysctl hw.pci.enable_io_modes. It can also
be set at boot time. It defaults to 1 now since it can be set in the
boot loader. If this proves unwise, we can reset it to defaulting to 0.

Use PCI_INTERRUPT_VALI in stead of hard coded 255

More style(9) nits

Make this file mostly conform to style(9).

Approved by: msmith in principle before walkabout

Add MODULE_VERSION.

intline == 0 is not a valid intline on 386. See pci_cfgintr() in
sys/i386/pci/pci_cfgreg.c.

This should resolve some cases where adding USB support to the kernel
produced an interrupt storm.

Add 5th parameter to pci_read_device specifying the size of the object
to create.

Use the pci.c code wherever possible, rather than copying all the pci
code into cardbus and s/pci/cardbus. This exposes a few pci_*
functions that are now static.

This work is similar to work Justin posted to the mobile list about a
year or two ago, which I have neglected since then.

This is a subset of his current work with the multiple inheritance
newbus architecutre. When completed, that will eliminate the need for
pci/pci_private.h.

Similar work is needed for the cardbus_cis and pccard_cis code as well.

Implement 2 small helper functions:
pci_find_bsf() - Find a device_t by bus/slot/function.
pci_find_device() - Find a device_t by vendor/device ID.

Use the new resource_list_print_type() function to print resource list
contents, and the new __BUS_ACCESSOR macro to construct the accessor
functions.

Add support for the Intel 82443MX chipset

PR: kern/33032
MFC after: 1 month

Don't put variable declarations in header files, put prototypes.

'pci_devq' provides useful information now.

Add PCI_ENABLE_IO_MODES option, for BIOSen that neglect this.

Submitted by: Andrew R. Reiter arr@watson.org

Re-route interrupts on ia64 so that we can get the I/O SAPIC interrupt
numbers (the BIOS leaves legacy PIC interrupt numbers in the intline
registers).

Small nit: Make both prints use 'at device %d.%d'.

Ugggg. I thought I'd already committed this to -current:

If the intline is 0 or 255, then it needs an interrupt routed. Some
Sony laptops improperly flag devices that need an interrupt with 0 :-(.

Backout previous revision. While it fixed many platforms, it broke
all alphas with devices behind ppb's. I'm working on a better solution now.

Note that all alphas that use per-platform interrupt mapping are broken
again (as they have been for several months)

finally fix intr routing on alphas such as the as500 after months of
breakage:

- call PCIB_ROUTE_INTERRUPT() regardless of how valid the intline looks.
Some alphas leave garbage in the intline and leave the intr mapping
to OS platform support routines that map slots/buses to intlines
- Down in the alpha pci code, first try platform.pci_intr_route() and
if it doesn't exist or returns garbage, just read the intline out of
config space.

tested on AS500 (garbage in intline) and UP1000 (PC-like, intline is valid)

Note that a nice little hack like the APIC_IO section of pci_cfgregread()
is not workable. This is because the calling interface for
alpha_pci_route_interrupt() requires us to figure out the bus/slot/etc
from a device_t. At pci_read_device() time, we don't have a device_t
for the bus/slot/func in question.

The serverworks OSB4 pci->isa bridge has the same mapping register at
offset 0x90 for the SMBus device as the PIIX4.

Slightly reimplement some recently added helper functions as methods, so
that drivers are not reaching into the internals of the pci bus. There
are no driver changes, the public interface is the same.

Fix typo: wierd -> weird.

There is no such thing as wierd in the english language.

Sanity check ptr for legal values so it is less likely
(but not impossible) to get stuck in an infinite loop.

Obtained from: msmith@freebsd.org

Remove a redundant prototype.

Don't try to free the now-nonexistent hdrspec field. This one snuck by
me in the previous round of patches. Oops.

Next round of PCI subsystem updates:

- Break out the /dev/pci driver into a separate file.
- Kill the COMPAT_OLDPCI support.
- Make the EISA bridge attach a bit more like the old code; explicitly
check for the existence of eisa0/isa0 and only attach if they don't
already exist. Only make one bus_generic_attach() pass over the
bridge, once both busses are attached. Note that the stupid Intel
bridge's class is entirely unpredictable.
- Add prototypes and re-layout the core PCI modules in line with
current coding standards (not a major whitespace change, just moving
the module data to the top of the file).
- Remove redundant type-2 bridge support from the core PCI code; the
PCI-CardBus code does this itself internally. Remove the now
entirely redundant header-class-specific support, as well as the
secondary and subordinate bus number fields. These are bridge
attributes now.
- Add support for PCI Extended Capabilities.
- Add support for PCI Power Management. The interface currently
allows a driver to query and set the power state of a device.
- Add helper functions to allow drivers to enable/disable busmastering
and the decoding of I/O and memory ranges.
- Use PCI_SLOTMAX and PCI_FUNCMAX rather than magic numbers in some
places.
- Make the PCI-PCI bridge code a little more paranoid about valid
I/O and memory decodes.
- Add some more PCI register definitions for the command and status
registers. Correct another bogus definition for type-1 bridges.

Cosmetic nit; separate slot/function with '.' not ':'

- Fix the device database parsing code so that it actually works.
- Improve the formatting for devices identified by the database.
- Fix the pcib_route_interrupt method definition, as an old version
snuck in here somehow 8(
- Remove a couple of the vendor/device IDs for PCI:ISA bridges which
correctly identify themselves.

Submitted by: peter

Next phase in the PCI subsystem cleanup.

- Move PCI core code to dev/pci.
- Split bridge code out into separate modules.
- Remove the descriptive strings from the bridge drivers. If you
want to know what a device is, use pciconf. Add support for
broadly identifying devices based on class/subclass, and for
parsing a preloaded device identification database so that if
you want to waste the memory, you can identify *anything* we know
about.
- Remove machine-dependant code from the core PCI code. APIC interrupt
mapping is performed by shadowing the intline register in machine-
dependant code.
- Bring interrupt routing support to the Alpha
(although many platforms don't yet support routing or mapping
interrupts entirely correctly). This resulted in spamming
<sys/bus.h> into more places than it really should have gone.
- Put sys/dev on the kernel/modules include path. This avoids
having to change *all* the pci*.h includes.

Reduce code duplication by using the GET_RESOURCE_LIST bus method and related
generic resource_list management functions.

I'll deal with the EISA bits later.

Not objected to by: new-bus

fix warning compile error about unused variable

Fix params passed to pci_porten() and pci_memen().

Unconditionally turning on the I/O and memory enable bits in the PCI
command register is too aggressive. Revert to the previous behaviour, but
leave the new behaviour available as an undocumented option. It's not
clear what the Right, Right Thing is to do here, but the more conservative
approach is safer.

Allow PCI busses to be connected to host bridges detected by ACPI as well.

Write the routed interrupt back to PCI configuration space.

The previous commit broke kernel builds on alpha (and probably ia64).
#ifdef away the offending code until somebody with more newbus fu than
me can figure out where to put a default function that returns 255
without touching each alpha chipset driver..

When a pci device hasn't had an interrupt routed to it (signified by
the intline of 255) go ahead and route the interrupt when we allocate
an interrupt.

Submitted by: msmith

Validate the PCI bus number that we fetch from our parent, since there's no
guarantee that everything attached to *it* is a PCI bus.

When dumping the 'found devices' list in verbose mode, actually show the
bus/slot/function numbers. The old PCI code used other markers or
something, but without it here under the new pci code it is very hard to
tell which device is which (this only affects bootverbose mode).

If a base address register has been set up by the BIOS, but the relevant
enable bit hasn't been set in the command register, set the bit and
honour the register. It seems that quite a few lazy BIOS writers
aren't bothering to do this, which upsets the existing code and causes
us to miss out on properly-configured devices.

Remove duplicate static definition of pci_devclass

* Completely rewrite the alpha busspace to hide the implementation from
the drivers.
* Remove legacy inx/outx support from chipset and replace with macros
which call busspace.
* Rework pci config accesses to route through the pcib device instead of
calling a MD function directly.

With these changes it is possible to cleanly support machines which have
more than one independantly numbered PCI busses. As a bonus, the new
busspace implementation should be measurably faster than the old one.

Nuke the useless chip driver. It gets in the way when you want to load
a functional driver for the device.

Encapsulate the old PCI compatability support and APIs completely under
"options COMPAT_OLDPCI". This option already existed, but now also tidies
up the declarations in #include <pci/pci*.h>. It is amazing how much stuff
was using the old pre-FreeBSD 3.x names and going silently undetected.

Back out the previous change to the queue(3) interface.
It was not discussed and should probably not happen.

Requested by: msmith and others

Change the way that the queue(3) structures are declared; don't assume that
the type argument to *_HEAD and *_ENTRY is a struct.

Suggested by: phk
Reviewed by: phk
Approved by: mdodd

Print the correct value for the map type on a verbose boot.

PR: kern/18662
Submitted by: tamaru@ap.t.u-tokyo.ac.jp

Update 'hose' (actually, MCPCIA instance #) for Alpha Rawhide systems.
We have *got* to fix this bogosity of trying to steal part of the PCI
address space for this stuff.

Fixed the type of some ivar access functions. Ivars have type uintptr_t,
not u_long. On i386's with 64-bit longs, returning u_longs indirectly
in (more than) the space reserved for uintptr_t's tended to corrupt the
previous frame pointer in the stack frame, so it was not easy to debug.
The type mismatches are hidden by the bogus cast in DEVMETHOD().

Remove unneeded <sys/buf.h> includes.

Due to some interesting cpp tricks in lockmgr, the LINT kernel shrinks
by 924 bytes.

* Factor out the object system from new-bus so that it can be used by
non-device code.
* Re-implement the method dispatch to improve efficiency. The new system
takes about 40ns for a method dispatch on a 300Mhz PII which is only
10ns slower than a direct function call on the same hardware.

This changes the new-bus ABI slightly so make sure you re-compile any
driver modules which you use.

Connect the ISA and PCI compatability shims to an option. In this case
it's options COMPAT_OLDISA and COMPAT_OLDPCI. This is meant to be a
fairly strong incentive to update the older drivers to newbus, but doesn't
(quite) leave anybody hanging with no hardware support. I was talking with
a few folks and I was encouraged to simply break or disable the shims but
that was a bit too drastic for my liking.

Print the PCI resources even if they are disabled. This shows more clearly
when the BIOS is forgetful about initialising the USB controllers.

Alpha 8200 port: Until we fix things better, determine which alpha CPU
platform we're running on so we know how many bits to reserve at the top
end for the 'hose' value. It turns out that there's *just* enough room
to support all possible hoses on TurboLaser.
Reviewed by: gallatin@freebsd.org, dfr@free3bsd.org

o No need to print the vendor/device ID for things that matched succesfully.
o ``<device name>'' versus ``device name'' for things that fall under nomatch.

Reviewed by: dfr (in principle)
Approved by: Baron von Hubbard

Remove the vga-pci driver. It serves no purpose and it hides the hardware
from useful drivers such as the 3D DRI drivers I will be porting for
hardware accelerated OpenGL. The hardware will still be reported during
boot using the nomatch system.

Approved by: jkh

Spell "pci_delete_resource" correctly.

Approved by: jkh (who must be very sick of requests now :-)

Put a FYI in the compatability shims so that people are aware that they
are using an old unconverted driver. Most (if not all) of the drivers
for common hardware are newbus these days. However, we don't want
to encourage people to take the easy way out and write new drivers
using the shims. This is just passive "encouragement".

Reviewed by: phk

Show the port/mem/irq of pci devices too.

Make the usb and ide/ata device identification a little saner. Rather than
attaching to the device via chip*, use the newbus nomatch method to report
the device. This leaves them unattached so that a driver can be easily
loaded to grab them later.

[ repository copy of sys/pci/pci_ioctl.h to sys/sys/pciio.h happened in the
background ]

Rename sys/pci/pci_ioctl.h to sys/sys/pciio.h to make it easier for
userland programs to use this interface. Reformat the file, and add a
BSD-style copyright to it.

Add a new man page for pci(4). The PCIOCGETCONF, PCIOCREAD, and PCIOCWRITE
ioctls are documented, but the PCIOCATTACHED ioctl is not documented
because it is not implemented.

Change includes of <pci/pci_ioctl.h> to <sys/pciio.h> or remove them
altogether. In many cases, pci_ioctl.h was unused.

Reviewed by: steve

Raise the pci compat driver match priority a bit so that it's not
quite so close to the chip* drivers.

Remove the 'ivars' arguement to device_add_child() and
device_add_child_ordered(). 'ivars' may now be set using the
device_set_ivars() function.

This makes it easier for us to change how arbitrary data structures are
associated with a device_t. Eventually we won't be modifying device_t
to add additional pointers for ivars, softc data etc.

Despite my best efforts I've probably forgotten something so let me know
if this breaks anything. I've been running with this change for months
and its been quite involved actually isolating all the changes from
the rest of the local changes in my tree.

Reviewed by: peter, dfr

Make the pci driver compat shim return a preference for probe
rather than an "it's mine!" so that other newbus-aware drivers can
bid for the device too. This should allow the sym driver to out-bid
the ncr driver for devices it supports without having to modify ncr.c
at all. ncr would then function as a catch-all.

Feh, kind of went wrong the previous commit. dev should child (in some
cases) plus a typo.

Move the pretty printing of the description for USB controllers to
pci_probe_nomatch, so it won't be in the way when loading USB as a module.

The reason for them being there in the first place is that every
motherboard comes with USB kit and this way it looks more pretty (peter).
The real solution will be to define some method of detaching a driver
after it has attached.

Allow NULL for startp and/or countp in bus_get_resource() so that you can
get one of the two without having to use a dummy variable.

now that a map's base addr is 64-bits, the alpha multi-hose hack needs
to be cast to 64-bits in pci_add_map. This should allow XP1000s and
DS20s to boot -current again.

Change useracc() and kernacc() to use VM_PROT_{READ|WRITE|EXECUTE} for the
"rw" argument, rather than hijacking B_{READ|WRITE}.

Fix two bugs (physio & cam) resulting by the confusion caused by this.

Submitted by: Tor.Egge@fast.no
Reviewed by: alc, ken (partly)

Don't test boolean return against != 1.
Don't needlessly assign the error variable in an if statement.

Fix some resource allocation peculiarities of the intpm device.

Make sure we add an interrupt resource if intline!=255.

Correct a stupid type which prevented us from working with any device
which needed port resources.

* Implement bus_set/get/delete_resource for pci.
* Change the hack used on the alpha for mapping devices into DENSE or
BWX memory spaces to a simpler one. Its still a hack and should be
a seperate api to explicitly map the resource.
* Add $FreeBSD$ as necessary.

allow pci_ioctl to work with multi-hose alphas.
Rather than teaching pci_ioctl about hoses, we just pass down a magic number
& let the platform code figure out what the hose is based on what the bus
number is.

concept approved by dfr

A band-aid to prevent multi-hose alpha chipsets (aka tsunami) from
panic'ing because the hose is not filled in. We should probably extend the
pciioctl interface to take hoses into account..

Backout part of the changes made in 1.111

For unknown devices the output will now be
pci0: unknown card (vendor=0x109e, dev=0x0878) at 14.1 irq 19
instead of
pci0: unknown card DD^0878 (vendor=0x109e, dev=0x0878) at 14.1 irq 19

Before this change, the code used to take the PCI vendor id and translate it
into a three letter ASCII name.
For PnP devices, the vendor id _does_ map to a nice ASCII name
(eg Creative Labs PnP ID maps to "CTL", ESS PnP ID maps to "ESS")

But there is no such mapping for PCI devices, as can be seen by the
example above where the Brooktree PCI vendor ID maps to "DD^"

The PCI Special Interest Group confirmed they do not have any mappings
from vendor ID to ASCII.

Remove five now unused fields from struct cdevsw. They should never
have been there in the first place. A GENERIC kernel shrinks almost 1k.

Add a slightly different safetybelt under nostop for tty drivers.

Add some missing FreeBSD tags

Handle for passthru resource release correctly.

$Id$ -> $FreeBSD$

Convert DEVFS hooks in (most) drivers to make_dev().

Diskslice/label code not yet handled.

Vinum, i4b, alpha, pc98 not dealt with (left to respective Maintainers)

Add the correct hook for devfs to kern_conf.c

The net result of this excercise is that a lot less files depends on DEVFS,
and devtoname() gets more sensible output in many cases.

A few drivers had minor additional cleanups performed relating to cdevsw
registration.

A few drivers don't register a cdevsw{} anymore, but only use make_dev().

Alter the behavior of sys/kern/subr_bus.c:device_print_child()

- device_print_child() either lets the BUS_PRINT_CHILD
method produce the entire device announcement message or
it prints "foo0: not found\n"

Alter sys/kern/subr_bus.c:bus_generic_print_child() to take on
the previous behavior of device_print_child() (printing the
"foo0: <FooDevice 1.1>" bit of the announce message.)

Provide bus_print_child_header() and bus_print_child_footer()
to actually print the output for bus_generic_print_child().
These functions should be used whenever possible (unless you can
just use bus_generic_print_child())

The BUS_PRINT_CHILD method now returns int instead of void.

Modify everything else that defines or uses a BUS_PRINT_CHILD
method to comply with the above changes.

- Devices are 'on' a bus, not 'at' it.
- If a custom BUS_PRINT_CHILD method does the same thing
as bus_generic_print_child(), use bus_generic_print_child()
- Use device_get_nameunit() instead of both
device_get_name() and device_get_unit()
- All BUS_PRINT_CHILD methods return the number of
characters output.

Reviewed by: dfr, peter

Add support for SYS_RES_DENSE and SYS_RES_BWX resource types. These are
equivalent to SYS_RES_MEMORY for x86 but for alpha, the rman_get_virtual()
address of the resource is initialised to point into either dense-mapped
or bwx-mapped space respectively, allowing direct memory pointers to be
used to device memory.

Reviewed by: Andrew Gallatin <gallatin@cs.duke.edu>

Case matters.

DEv_METHOD to DEV_METHOD.

Implement the BUS_PROBE_NOMATCH method for the PCI bus.

This function is called for each device for which no driver
was found.

Output is similar to the eisa_probe_nomatch() function but with the
added benefit of displaying the assigned IRQ (since PCI gives us
this information up front.)

Output is like so:

pci0: unknown card CPQ0508 (vendor=0x0e11, dev=0x0508) at 11.0 irq 9
pci0: unknown card DFZ0508 (vendor=0x10da, dev=0x0508) at 11.0 irq 9
pci0: unknown card DBL0508 (vendor=0x104c, dev=0x0508) at 11.0 irq 9
pci0: unknown card DDM0011 (vendor=0x108d, dev=0x0011) at 11.0 irq 9

I'm not happy with the 3 lines of macro cruft that got added but
I consider it a temporary annoyance as those bits will be moved to
some place where PCI, EISA and ISAPNP code will be able to use them.

(Not surprisingly, this message is longer than the code in question.)

Reviewed by: peter, dfr

Eliminate a bunch of #include "pci.h" and #if NPCI > 0 around entire
files. config will leave the whole file out if configured to do so.

#include <machine/md_var.h> to bring the prototype for
alpha_platform_assign_pciintr() into scope (!).

On the new Meteor cards, the Philips SAA 7116 is connected to the PCI bus
via an IBM PCI-PCI bridge (82351 or 82352 or 82353)

The driver must identify if it is on a secondary PCI bus, which is
created via the IBM PCI-PCI bridge. If it is, then it must initialise
the IBM PCI-PCI bridge correctly.

To do this, the following new functions are added.
Because they use the pcici_t tag, they are considered 2.2 compatibility APIs
pcici_t * pci_get_parent_from_tag(pcici_t tag);
int pci_get_bus_from_tag(pcici_t tag);

(The _from_tag suffix is used to prevent clashes with similarly named
newbus PCI API functions)

Submitted by: Anton Berezin <tobez@plab.ku.dk>
Reviewed by: Doug Rabson <dfr@nlsystems.com>
Reworked by: Me (roger)

Simplify cdevsw registration.

The cdevsw_add() function now finds the major number(s) in the
struct cdevsw passed to it. cdevsw_add_generic() is no longer
needed, cdevsw_add() does the same thing.

cdevsw_add() will print an message if the d_maj field looks bogus.

Remove nblkdev and nchrdev variables. Most places they were used
bogusly. Instead check a dev_t for validity by seeing if devsw()
or bdevsw() returns NULL.

Move bdevsw() and devsw() functions to kern/kern_conf.c

Bump __FreeBSD_version to 400006

This commit removes:
72 bogus makedev() calls
26 bogus SYSINIT functions

if_xe.c bogusly accessed cdevsw[], author/maintainer please fix.

I4b and vinum not changed. Patches emailed to authors. LINT
probably broken until they catch up.

This commit should be a extensive NO-OP:

Reformat and initialize correctly all "struct cdevsw".

Initialize the d_maj and d_bmaj fields.

The d_reset field was not removed, although it is never used.

I used a program to do most of this, so all the files now use the
same consistent format. Please keep it that way.

Vinum and i4b not modified, patches emailed to respective authors.

In pci_alloc_resource() only check start and end to see if its a default.

Add support for multiple PCI "hoses" used on various alpha platforms.
The specific intent of this commit is to pave the way for importing
Compaq XP1000 support. These changes should not affect the i386 port.

Reviewed by: Doug Rabson <dfr@nlsystems.com>
(actually, he walked me through most of it & deserves more than reviewd-by
credit )

Add missing suspend/resume methods.

For the ioctl that reads the pci configuration, look up the name and unit
on the fly so that we can see the driver assignment of new pci devices
as well in the 'pciconf -l' display.

Argh, don't clobber the pci device list if there are multiple busses!
(An AGP counts as a PCI bus, it seems...)
This stopped 'pciconf -l' from working on AGP or PCI->PCI bridge systems.

Move the declaration of the interrupt type from the driver structure
to the BUS_SETUP_INTR call.

Print 'irq nn' on the device attach line like the old pci code did.
However, we are not printing 'int a/b/c/d' yet, is it worth it on non-SMP
systems? (It's useful when tracing PCI->IO-APIC routing on SMP systems)