pci.c revision 49130
1/* 2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * $Id: pci.c,v 1.111 1999/07/27 04:28:14 mdodd Exp $ 27 * 28 */ 29 30#include "opt_bus.h" 31 32#include "opt_devfs.h" 33#include "opt_simos.h" 34 35#include <sys/param.h> 36#include <sys/systm.h> 37#include <sys/malloc.h> 38#include <sys/module.h> 39#include <sys/fcntl.h> 40#include <sys/conf.h> 41#include <sys/kernel.h> 42#include <sys/queue.h> 43#include <sys/types.h> 44#include <sys/buf.h> 45#ifdef DEVFS 46#include <sys/devfsext.h> 47#endif /* DEVFS */ 48 49#include <vm/vm.h> 50#include <vm/pmap.h> 51#include <vm/vm_extern.h> 52 53#include <sys/bus.h> 54#include <machine/bus.h> 55#include <sys/rman.h> 56#include <machine/resource.h> 57#include <machine/md_var.h> /* For the Alpha */ 58 59#include <pci/pcireg.h> 60#include <pci/pcivar.h> 61#include <pci/pci_ioctl.h> 62 63#ifdef APIC_IO 64#include <machine/smp.h> 65#endif /* APIC_IO */ 66 67static STAILQ_HEAD(devlist, pci_devinfo) pci_devq; 68u_int32_t pci_numdevs = 0; 69static u_int32_t pci_generation = 0; 70 71#define PCI_MFCTR_CHAR0(ID) (char)(((ID>>10) & 0x1F) | '@') /* Bits 10-14 */ 72#define PCI_MFCTR_CHAR1(ID) (char)(((ID>>5 ) & 0x1F) | '@') /* Bits 5-9 */ 73#define PCI_MFCTR_CHAR2(ID) (char)(( ID & 0x1F) | '@') /* Bits 0-4 */ 74 75/* return base address of memory or port map */ 76 77static int 78pci_mapbase(unsigned mapreg) 79{ 80 int mask = 0x03; 81 if ((mapreg & 0x01) == 0) 82 mask = 0x0f; 83 return (mapreg & ~mask); 84} 85 86/* return map type of memory or port map */ 87 88static int 89pci_maptype(unsigned mapreg) 90{ 91 static u_int8_t maptype[0x10] = { 92 PCI_MAPMEM, PCI_MAPPORT, 93 PCI_MAPMEM, 0, 94 PCI_MAPMEM, PCI_MAPPORT, 95 0, 0, 96 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT, 97 PCI_MAPMEM|PCI_MAPMEMP, 0, 98 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT, 99 0, 0, 100 }; 101 102 return maptype[mapreg & 0x0f]; 103} 104 105/* return log2 of map size decoded for memory or port map */ 106 107static int 108pci_mapsize(unsigned testval) 109{ 110 int ln2size; 111 112 testval = pci_mapbase(testval); 113 ln2size = 0; 114 if (testval != 0) { 115 while ((testval & 1) == 0) 116 { 117 ln2size++; 118 testval >>= 1; 119 } 120 } 121 return (ln2size); 122} 123 124/* return log2 of address range supported by map register */ 125 126static int 127pci_maprange(unsigned mapreg) 128{ 129 int ln2range = 0; 130 switch (mapreg & 0x07) { 131 case 0x00: 132 case 0x01: 133 case 0x05: 134 ln2range = 32; 135 break; 136 case 0x02: 137 ln2range = 20; 138 break; 139 case 0x04: 140 ln2range = 64; 141 break; 142 } 143 return (ln2range); 144} 145 146/* extract map parameters into newly allocated array of pcimap structures */ 147 148static pcimap * 149pci_readmaps(pcicfgregs *cfg, int maxmaps) 150{ 151 int i, j = 0; 152 pcimap *map; 153 int map64 = 0; 154 int reg = PCIR_MAPS; 155 156 for (i = 0; i < maxmaps; i++) { 157 int reg = PCIR_MAPS + i*4; 158 u_int32_t base; 159 u_int32_t ln2range; 160 161 base = pci_cfgread(cfg, reg, 4); 162 ln2range = pci_maprange(base); 163 164 if (base == 0 || ln2range == 0 || base == 0xffffffff) 165 continue; /* skip invalid entry */ 166 else { 167 j++; 168 if (ln2range > 32) { 169 i++; 170 j++; 171 } 172 } 173 } 174 175 map = malloc(j * sizeof (pcimap), M_DEVBUF, M_WAITOK); 176 if (map != NULL) { 177 bzero(map, sizeof(pcimap) * j); 178 cfg->nummaps = j; 179 180 for (i = 0, j = 0; i < maxmaps; i++, reg += 4) { 181 u_int32_t base; 182 u_int32_t testval; 183 184 base = pci_cfgread(cfg, reg, 4); 185 186 if (map64 == 0) { 187 if (base == 0 || base == 0xffffffff) 188 continue; /* skip invalid entry */ 189 pci_cfgwrite(cfg, reg, 0xffffffff, 4); 190 testval = pci_cfgread(cfg, reg, 4); 191 pci_cfgwrite(cfg, reg, base, 4); 192 193 map[j].reg = reg; 194 map[j].base = pci_mapbase(base); 195 map[j].type = pci_maptype(base); 196 map[j].ln2size = pci_mapsize(testval); 197 map[j].ln2range = pci_maprange(testval); 198 map64 = map[j].ln2range == 64; 199 } else { 200 /* only fill in base, other fields are 0 */ 201 map[j].base = base; 202 map64 = 0; 203 } 204#ifdef __alpha__ 205 /* 206 * XXX: encode hose number in the base addr, 207 * This will go away once the bus_space functions 208 * can deal with multiple hoses 209 */ 210 211 if(cfg->hose){ 212 if(map[j].base & 0x80000000){ 213 printf("base addr = 0x%x\n", map[j].base); 214 printf("hacked addr = 0x%x\n", 215 map[j].base | (cfg->hose << 31)); 216 217 panic("hose encoding hack would clobber base addr"); 218 } 219 if(cfg->hose > 1 ) 220 panic("only one hose supported!"); 221 map[j].base |= (cfg->hose << 31); 222 } 223#endif 224 j++; 225 } 226 } 227 return (map); 228} 229 230/* adjust some values from PCI 1.0 devices to match 2.0 standards ... */ 231 232static void 233pci_fixancient(pcicfgregs *cfg) 234{ 235 if (cfg->hdrtype != 0) 236 return; 237 238 /* PCI to PCI bridges use header type 1 */ 239 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI) 240 cfg->hdrtype = 1; 241} 242 243/* read config data specific to header type 1 device (PCI to PCI bridge) */ 244 245static void * 246pci_readppb(pcicfgregs *cfg) 247{ 248 pcih1cfgregs *p; 249 250 p = malloc(sizeof (pcih1cfgregs), M_DEVBUF, M_WAITOK); 251 if (p == NULL) 252 return (NULL); 253 254 bzero(p, sizeof *p); 255 256 p->secstat = pci_cfgread(cfg, PCIR_SECSTAT_1, 2); 257 p->bridgectl = pci_cfgread(cfg, PCIR_BRIDGECTL_1, 2); 258 259 p->seclat = pci_cfgread(cfg, PCIR_SECLAT_1, 1); 260 261 p->iobase = PCI_PPBIOBASE (pci_cfgread(cfg, PCIR_IOBASEH_1, 2), 262 pci_cfgread(cfg, PCIR_IOBASEL_1, 1)); 263 p->iolimit = PCI_PPBIOLIMIT (pci_cfgread(cfg, PCIR_IOLIMITH_1, 2), 264 pci_cfgread(cfg, PCIR_IOLIMITL_1, 1)); 265 266 p->membase = PCI_PPBMEMBASE (0, 267 pci_cfgread(cfg, PCIR_MEMBASE_1, 2)); 268 p->memlimit = PCI_PPBMEMLIMIT (0, 269 pci_cfgread(cfg, PCIR_MEMLIMIT_1, 2)); 270 271 p->pmembase = PCI_PPBMEMBASE ( 272 (pci_addr_t)pci_cfgread(cfg, PCIR_PMBASEH_1, 4), 273 pci_cfgread(cfg, PCIR_PMBASEL_1, 2)); 274 275 p->pmemlimit = PCI_PPBMEMLIMIT ( 276 (pci_addr_t)pci_cfgread(cfg, PCIR_PMLIMITH_1, 4), 277 pci_cfgread(cfg, PCIR_PMLIMITL_1, 2)); 278 return (p); 279} 280 281/* read config data specific to header type 2 device (PCI to CardBus bridge) */ 282 283static void * 284pci_readpcb(pcicfgregs *cfg) 285{ 286 pcih2cfgregs *p; 287 288 p = malloc(sizeof (pcih2cfgregs), M_DEVBUF, M_WAITOK); 289 if (p == NULL) 290 return (NULL); 291 292 bzero(p, sizeof *p); 293 294 p->secstat = pci_cfgread(cfg, PCIR_SECSTAT_2, 2); 295 p->bridgectl = pci_cfgread(cfg, PCIR_BRIDGECTL_2, 2); 296 297 p->seclat = pci_cfgread(cfg, PCIR_SECLAT_2, 1); 298 299 p->membase0 = pci_cfgread(cfg, PCIR_MEMBASE0_2, 4); 300 p->memlimit0 = pci_cfgread(cfg, PCIR_MEMLIMIT0_2, 4); 301 p->membase1 = pci_cfgread(cfg, PCIR_MEMBASE1_2, 4); 302 p->memlimit1 = pci_cfgread(cfg, PCIR_MEMLIMIT1_2, 4); 303 304 p->iobase0 = pci_cfgread(cfg, PCIR_IOBASE0_2, 4); 305 p->iolimit0 = pci_cfgread(cfg, PCIR_IOLIMIT0_2, 4); 306 p->iobase1 = pci_cfgread(cfg, PCIR_IOBASE1_2, 4); 307 p->iolimit1 = pci_cfgread(cfg, PCIR_IOLIMIT1_2, 4); 308 309 p->pccardif = pci_cfgread(cfg, PCIR_PCCARDIF_2, 4); 310 return p; 311} 312 313/* extract header type specific config data */ 314 315static void 316pci_hdrtypedata(pcicfgregs *cfg) 317{ 318 switch (cfg->hdrtype) { 319 case 0: 320 cfg->subvendor = pci_cfgread(cfg, PCIR_SUBVEND_0, 2); 321 cfg->subdevice = pci_cfgread(cfg, PCIR_SUBDEV_0, 2); 322 cfg->map = pci_readmaps(cfg, PCI_MAXMAPS_0); 323 break; 324 case 1: 325 cfg->subvendor = pci_cfgread(cfg, PCIR_SUBVEND_1, 2); 326 cfg->subdevice = pci_cfgread(cfg, PCIR_SUBDEV_1, 2); 327 cfg->secondarybus = pci_cfgread(cfg, PCIR_SECBUS_1, 1); 328 cfg->subordinatebus = pci_cfgread(cfg, PCIR_SUBBUS_1, 1); 329 cfg->map = pci_readmaps(cfg, PCI_MAXMAPS_1); 330 cfg->hdrspec = pci_readppb(cfg); 331 break; 332 case 2: 333 cfg->subvendor = pci_cfgread(cfg, PCIR_SUBVEND_2, 2); 334 cfg->subdevice = pci_cfgread(cfg, PCIR_SUBDEV_2, 2); 335 cfg->secondarybus = pci_cfgread(cfg, PCIR_SECBUS_2, 1); 336 cfg->subordinatebus = pci_cfgread(cfg, PCIR_SUBBUS_2, 1); 337 cfg->map = pci_readmaps(cfg, PCI_MAXMAPS_2); 338 cfg->hdrspec = pci_readpcb(cfg); 339 break; 340 } 341} 342 343/* read configuration header into pcicfgrect structure */ 344 345static struct pci_devinfo * 346pci_readcfg(pcicfgregs *probe) 347{ 348 pcicfgregs *cfg = NULL; 349 struct pci_devinfo *devlist_entry; 350 struct devlist *devlist_head; 351 352 devlist_head = &pci_devq; 353 354 devlist_entry = NULL; 355 356 if (pci_cfgread(probe, PCIR_DEVVENDOR, 4) != -1) { 357 devlist_entry = malloc(sizeof(struct pci_devinfo), 358 M_DEVBUF, M_WAITOK); 359 if (devlist_entry == NULL) 360 return (NULL); 361 bzero(devlist_entry, sizeof *devlist_entry); 362 363 cfg = &devlist_entry->cfg; 364 365 cfg->hose = probe->hose; 366 cfg->bus = probe->bus; 367 cfg->slot = probe->slot; 368 cfg->func = probe->func; 369 cfg->vendor = pci_cfgread(cfg, PCIR_VENDOR, 2); 370 cfg->device = pci_cfgread(cfg, PCIR_DEVICE, 2); 371 cfg->cmdreg = pci_cfgread(cfg, PCIR_COMMAND, 2); 372 cfg->statreg = pci_cfgread(cfg, PCIR_STATUS, 2); 373 cfg->baseclass = pci_cfgread(cfg, PCIR_CLASS, 1); 374 cfg->subclass = pci_cfgread(cfg, PCIR_SUBCLASS, 1); 375 cfg->progif = pci_cfgread(cfg, PCIR_PROGIF, 1); 376 cfg->revid = pci_cfgread(cfg, PCIR_REVID, 1); 377 cfg->hdrtype = pci_cfgread(cfg, PCIR_HEADERTYPE, 1); 378 cfg->cachelnsz = pci_cfgread(cfg, PCIR_CACHELNSZ, 1); 379 cfg->lattimer = pci_cfgread(cfg, PCIR_LATTIMER, 1); 380 cfg->intpin = pci_cfgread(cfg, PCIR_INTPIN, 1); 381 cfg->intline = pci_cfgread(cfg, PCIR_INTLINE, 1); 382#ifdef __alpha__ 383 alpha_platform_assign_pciintr(cfg); 384#endif 385 386#ifdef APIC_IO 387 if (cfg->intpin != 0) { 388 int airq; 389 390 airq = pci_apic_irq(cfg->bus, cfg->slot, cfg->intpin); 391 if (airq >= 0) { 392 /* PCI specific entry found in MP table */ 393 if (airq != cfg->intline) { 394 undirect_pci_irq(cfg->intline); 395 cfg->intline = airq; 396 } 397 } else { 398 /* 399 * PCI interrupts might be redirected to the 400 * ISA bus according to some MP tables. Use the 401 * same methods as used by the ISA devices 402 * devices to find the proper IOAPIC int pin. 403 */ 404 airq = isa_apic_irq(cfg->intline); 405 if ((airq >= 0) && (airq != cfg->intline)) { 406 /* XXX: undirect_pci_irq() ? */ 407 undirect_isa_irq(cfg->intline); 408 cfg->intline = airq; 409 } 410 } 411 } 412#endif /* APIC_IO */ 413 414 cfg->mingnt = pci_cfgread(cfg, PCIR_MINGNT, 1); 415 cfg->maxlat = pci_cfgread(cfg, PCIR_MAXLAT, 1); 416 417 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0; 418 cfg->hdrtype &= ~PCIM_MFDEV; 419 420 pci_fixancient(cfg); 421 pci_hdrtypedata(cfg); 422 423 STAILQ_INSERT_TAIL(devlist_head, devlist_entry, pci_links); 424 425 devlist_entry->conf.pc_sel.pc_bus = cfg->bus; 426 devlist_entry->conf.pc_sel.pc_dev = cfg->slot; 427 devlist_entry->conf.pc_sel.pc_func = cfg->func; 428 devlist_entry->conf.pc_hdr = cfg->hdrtype; 429 430 devlist_entry->conf.pc_subvendor = cfg->subvendor; 431 devlist_entry->conf.pc_subdevice = cfg->subdevice; 432 devlist_entry->conf.pc_vendor = cfg->vendor; 433 devlist_entry->conf.pc_device = cfg->device; 434 435 devlist_entry->conf.pc_class = cfg->baseclass; 436 devlist_entry->conf.pc_subclass = cfg->subclass; 437 devlist_entry->conf.pc_progif = cfg->progif; 438 devlist_entry->conf.pc_revid = cfg->revid; 439 440 pci_numdevs++; 441 pci_generation++; 442 } 443 return (devlist_entry); 444} 445 446#if 0 447/* free pcicfgregs structure and all depending data structures */ 448 449static int 450pci_freecfg(struct pci_devinfo *dinfo) 451{ 452 struct devlist *devlist_head; 453 454 devlist_head = &pci_devq; 455 456 if (dinfo->cfg.hdrspec != NULL) 457 free(dinfo->cfg.hdrspec, M_DEVBUF); 458 if (dinfo->cfg.map != NULL) 459 free(dinfo->cfg.map, M_DEVBUF); 460 /* XXX this hasn't been tested */ 461 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links); 462 free(dinfo, M_DEVBUF); 463 464 /* increment the generation count */ 465 pci_generation++; 466 467 /* we're losing one device */ 468 pci_numdevs--; 469 return (0); 470} 471#endif 472 473 474/* 475 * This is the user interface to PCI configuration space. 476 */ 477 478static int 479pci_open(dev_t dev, int oflags, int devtype, struct proc *p) 480{ 481 if ((oflags & FWRITE) && securelevel > 0) { 482 return EPERM; 483 } 484 return 0; 485} 486 487static int 488pci_close(dev_t dev, int flag, int devtype, struct proc *p) 489{ 490 return 0; 491} 492 493/* 494 * Match a single pci_conf structure against an array of pci_match_conf 495 * structures. The first argument, 'matches', is an array of num_matches 496 * pci_match_conf structures. match_buf is a pointer to the pci_conf 497 * structure that will be compared to every entry in the matches array. 498 * This function returns 1 on failure, 0 on success. 499 */ 500static int 501pci_conf_match(struct pci_match_conf *matches, int num_matches, 502 struct pci_conf *match_buf) 503{ 504 int i; 505 506 if ((matches == NULL) || (match_buf == NULL) || (num_matches <= 0)) 507 return(1); 508 509 for (i = 0; i < num_matches; i++) { 510 /* 511 * I'm not sure why someone would do this...but... 512 */ 513 if (matches[i].flags == PCI_GETCONF_NO_MATCH) 514 continue; 515 516 /* 517 * Look at each of the match flags. If it's set, do the 518 * comparison. If the comparison fails, we don't have a 519 * match, go on to the next item if there is one. 520 */ 521 if (((matches[i].flags & PCI_GETCONF_MATCH_BUS) != 0) 522 && (match_buf->pc_sel.pc_bus != matches[i].pc_sel.pc_bus)) 523 continue; 524 525 if (((matches[i].flags & PCI_GETCONF_MATCH_DEV) != 0) 526 && (match_buf->pc_sel.pc_dev != matches[i].pc_sel.pc_dev)) 527 continue; 528 529 if (((matches[i].flags & PCI_GETCONF_MATCH_FUNC) != 0) 530 && (match_buf->pc_sel.pc_func != matches[i].pc_sel.pc_func)) 531 continue; 532 533 if (((matches[i].flags & PCI_GETCONF_MATCH_VENDOR) != 0) 534 && (match_buf->pc_vendor != matches[i].pc_vendor)) 535 continue; 536 537 if (((matches[i].flags & PCI_GETCONF_MATCH_DEVICE) != 0) 538 && (match_buf->pc_device != matches[i].pc_device)) 539 continue; 540 541 if (((matches[i].flags & PCI_GETCONF_MATCH_CLASS) != 0) 542 && (match_buf->pc_class != matches[i].pc_class)) 543 continue; 544 545 if (((matches[i].flags & PCI_GETCONF_MATCH_UNIT) != 0) 546 && (match_buf->pd_unit != matches[i].pd_unit)) 547 continue; 548 549 if (((matches[i].flags & PCI_GETCONF_MATCH_NAME) != 0) 550 && (strncmp(matches[i].pd_name, match_buf->pd_name, 551 sizeof(match_buf->pd_name)) != 0)) 552 continue; 553 554 return(0); 555 } 556 557 return(1); 558} 559 560/* 561 * Locate the parent of a PCI device by scanning the PCI devlist 562 * and return the entry for the parent. 563 * For devices on PCI Bus 0 (the host bus), this is the PCI Host. 564 * For devices on secondary PCI busses, this is that bus' PCI-PCI Bridge. 565 */ 566 567pcicfgregs * 568pci_devlist_get_parent(pcicfgregs *cfg) 569{ 570 struct devlist *devlist_head; 571 struct pci_devinfo *dinfo; 572 pcicfgregs *bridge_cfg; 573 int i; 574 575 dinfo = STAILQ_FIRST(devlist_head = &pci_devq); 576 577 /* If the device is on PCI bus 0, look for the host */ 578 if (cfg->bus == 0) { 579 for (i = 0; (dinfo != NULL) && (i < pci_numdevs); 580 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) { 581 bridge_cfg = &dinfo->cfg; 582 if (bridge_cfg->baseclass == PCIC_BRIDGE 583 && bridge_cfg->subclass == PCIS_BRIDGE_HOST 584 && bridge_cfg->bus == cfg->bus) { 585 return bridge_cfg; 586 } 587 } 588 } 589 590 /* If the device is not on PCI bus 0, look for the PCI-PCI bridge */ 591 if (cfg->bus > 0) { 592 for (i = 0; (dinfo != NULL) && (i < pci_numdevs); 593 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) { 594 bridge_cfg = &dinfo->cfg; 595 if (bridge_cfg->baseclass == PCIC_BRIDGE 596 && bridge_cfg->subclass == PCIS_BRIDGE_PCI 597 && bridge_cfg->secondarybus == cfg->bus) { 598 return bridge_cfg; 599 } 600 } 601 } 602 603 return NULL; 604} 605 606static int 607pci_ioctl(dev_t dev, u_long cmd, caddr_t data, int flag, struct proc *p) 608{ 609 struct pci_io *io; 610 const char *name; 611 int error; 612 613 if (!(flag & FWRITE)) 614 return EPERM; 615 616 617 switch(cmd) { 618 case PCIOCGETCONF: 619 { 620 struct pci_devinfo *dinfo; 621 struct pci_conf_io *cio; 622 struct devlist *devlist_head; 623 struct pci_match_conf *pattern_buf; 624 int num_patterns; 625 size_t iolen; 626 int ionum, i; 627 628 cio = (struct pci_conf_io *)data; 629 630 num_patterns = 0; 631 dinfo = NULL; 632 633 /* 634 * Hopefully the user won't pass in a null pointer, but it 635 * can't hurt to check. 636 */ 637 if (cio == NULL) { 638 error = EINVAL; 639 break; 640 } 641 642 /* 643 * If the user specified an offset into the device list, 644 * but the list has changed since they last called this 645 * ioctl, tell them that the list has changed. They will 646 * have to get the list from the beginning. 647 */ 648 if ((cio->offset != 0) 649 && (cio->generation != pci_generation)){ 650 cio->num_matches = 0; 651 cio->status = PCI_GETCONF_LIST_CHANGED; 652 error = 0; 653 break; 654 } 655 656 /* 657 * Check to see whether the user has asked for an offset 658 * past the end of our list. 659 */ 660 if (cio->offset >= pci_numdevs) { 661 cio->num_matches = 0; 662 cio->status = PCI_GETCONF_LAST_DEVICE; 663 error = 0; 664 break; 665 } 666 667 /* get the head of the device queue */ 668 devlist_head = &pci_devq; 669 670 /* 671 * Determine how much room we have for pci_conf structures. 672 * Round the user's buffer size down to the nearest 673 * multiple of sizeof(struct pci_conf) in case the user 674 * didn't specify a multiple of that size. 675 */ 676 iolen = min(cio->match_buf_len - 677 (cio->match_buf_len % sizeof(struct pci_conf)), 678 pci_numdevs * sizeof(struct pci_conf)); 679 680 /* 681 * Since we know that iolen is a multiple of the size of 682 * the pciconf union, it's okay to do this. 683 */ 684 ionum = iolen / sizeof(struct pci_conf); 685 686 /* 687 * If this test is true, the user wants the pci_conf 688 * structures returned to match the supplied entries. 689 */ 690 if ((cio->num_patterns > 0) 691 && (cio->pat_buf_len > 0)) { 692 /* 693 * pat_buf_len needs to be: 694 * num_patterns * sizeof(struct pci_match_conf) 695 * While it is certainly possible the user just 696 * allocated a large buffer, but set the number of 697 * matches correctly, it is far more likely that 698 * their kernel doesn't match the userland utility 699 * they're using. It's also possible that the user 700 * forgot to initialize some variables. Yes, this 701 * may be overly picky, but I hazard to guess that 702 * it's far more likely to just catch folks that 703 * updated their kernel but not their userland. 704 */ 705 if ((cio->num_patterns * 706 sizeof(struct pci_match_conf)) != cio->pat_buf_len){ 707 /* The user made a mistake, return an error*/ 708 cio->status = PCI_GETCONF_ERROR; 709 printf("pci_ioctl: pat_buf_len %d != " 710 "num_patterns (%d) * sizeof(struct " 711 "pci_match_conf) (%d)\npci_ioctl: " 712 "pat_buf_len should be = %d\n", 713 cio->pat_buf_len, cio->num_patterns, 714 (int)sizeof(struct pci_match_conf), 715 (int)sizeof(struct pci_match_conf) * 716 cio->num_patterns); 717 printf("pci_ioctl: do your headers match your " 718 "kernel?\n"); 719 cio->num_matches = 0; 720 error = EINVAL; 721 break; 722 } 723 724 /* 725 * Check the user's buffer to make sure it's readable. 726 */ 727 if ((error = useracc((caddr_t)cio->patterns, 728 cio->pat_buf_len, B_READ)) != 1){ 729 printf("pci_ioctl: pattern buffer %p, " 730 "length %u isn't user accessible for" 731 " READ\n", cio->patterns, 732 cio->pat_buf_len); 733 error = EACCES; 734 break; 735 } 736 /* 737 * Allocate a buffer to hold the patterns. 738 */ 739 pattern_buf = malloc(cio->pat_buf_len, M_TEMP, 740 M_WAITOK); 741 error = copyin(cio->patterns, pattern_buf, 742 cio->pat_buf_len); 743 if (error != 0) 744 break; 745 num_patterns = cio->num_patterns; 746 747 } else if ((cio->num_patterns > 0) 748 || (cio->pat_buf_len > 0)) { 749 /* 750 * The user made a mistake, spit out an error. 751 */ 752 cio->status = PCI_GETCONF_ERROR; 753 cio->num_matches = 0; 754 printf("pci_ioctl: invalid GETCONF arguments\n"); 755 error = EINVAL; 756 break; 757 } else 758 pattern_buf = NULL; 759 760 /* 761 * Make sure we can write to the match buffer. 762 */ 763 if ((error = useracc((caddr_t)cio->matches, cio->match_buf_len, 764 B_WRITE)) != 1) { 765 printf("pci_ioctl: match buffer %p, length %u " 766 "isn't user accessible for WRITE\n", 767 cio->matches, cio->match_buf_len); 768 error = EACCES; 769 break; 770 } 771 772 /* 773 * Go through the list of devices and copy out the devices 774 * that match the user's criteria. 775 */ 776 for (cio->num_matches = 0, error = 0, i = 0, 777 dinfo = STAILQ_FIRST(devlist_head); 778 (dinfo != NULL) && (cio->num_matches < ionum) 779 && (error == 0) && (i < pci_numdevs); 780 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) { 781 782 if (i < cio->offset) 783 continue; 784 785 /* Populate pd_name and pd_unit */ 786 name = NULL; 787 if (dinfo->cfg.dev && dinfo->conf.pd_name[0] == '\0') 788 name = device_get_name(dinfo->cfg.dev); 789 if (name) { 790 strncpy(dinfo->conf.pd_name, name, 791 sizeof(dinfo->conf.pd_name)); 792 dinfo->conf.pd_name[PCI_MAXNAMELEN] = 0; 793 dinfo->conf.pd_unit = 794 device_get_unit(dinfo->cfg.dev); 795 } 796 797 if ((pattern_buf == NULL) || 798 (pci_conf_match(pattern_buf, num_patterns, 799 &dinfo->conf) == 0)) { 800 801 /* 802 * If we've filled up the user's buffer, 803 * break out at this point. Since we've 804 * got a match here, we'll pick right back 805 * up at the matching entry. We can also 806 * tell the user that there are more matches 807 * left. 808 */ 809 if (cio->num_matches >= ionum) 810 break; 811 812 error = copyout(&dinfo->conf, 813 &cio->matches[cio->num_matches], 814 sizeof(struct pci_conf)); 815 cio->num_matches++; 816 } 817 } 818 819 /* 820 * Set the pointer into the list, so if the user is getting 821 * n records at a time, where n < pci_numdevs, 822 */ 823 cio->offset = i; 824 825 /* 826 * Set the generation, the user will need this if they make 827 * another ioctl call with offset != 0. 828 */ 829 cio->generation = pci_generation; 830 831 /* 832 * If this is the last device, inform the user so he won't 833 * bother asking for more devices. If dinfo isn't NULL, we 834 * know that there are more matches in the list because of 835 * the way the traversal is done. 836 */ 837 if (dinfo == NULL) 838 cio->status = PCI_GETCONF_LAST_DEVICE; 839 else 840 cio->status = PCI_GETCONF_MORE_DEVS; 841 842 if (pattern_buf != NULL) 843 free(pattern_buf, M_TEMP); 844 845 break; 846 } 847 case PCIOCREAD: 848 io = (struct pci_io *)data; 849 switch(io->pi_width) { 850 pcicfgregs probe; 851 case 4: 852 case 2: 853 case 1: 854 probe.bus = io->pi_sel.pc_bus; 855 probe.slot = io->pi_sel.pc_dev; 856 probe.func = io->pi_sel.pc_func; 857 io->pi_data = pci_cfgread(&probe, 858 io->pi_reg, io->pi_width); 859 error = 0; 860 break; 861 default: 862 error = ENODEV; 863 break; 864 } 865 break; 866 867 case PCIOCWRITE: 868 io = (struct pci_io *)data; 869 switch(io->pi_width) { 870 pcicfgregs probe; 871 case 4: 872 case 2: 873 case 1: 874 probe.bus = io->pi_sel.pc_bus; 875 probe.slot = io->pi_sel.pc_dev; 876 probe.func = io->pi_sel.pc_func; 877 pci_cfgwrite(&probe, 878 io->pi_reg, io->pi_data, io->pi_width); 879 error = 0; 880 break; 881 default: 882 error = ENODEV; 883 break; 884 } 885 break; 886 887 default: 888 error = ENOTTY; 889 break; 890 } 891 892 return (error); 893} 894 895#define PCI_CDEV 78 896 897static struct cdevsw pcicdev = { 898 /* open */ pci_open, 899 /* close */ pci_close, 900 /* read */ noread, 901 /* write */ nowrite, 902 /* ioctl */ pci_ioctl, 903 /* stop */ nostop, 904 /* reset */ noreset, 905 /* devtotty */ nodevtotty, 906 /* poll */ nopoll, 907 /* mmap */ nommap, 908 /* strategy */ nostrategy, 909 /* name */ "pci", 910 /* parms */ noparms, 911 /* maj */ PCI_CDEV, 912 /* dump */ nodump, 913 /* psize */ nopsize, 914 /* flags */ 0, 915 /* maxio */ 0, 916 /* bmaj */ -1 917}; 918 919#ifdef DEVFS 920static void *pci_devfs_token; 921#endif 922 923static void 924pci_cdevinit(void *dummy) 925{ 926 cdevsw_add(&pcicdev); 927#ifdef DEVFS 928 pci_devfs_token = devfs_add_devswf(&pcicdev, 0, DV_CHR, 929 UID_ROOT, GID_WHEEL, 0644, "pci"); 930#endif 931} 932 933SYSINIT(pcidev, SI_SUB_DRIVERS, SI_ORDER_MIDDLE+PCI_CDEV, pci_cdevinit, NULL); 934 935#include "pci_if.h" 936 937/* 938 * A simple driver to wrap the old pci driver mechanism for back-compat. 939 */ 940 941static int 942pci_compat_probe(device_t dev) 943{ 944 struct pci_device *dvp; 945 struct pci_devinfo *dinfo; 946 pcicfgregs *cfg; 947 const char *name; 948 int error; 949 950 dinfo = device_get_ivars(dev); 951 cfg = &dinfo->cfg; 952 dvp = device_get_driver(dev)->priv; 953 954 /* 955 * Do the wrapped probe. 956 */ 957 error = ENXIO; 958 if (dvp && dvp->pd_probe) { 959 name = dvp->pd_probe(cfg, (cfg->device << 16) + cfg->vendor); 960 if (name) { 961 device_set_desc_copy(dev, name); 962 error = 0; 963 } 964 } 965 966 return error; 967} 968 969static int 970pci_compat_attach(device_t dev) 971{ 972 struct pci_device *dvp; 973 struct pci_devinfo *dinfo; 974 pcicfgregs *cfg; 975 int unit; 976 977 dinfo = device_get_ivars(dev); 978 cfg = &dinfo->cfg; 979 dvp = device_get_driver(dev)->priv; 980 981 unit = device_get_unit(dev); 982 if (unit > *dvp->pd_count) 983 *dvp->pd_count = unit; 984 if (dvp->pd_attach) 985 dvp->pd_attach(cfg, unit); 986 return 0; 987} 988 989static device_method_t pci_compat_methods[] = { 990 /* Device interface */ 991 DEVMETHOD(device_probe, pci_compat_probe), 992 DEVMETHOD(device_attach, pci_compat_attach), 993 994 { 0, 0 } 995}; 996 997static devclass_t pci_devclass; 998 999/* 1000 * Create a new style driver around each old pci driver. 1001 */ 1002int 1003compat_pci_handler(module_t mod, int type, void *data) 1004{ 1005 struct pci_device *dvp = (struct pci_device *)data; 1006 driver_t *driver; 1007 1008 switch (type) { 1009 case MOD_LOAD: 1010 driver = malloc(sizeof(driver_t), M_DEVBUF, M_NOWAIT); 1011 if (!driver) 1012 return ENOMEM; 1013 bzero(driver, sizeof(driver_t)); 1014 driver->name = dvp->pd_name; 1015 driver->methods = pci_compat_methods; 1016 driver->softc = sizeof(struct pci_devinfo *); 1017 driver->priv = dvp; 1018 devclass_add_driver(pci_devclass, driver); 1019 break; 1020 case MOD_UNLOAD: 1021 printf("%s: module unload not supported!\n", dvp->pd_name); 1022 return EOPNOTSUPP; 1023 default: 1024 break; 1025 } 1026 return 0; 1027} 1028 1029/* 1030 * New style pci driver. Parent device is either a pci-host-bridge or a 1031 * pci-pci-bridge. Both kinds are represented by instances of pcib. 1032 */ 1033 1034static void 1035pci_print_verbose(struct pci_devinfo *dinfo) 1036{ 1037 if (bootverbose) { 1038 int i; 1039 pcicfgregs *cfg = &dinfo->cfg; 1040 1041 printf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n", 1042 cfg->vendor, cfg->device, cfg->revid); 1043 printf("\tclass=%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n", 1044 cfg->baseclass, cfg->subclass, cfg->progif, 1045 cfg->hdrtype, cfg->mfdev); 1046 printf("\tsubordinatebus=%x \tsecondarybus=%x\n", 1047 cfg->subordinatebus, cfg->secondarybus); 1048#ifdef PCI_DEBUG 1049 printf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n", 1050 cfg->cmdreg, cfg->statreg, cfg->cachelnsz); 1051 printf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n", 1052 cfg->lattimer, cfg->lattimer * 30, 1053 cfg->mingnt, cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250); 1054#endif /* PCI_DEBUG */ 1055 if (cfg->intpin > 0) 1056 printf("\tintpin=%c, irq=%d\n", cfg->intpin +'a' -1, cfg->intline); 1057 1058 for (i = 0; i < cfg->nummaps; i++) { 1059 pcimap *m = &cfg->map[i]; 1060 printf("\tmap[%d]: type %x, range %2d, base %08x, size %2d\n", 1061 i, m->type, m->ln2range, m->base, m->ln2size); 1062 } 1063 } 1064} 1065 1066static int 1067pci_add_children(device_t dev, int busno) 1068{ 1069 pcicfgregs probe; 1070 int bushigh = busno; 1071 1072#ifdef SIMOS 1073#undef PCI_SLOTMAX 1074#define PCI_SLOTMAX 0 1075#endif 1076 1077 bzero(&probe, sizeof probe); 1078#ifdef __alpha__ 1079 probe.hose = pcib_get_hose(dev); 1080#endif 1081#ifdef __i386__ 1082 probe.hose = 0; 1083#endif 1084 probe.bus = busno; 1085 1086 for (probe.slot = 0; probe.slot <= PCI_SLOTMAX; probe.slot++) { 1087 int pcifunchigh = 0; 1088 for (probe.func = 0; probe.func <= pcifunchigh; probe.func++) { 1089 struct pci_devinfo *dinfo = pci_readcfg(&probe); 1090 if (dinfo != NULL) { 1091 if (dinfo->cfg.mfdev) 1092 pcifunchigh = 7; 1093 1094 pci_print_verbose(dinfo); 1095 dinfo->cfg.dev = 1096 device_add_child(dev, NULL, -1, dinfo); 1097 1098 if (bushigh < dinfo->cfg.subordinatebus) 1099 bushigh = dinfo->cfg.subordinatebus; 1100 if (bushigh < dinfo->cfg.secondarybus) 1101 bushigh = dinfo->cfg.secondarybus; 1102 } 1103 } 1104 } 1105 1106 return bushigh; 1107} 1108 1109static int 1110pci_new_probe(device_t dev) 1111{ 1112 device_set_desc(dev, "PCI bus"); 1113 1114 pci_add_children(dev, device_get_unit(dev)); 1115 1116 return 0; 1117} 1118 1119static void 1120pci_print_child(device_t dev, device_t child) 1121{ 1122 struct pci_devinfo *dinfo; 1123 pcicfgregs *cfg; 1124 1125 dinfo = device_get_ivars(child); 1126 cfg = &dinfo->cfg; 1127 if (cfg->intpin > 0 && cfg->intline != 255) 1128 printf(" irq %d", cfg->intline); 1129 printf(" at device %d.%d", pci_get_slot(child), pci_get_function(child)); 1130 printf(" on %s%d", device_get_name(dev), device_get_unit(dev)); 1131} 1132 1133static void 1134pci_probe_nomatch(device_t dev, device_t child) 1135{ 1136 struct pci_devinfo *dinfo; 1137 pcicfgregs *cfg; 1138 1139 dinfo = device_get_ivars(child); 1140 cfg = &dinfo->cfg; 1141 1142 device_printf(dev, "unknown card %c%c%c%04x (vendor=0x%04x, dev=0x%04x) at %d.%d", 1143 PCI_MFCTR_CHAR0(cfg->vendor), 1144 PCI_MFCTR_CHAR1(cfg->vendor), 1145 PCI_MFCTR_CHAR2(cfg->vendor), 1146 cfg->device, 1147 cfg->vendor, 1148 cfg->device, 1149 pci_get_slot(child), 1150 pci_get_function(child)); 1151 if (cfg->intpin > 0 && cfg->intline != 255) { 1152 printf(" irq %d", cfg->intline); 1153 } 1154 printf("\n"); 1155 1156 return; 1157} 1158 1159static int 1160pci_read_ivar(device_t dev, device_t child, int which, u_long *result) 1161{ 1162 struct pci_devinfo *dinfo; 1163 pcicfgregs *cfg; 1164 1165 dinfo = device_get_ivars(child); 1166 cfg = &dinfo->cfg; 1167 1168 switch (which) { 1169 case PCI_IVAR_SUBVENDOR: 1170 *result = cfg->subvendor; 1171 break; 1172 case PCI_IVAR_SUBDEVICE: 1173 *result = cfg->subdevice; 1174 break; 1175 case PCI_IVAR_VENDOR: 1176 *result = cfg->vendor; 1177 break; 1178 case PCI_IVAR_DEVICE: 1179 *result = cfg->device; 1180 break; 1181 case PCI_IVAR_DEVID: 1182 *result = (cfg->device << 16) | cfg->vendor; 1183 break; 1184 case PCI_IVAR_CLASS: 1185 *result = cfg->baseclass; 1186 break; 1187 case PCI_IVAR_SUBCLASS: 1188 *result = cfg->subclass; 1189 break; 1190 case PCI_IVAR_PROGIF: 1191 *result = cfg->progif; 1192 break; 1193 case PCI_IVAR_REVID: 1194 *result = cfg->revid; 1195 break; 1196 case PCI_IVAR_INTPIN: 1197 *result = cfg->intpin; 1198 break; 1199 case PCI_IVAR_IRQ: 1200 *result = cfg->intline; 1201 break; 1202 case PCI_IVAR_BUS: 1203 *result = cfg->bus; 1204 break; 1205 case PCI_IVAR_SLOT: 1206 *result = cfg->slot; 1207 break; 1208 case PCI_IVAR_FUNCTION: 1209 *result = cfg->func; 1210 break; 1211 case PCI_IVAR_SECONDARYBUS: 1212 *result = cfg->secondarybus; 1213 break; 1214 case PCI_IVAR_SUBORDINATEBUS: 1215 *result = cfg->subordinatebus; 1216 break; 1217 case PCI_IVAR_HOSE: 1218 /* 1219 * Pass up to parent bridge. 1220 */ 1221 *result = pcib_get_hose(dev); 1222 break; 1223 default: 1224 return ENOENT; 1225 } 1226 return 0; 1227} 1228 1229static int 1230pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value) 1231{ 1232 struct pci_devinfo *dinfo; 1233 pcicfgregs *cfg; 1234 1235 dinfo = device_get_ivars(child); 1236 cfg = &dinfo->cfg; 1237 1238 switch (which) { 1239 case PCI_IVAR_SUBVENDOR: 1240 case PCI_IVAR_SUBDEVICE: 1241 case PCI_IVAR_VENDOR: 1242 case PCI_IVAR_DEVICE: 1243 case PCI_IVAR_DEVID: 1244 case PCI_IVAR_CLASS: 1245 case PCI_IVAR_SUBCLASS: 1246 case PCI_IVAR_PROGIF: 1247 case PCI_IVAR_REVID: 1248 case PCI_IVAR_INTPIN: 1249 case PCI_IVAR_IRQ: 1250 case PCI_IVAR_BUS: 1251 case PCI_IVAR_SLOT: 1252 case PCI_IVAR_FUNCTION: 1253 return EINVAL; /* disallow for now */ 1254 1255 case PCI_IVAR_SECONDARYBUS: 1256 cfg->secondarybus = value; 1257 break; 1258 case PCI_IVAR_SUBORDINATEBUS: 1259 cfg->subordinatebus = value; 1260 break; 1261 default: 1262 return ENOENT; 1263 } 1264 return 0; 1265} 1266 1267static int 1268pci_mapno(pcicfgregs *cfg, int reg) 1269{ 1270 int i, nummaps; 1271 pcimap *map; 1272 1273 nummaps = cfg->nummaps; 1274 map = cfg->map; 1275 1276 for (i = 0; i < nummaps; i++) 1277 if (map[i].reg == reg) 1278 return (i); 1279 return (-1); 1280} 1281 1282static int 1283pci_porten(pcicfgregs *cfg) 1284{ 1285 return ((cfg->cmdreg & PCIM_CMD_PORTEN) != 0); 1286} 1287 1288static int 1289pci_isportmap(pcicfgregs *cfg, int map) 1290 1291{ 1292 return ((unsigned)map < cfg->nummaps 1293 && (cfg->map[map].type & PCI_MAPPORT) != 0); 1294} 1295 1296static int 1297pci_memen(pcicfgregs *cfg) 1298{ 1299 return ((cfg->cmdreg & PCIM_CMD_MEMEN) != 0); 1300} 1301 1302static int 1303pci_ismemmap(pcicfgregs *cfg, int map) 1304{ 1305 return ((unsigned)map < cfg->nummaps 1306 && (cfg->map[map].type & PCI_MAPMEM) != 0); 1307} 1308 1309static struct resource * 1310pci_alloc_resource(device_t dev, device_t child, int type, int *rid, 1311 u_long start, u_long end, u_long count, u_int flags) 1312{ 1313 int isdefault; 1314 struct pci_devinfo *dinfo = device_get_ivars(child); 1315 pcicfgregs *cfg = &dinfo->cfg; 1316 struct resource *rv, **rvp = 0; 1317 int map; 1318 1319 isdefault = (device_get_parent(child) == dev 1320 && start == 0UL && end == ~0UL); 1321 1322 switch (type) { 1323 case SYS_RES_IRQ: 1324 if (*rid != 0) 1325 return 0; 1326 if (isdefault && cfg->intline != 255) { 1327 start = cfg->intline; 1328 end = cfg->intline; 1329 count = 1; 1330 } 1331 break; 1332 1333 case SYS_RES_DRQ: /* passthru for child isa */ 1334 break; 1335 1336 case SYS_RES_MEMORY: 1337 if (isdefault) { 1338 map = pci_mapno(cfg, *rid); 1339 if (pci_memen(cfg) && pci_ismemmap(cfg, map)) { 1340 start = cfg->map[map].base; 1341 count = 1 << cfg->map[map].ln2size; 1342 end = start + count; 1343 rvp = &cfg->map[map].res; 1344 } else 1345 return 0; 1346 } 1347 break; 1348 1349 case SYS_RES_IOPORT: 1350 if (isdefault) { 1351 map = pci_mapno(cfg, *rid); 1352 if (pci_porten(cfg) && pci_isportmap(cfg, map)) { 1353 start = cfg->map[map].base; 1354 count = 1 << cfg->map[map].ln2size; 1355 end = start + count; 1356 rvp = &cfg->map[map].res; 1357 } else 1358 return 0; 1359 } 1360 break; 1361 1362 default: 1363 return 0; 1364 } 1365 1366 rv = BUS_ALLOC_RESOURCE(device_get_parent(dev), child, 1367 type, rid, start, end, count, flags); 1368 if (rvp) 1369 *rvp = rv; 1370 1371 return rv; 1372} 1373 1374static int 1375pci_release_resource(device_t dev, device_t child, int type, int rid, 1376 struct resource *r) 1377{ 1378 int rv; 1379 struct pci_devinfo *dinfo = device_get_ivars(child); 1380 pcicfgregs *cfg = &dinfo->cfg; 1381 int map = 0; 1382 1383 switch (type) { 1384 case SYS_RES_IRQ: 1385 if (rid != 0) 1386 return EINVAL; 1387 break; 1388 1389 case SYS_RES_DRQ: /* passthru for child isa */ 1390 break; 1391 1392 case SYS_RES_MEMORY: 1393 case SYS_RES_IOPORT: 1394 /* 1395 * Only check the map registers if this is a direct 1396 * descendant. 1397 */ 1398 if (device_get_parent(child) == dev) 1399 map = pci_mapno(cfg, rid); 1400 else 1401 map = -1; 1402 break; 1403 1404 default: 1405 return (ENOENT); 1406 } 1407 1408 rv = BUS_RELEASE_RESOURCE(device_get_parent(dev), child, type, rid, r); 1409 1410 if (rv == 0) { 1411 switch (type) { 1412 case SYS_RES_IRQ: 1413 cfg->irqres = 0; 1414 break; 1415 1416 case SYS_RES_DRQ: /* passthru for child isa */ 1417 break; 1418 1419 case SYS_RES_MEMORY: 1420 case SYS_RES_IOPORT: 1421 if (map != -1) 1422 cfg->map[map].res = 0; 1423 break; 1424 1425 default: 1426 return ENOENT; 1427 } 1428 } 1429 1430 return rv; 1431} 1432 1433static u_int32_t 1434pci_read_config_method(device_t dev, device_t child, int reg, int width) 1435{ 1436 struct pci_devinfo *dinfo = device_get_ivars(child); 1437 pcicfgregs *cfg = &dinfo->cfg; 1438 return pci_cfgread(cfg, reg, width); 1439} 1440 1441static void 1442pci_write_config_method(device_t dev, device_t child, int reg, 1443 u_int32_t val, int width) 1444{ 1445 struct pci_devinfo *dinfo = device_get_ivars(child); 1446 pcicfgregs *cfg = &dinfo->cfg; 1447 pci_cfgwrite(cfg, reg, val, width); 1448} 1449 1450static int 1451pci_modevent(module_t mod, int what, void *arg) 1452{ 1453 switch (what) { 1454 case MOD_LOAD: 1455 STAILQ_INIT(&pci_devq); 1456 break; 1457 1458 case MOD_UNLOAD: 1459 break; 1460 } 1461 1462 return 0; 1463} 1464 1465static device_method_t pci_methods[] = { 1466 /* Device interface */ 1467 DEVMETHOD(device_probe, pci_new_probe), 1468 DEVMETHOD(device_attach, bus_generic_attach), 1469 DEVMETHOD(device_shutdown, bus_generic_shutdown), 1470 DEVMETHOD(device_suspend, bus_generic_suspend), 1471 DEVMETHOD(device_resume, bus_generic_resume), 1472 1473 /* Bus interface */ 1474 DEVMETHOD(bus_print_child, pci_print_child), 1475 DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch), 1476 DEVMETHOD(bus_read_ivar, pci_read_ivar), 1477 DEVMETHOD(bus_write_ivar, pci_write_ivar), 1478 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 1479 DEVMETHOD(bus_alloc_resource, pci_alloc_resource), 1480 DEVMETHOD(bus_release_resource, pci_release_resource), 1481 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 1482 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 1483 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 1484 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 1485 1486 /* PCI interface */ 1487 DEVMETHOD(pci_read_config, pci_read_config_method), 1488 DEVMETHOD(pci_write_config, pci_write_config_method), 1489 1490 { 0, 0 } 1491}; 1492 1493static driver_t pci_driver = { 1494 "pci", 1495 pci_methods, 1496 1, /* no softc */ 1497}; 1498 1499DRIVER_MODULE(pci, pcib, pci_driver, pci_devclass, pci_modevent, 0); 1500