pci.c revision 119656
1/* 2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 3 * Copyright (c) 2000, Michael Smith <msmith@freebsd.org> 4 * Copyright (c) 2000, BSDi 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * $FreeBSD: head/sys/dev/pci/pci.c 119656 2003-09-01 15:01:49Z dfr $ 29 * 30 */ 31 32#include "opt_bus.h" 33 34#include <sys/param.h> 35#include <sys/systm.h> 36#include <sys/malloc.h> 37#include <sys/module.h> 38#include <sys/linker.h> 39#include <sys/fcntl.h> 40#include <sys/conf.h> 41#include <sys/kernel.h> 42#include <sys/queue.h> 43#include <sys/sysctl.h> 44#include <sys/types.h> 45 46#include <vm/vm.h> 47#include <vm/pmap.h> 48#include <vm/vm_extern.h> 49 50#include <sys/bus.h> 51#include <machine/bus.h> 52#include <sys/rman.h> 53#include <machine/resource.h> 54 55#include <sys/pciio.h> 56#include <dev/pci/pcireg.h> 57#include <dev/pci/pcivar.h> 58#include <dev/pci/pci_private.h> 59 60#include "pcib_if.h" 61#include "pci_if.h" 62 63static uint32_t pci_mapbase(unsigned mapreg); 64static int pci_maptype(unsigned mapreg); 65static int pci_mapsize(unsigned testval); 66static int pci_maprange(unsigned mapreg); 67static void pci_fixancient(pcicfgregs *cfg); 68 69static int pci_porten(device_t pcib, int b, int s, int f); 70static int pci_memen(device_t pcib, int b, int s, int f); 71static int pci_add_map(device_t pcib, int b, int s, int f, int reg, 72 struct resource_list *rl); 73static void pci_add_resources(device_t pcib, device_t bus, 74 device_t dev); 75static int pci_probe(device_t dev); 76static int pci_attach(device_t dev); 77static void pci_load_vendor_data(void); 78static int pci_describe_parse_line(char **ptr, int *vendor, 79 int *device, char **desc); 80static char *pci_describe_device(device_t dev); 81static int pci_modevent(module_t mod, int what, void *arg); 82static void pci_hdrtypedata(device_t pcib, int b, int s, int f, 83 pcicfgregs *cfg); 84static void pci_read_extcap(device_t pcib, pcicfgregs *cfg); 85 86static device_method_t pci_methods[] = { 87 /* Device interface */ 88 DEVMETHOD(device_probe, pci_probe), 89 DEVMETHOD(device_attach, pci_attach), 90 DEVMETHOD(device_shutdown, bus_generic_shutdown), 91 DEVMETHOD(device_suspend, bus_generic_suspend), 92 DEVMETHOD(device_resume, bus_generic_resume), 93 94 /* Bus interface */ 95 DEVMETHOD(bus_print_child, pci_print_child), 96 DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch), 97 DEVMETHOD(bus_read_ivar, pci_read_ivar), 98 DEVMETHOD(bus_write_ivar, pci_write_ivar), 99 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 100 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 101 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 102 103 DEVMETHOD(bus_get_resource_list,pci_get_resource_list), 104 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource), 105 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource), 106 DEVMETHOD(bus_delete_resource, pci_delete_resource), 107 DEVMETHOD(bus_alloc_resource, pci_alloc_resource), 108 DEVMETHOD(bus_release_resource, bus_generic_rl_release_resource), 109 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 110 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 111 DEVMETHOD(bus_child_pnpinfo_str, pci_child_pnpinfo_str_method), 112 DEVMETHOD(bus_child_location_str, pci_child_location_str_method), 113 114 /* PCI interface */ 115 DEVMETHOD(pci_read_config, pci_read_config_method), 116 DEVMETHOD(pci_write_config, pci_write_config_method), 117 DEVMETHOD(pci_enable_busmaster, pci_enable_busmaster_method), 118 DEVMETHOD(pci_disable_busmaster, pci_disable_busmaster_method), 119 DEVMETHOD(pci_enable_io, pci_enable_io_method), 120 DEVMETHOD(pci_disable_io, pci_disable_io_method), 121 DEVMETHOD(pci_get_powerstate, pci_get_powerstate_method), 122 DEVMETHOD(pci_set_powerstate, pci_set_powerstate_method), 123 DEVMETHOD(pci_assign_interrupt, pci_assign_interrupt_method), 124 125 { 0, 0 } 126}; 127 128static driver_t pci_driver = { 129 "pci", 130 pci_methods, 131 0, /* no softc */ 132}; 133 134devclass_t pci_devclass; 135DRIVER_MODULE(pci, pcib, pci_driver, pci_devclass, pci_modevent, 0); 136MODULE_VERSION(pci, 1); 137 138static char *pci_vendordata; 139static size_t pci_vendordata_size; 140 141 142struct pci_quirk { 143 uint32_t devid; /* Vendor/device of the card */ 144 int type; 145#define PCI_QUIRK_MAP_REG 1 /* PCI map register in weird place */ 146 int arg1; 147 int arg2; 148}; 149 150struct pci_quirk pci_quirks[] = { 151 /* The Intel 82371AB and 82443MX has a map register at offset 0x90. */ 152 { 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 153 { 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 154 /* As does the Serverworks OSB4 (the SMBus mapping register) */ 155 { 0x02001166, PCI_QUIRK_MAP_REG, 0x90, 0 }, 156 157 { 0 } 158}; 159 160/* map register information */ 161#define PCI_MAPMEM 0x01 /* memory map */ 162#define PCI_MAPMEMP 0x02 /* prefetchable memory map */ 163#define PCI_MAPPORT 0x04 /* port map */ 164 165struct devlist pci_devq; 166uint32_t pci_generation; 167uint32_t pci_numdevs = 0; 168 169/* sysctl vars */ 170SYSCTL_NODE(_hw, OID_AUTO, pci, CTLFLAG_RD, 0, "PCI bus tuning parameters"); 171 172static int pci_enable_io_modes = 1; 173TUNABLE_INT("hw.pci.enable_io_modes", (int *)&pci_enable_io_modes); 174SYSCTL_INT(_hw_pci, OID_AUTO, enable_io_modes, CTLFLAG_RW, 175 &pci_enable_io_modes, 1, 176 "Enable I/O and memory bits in the config register. Some BIOSes do not\n\ 177enable these bits correctly. We'd like to do this all the time, but there\n\ 178are some peripherals that this causes problems with."); 179 180/* Find a device_t by bus/slot/function */ 181 182device_t 183pci_find_bsf(uint8_t bus, uint8_t slot, uint8_t func) 184{ 185 struct pci_devinfo *dinfo; 186 187 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 188 if ((dinfo->cfg.bus == bus) && 189 (dinfo->cfg.slot == slot) && 190 (dinfo->cfg.func == func)) { 191 return (dinfo->cfg.dev); 192 } 193 } 194 195 return (NULL); 196} 197 198/* Find a device_t by vendor/device ID */ 199 200device_t 201pci_find_device(uint16_t vendor, uint16_t device) 202{ 203 struct pci_devinfo *dinfo; 204 205 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 206 if ((dinfo->cfg.vendor == vendor) && 207 (dinfo->cfg.device == device)) { 208 return (dinfo->cfg.dev); 209 } 210 } 211 212 return (NULL); 213} 214 215/* return base address of memory or port map */ 216 217static uint32_t 218pci_mapbase(unsigned mapreg) 219{ 220 int mask = 0x03; 221 if ((mapreg & 0x01) == 0) 222 mask = 0x0f; 223 return (mapreg & ~mask); 224} 225 226/* return map type of memory or port map */ 227 228static int 229pci_maptype(unsigned mapreg) 230{ 231 static uint8_t maptype[0x10] = { 232 PCI_MAPMEM, PCI_MAPPORT, 233 PCI_MAPMEM, 0, 234 PCI_MAPMEM, PCI_MAPPORT, 235 0, 0, 236 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT, 237 PCI_MAPMEM|PCI_MAPMEMP, 0, 238 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT, 239 0, 0, 240 }; 241 242 return maptype[mapreg & 0x0f]; 243} 244 245/* return log2 of map size decoded for memory or port map */ 246 247static int 248pci_mapsize(unsigned testval) 249{ 250 int ln2size; 251 252 testval = pci_mapbase(testval); 253 ln2size = 0; 254 if (testval != 0) { 255 while ((testval & 1) == 0) 256 { 257 ln2size++; 258 testval >>= 1; 259 } 260 } 261 return (ln2size); 262} 263 264/* return log2 of address range supported by map register */ 265 266static int 267pci_maprange(unsigned mapreg) 268{ 269 int ln2range = 0; 270 switch (mapreg & 0x07) { 271 case 0x00: 272 case 0x01: 273 case 0x05: 274 ln2range = 32; 275 break; 276 case 0x02: 277 ln2range = 20; 278 break; 279 case 0x04: 280 ln2range = 64; 281 break; 282 } 283 return (ln2range); 284} 285 286/* adjust some values from PCI 1.0 devices to match 2.0 standards ... */ 287 288static void 289pci_fixancient(pcicfgregs *cfg) 290{ 291 if (cfg->hdrtype != 0) 292 return; 293 294 /* PCI to PCI bridges use header type 1 */ 295 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI) 296 cfg->hdrtype = 1; 297} 298 299/* extract header type specific config data */ 300 301static void 302pci_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg) 303{ 304#define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 305 switch (cfg->hdrtype) { 306 case 0: 307 cfg->subvendor = REG(PCIR_SUBVEND_0, 2); 308 cfg->subdevice = REG(PCIR_SUBDEV_0, 2); 309 cfg->nummaps = PCI_MAXMAPS_0; 310 break; 311 case 1: 312 cfg->subvendor = REG(PCIR_SUBVEND_1, 2); 313 cfg->subdevice = REG(PCIR_SUBDEV_1, 2); 314 cfg->nummaps = PCI_MAXMAPS_1; 315 break; 316 case 2: 317 cfg->subvendor = REG(PCIR_SUBVEND_2, 2); 318 cfg->subdevice = REG(PCIR_SUBDEV_2, 2); 319 cfg->nummaps = PCI_MAXMAPS_2; 320 break; 321 } 322#undef REG 323} 324 325/* read configuration header into pcicfgregs structure */ 326 327struct pci_devinfo * 328pci_read_device(device_t pcib, int b, int s, int f, size_t size) 329{ 330#define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 331 pcicfgregs *cfg = NULL; 332 struct pci_devinfo *devlist_entry; 333 struct devlist *devlist_head; 334 335 devlist_head = &pci_devq; 336 337 devlist_entry = NULL; 338 339 if (REG(PCIR_DEVVENDOR, 4) != -1) { 340 devlist_entry = malloc(size, M_DEVBUF, M_WAITOK | M_ZERO); 341 if (devlist_entry == NULL) 342 return (NULL); 343 344 cfg = &devlist_entry->cfg; 345 346 cfg->bus = b; 347 cfg->slot = s; 348 cfg->func = f; 349 cfg->vendor = REG(PCIR_VENDOR, 2); 350 cfg->device = REG(PCIR_DEVICE, 2); 351 cfg->cmdreg = REG(PCIR_COMMAND, 2); 352 cfg->statreg = REG(PCIR_STATUS, 2); 353 cfg->baseclass = REG(PCIR_CLASS, 1); 354 cfg->subclass = REG(PCIR_SUBCLASS, 1); 355 cfg->progif = REG(PCIR_PROGIF, 1); 356 cfg->revid = REG(PCIR_REVID, 1); 357 cfg->hdrtype = REG(PCIR_HDRTYPE, 1); 358 cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1); 359 cfg->lattimer = REG(PCIR_LATTIMER, 1); 360 cfg->intpin = REG(PCIR_INTPIN, 1); 361 cfg->intline = REG(PCIR_INTLINE, 1); 362 363 cfg->mingnt = REG(PCIR_MINGNT, 1); 364 cfg->maxlat = REG(PCIR_MAXLAT, 1); 365 366 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0; 367 cfg->hdrtype &= ~PCIM_MFDEV; 368 369 pci_fixancient(cfg); 370 pci_hdrtypedata(pcib, b, s, f, cfg); 371 372 if (REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT) 373 pci_read_extcap(pcib, cfg); 374 375 STAILQ_INSERT_TAIL(devlist_head, devlist_entry, pci_links); 376 377 devlist_entry->conf.pc_sel.pc_bus = cfg->bus; 378 devlist_entry->conf.pc_sel.pc_dev = cfg->slot; 379 devlist_entry->conf.pc_sel.pc_func = cfg->func; 380 devlist_entry->conf.pc_hdr = cfg->hdrtype; 381 382 devlist_entry->conf.pc_subvendor = cfg->subvendor; 383 devlist_entry->conf.pc_subdevice = cfg->subdevice; 384 devlist_entry->conf.pc_vendor = cfg->vendor; 385 devlist_entry->conf.pc_device = cfg->device; 386 387 devlist_entry->conf.pc_class = cfg->baseclass; 388 devlist_entry->conf.pc_subclass = cfg->subclass; 389 devlist_entry->conf.pc_progif = cfg->progif; 390 devlist_entry->conf.pc_revid = cfg->revid; 391 392 pci_numdevs++; 393 pci_generation++; 394 } 395 return (devlist_entry); 396#undef REG 397} 398 399static void 400pci_read_extcap(device_t pcib, pcicfgregs *cfg) 401{ 402#define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w) 403 int ptr, nextptr, ptrptr; 404 405 switch (cfg->hdrtype) { 406 case 0: 407 ptrptr = 0x34; 408 break; 409 case 2: 410 ptrptr = 0x14; 411 break; 412 default: 413 return; /* no extended capabilities support */ 414 } 415 nextptr = REG(ptrptr, 1); /* sanity check? */ 416 417 /* 418 * Read capability entries. 419 */ 420 while (nextptr != 0) { 421 /* Sanity check */ 422 if (nextptr > 255) { 423 printf("illegal PCI extended capability offset %d\n", 424 nextptr); 425 return; 426 } 427 /* Find the next entry */ 428 ptr = nextptr; 429 nextptr = REG(ptr + 1, 1); 430 431 /* Process this entry */ 432 switch (REG(ptr, 1)) { 433 case 0x01: /* PCI power management */ 434 if (cfg->pp_cap == 0) { 435 cfg->pp_cap = REG(ptr + PCIR_POWER_CAP, 2); 436 cfg->pp_status = ptr + PCIR_POWER_STATUS; 437 cfg->pp_pmcsr = ptr + PCIR_POWER_PMCSR; 438 if ((nextptr - ptr) > PCIR_POWER_DATA) 439 cfg->pp_data = ptr + PCIR_POWER_DATA; 440 } 441 break; 442 default: 443 break; 444 } 445 } 446#undef REG 447} 448 449/* free pcicfgregs structure and all depending data structures */ 450 451int 452pci_freecfg(struct pci_devinfo *dinfo) 453{ 454 struct devlist *devlist_head; 455 456 devlist_head = &pci_devq; 457 458 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links); 459 free(dinfo, M_DEVBUF); 460 461 /* increment the generation count */ 462 pci_generation++; 463 464 /* we're losing one device */ 465 pci_numdevs--; 466 return (0); 467} 468 469/* 470 * PCI power manangement 471 */ 472int 473pci_set_powerstate_method(device_t dev, device_t child, int state) 474{ 475 struct pci_devinfo *dinfo = device_get_ivars(child); 476 pcicfgregs *cfg = &dinfo->cfg; 477 uint16_t status; 478 int result; 479 480 if (cfg->pp_cap != 0) { 481 status = PCI_READ_CONFIG(dev, child, cfg->pp_status, 2) & ~PCIM_PSTAT_DMASK; 482 result = 0; 483 switch (state) { 484 case PCI_POWERSTATE_D0: 485 status |= PCIM_PSTAT_D0; 486 break; 487 case PCI_POWERSTATE_D1: 488 if (cfg->pp_cap & PCIM_PCAP_D1SUPP) { 489 status |= PCIM_PSTAT_D1; 490 } else { 491 result = EOPNOTSUPP; 492 } 493 break; 494 case PCI_POWERSTATE_D2: 495 if (cfg->pp_cap & PCIM_PCAP_D2SUPP) { 496 status |= PCIM_PSTAT_D2; 497 } else { 498 result = EOPNOTSUPP; 499 } 500 break; 501 case PCI_POWERSTATE_D3: 502 status |= PCIM_PSTAT_D3; 503 break; 504 default: 505 result = EINVAL; 506 } 507 if (result == 0) 508 PCI_WRITE_CONFIG(dev, child, cfg->pp_status, status, 2); 509 } else { 510 result = ENXIO; 511 } 512 return(result); 513} 514 515int 516pci_get_powerstate_method(device_t dev, device_t child) 517{ 518 struct pci_devinfo *dinfo = device_get_ivars(child); 519 pcicfgregs *cfg = &dinfo->cfg; 520 uint16_t status; 521 int result; 522 523 if (cfg->pp_cap != 0) { 524 status = PCI_READ_CONFIG(dev, child, cfg->pp_status, 2); 525 switch (status & PCIM_PSTAT_DMASK) { 526 case PCIM_PSTAT_D0: 527 result = PCI_POWERSTATE_D0; 528 break; 529 case PCIM_PSTAT_D1: 530 result = PCI_POWERSTATE_D1; 531 break; 532 case PCIM_PSTAT_D2: 533 result = PCI_POWERSTATE_D2; 534 break; 535 case PCIM_PSTAT_D3: 536 result = PCI_POWERSTATE_D3; 537 break; 538 default: 539 result = PCI_POWERSTATE_UNKNOWN; 540 break; 541 } 542 } else { 543 /* No support, device is always at D0 */ 544 result = PCI_POWERSTATE_D0; 545 } 546 return(result); 547} 548 549/* 550 * Some convenience functions for PCI device drivers. 551 */ 552 553static __inline void 554pci_set_command_bit(device_t dev, device_t child, uint16_t bit) 555{ 556 uint16_t command; 557 558 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 559 command |= bit; 560 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 561} 562 563static __inline void 564pci_clear_command_bit(device_t dev, device_t child, uint16_t bit) 565{ 566 uint16_t command; 567 568 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 569 command &= ~bit; 570 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 571} 572 573int 574pci_enable_busmaster_method(device_t dev, device_t child) 575{ 576 pci_set_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 577 return (0); 578} 579 580int 581pci_disable_busmaster_method(device_t dev, device_t child) 582{ 583 pci_clear_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 584 return (0); 585} 586 587int 588pci_enable_io_method(device_t dev, device_t child, int space) 589{ 590 uint16_t command; 591 uint16_t bit; 592 char *error; 593 594 bit = 0; 595 error = NULL; 596 597 switch(space) { 598 case SYS_RES_IOPORT: 599 bit = PCIM_CMD_PORTEN; 600 error = "port"; 601 break; 602 case SYS_RES_MEMORY: 603 bit = PCIM_CMD_MEMEN; 604 error = "memory"; 605 break; 606 default: 607 return (EINVAL); 608 } 609 pci_set_command_bit(dev, child, bit); 610 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 611 if (command & bit) 612 return (0); 613 device_printf(child, "failed to enable %s mapping!\n", error); 614 return (ENXIO); 615} 616 617int 618pci_disable_io_method(device_t dev, device_t child, int space) 619{ 620 uint16_t command; 621 uint16_t bit; 622 char *error; 623 624 bit = 0; 625 error = NULL; 626 627 switch(space) { 628 case SYS_RES_IOPORT: 629 bit = PCIM_CMD_PORTEN; 630 error = "port"; 631 break; 632 case SYS_RES_MEMORY: 633 bit = PCIM_CMD_MEMEN; 634 error = "memory"; 635 break; 636 default: 637 return (EINVAL); 638 } 639 pci_clear_command_bit(dev, child, bit); 640 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 641 if (command & bit) { 642 device_printf(child, "failed to disable %s mapping!\n", error); 643 return (ENXIO); 644 } 645 return (0); 646} 647 648/* 649 * New style pci driver. Parent device is either a pci-host-bridge or a 650 * pci-pci-bridge. Both kinds are represented by instances of pcib. 651 */ 652 653void 654pci_print_verbose(struct pci_devinfo *dinfo) 655{ 656 if (bootverbose) { 657 pcicfgregs *cfg = &dinfo->cfg; 658 659 printf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n", 660 cfg->vendor, cfg->device, cfg->revid); 661 printf("\tbus=%d, slot=%d, func=%d\n", 662 cfg->bus, cfg->slot, cfg->func); 663 printf("\tclass=%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n", 664 cfg->baseclass, cfg->subclass, cfg->progif, cfg->hdrtype, 665 cfg->mfdev); 666 printf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n", 667 cfg->cmdreg, cfg->statreg, cfg->cachelnsz); 668 printf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n", 669 cfg->lattimer, cfg->lattimer * 30, cfg->mingnt, 670 cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250); 671 if (cfg->intpin > 0) 672 printf("\tintpin=%c, irq=%d\n", 673 cfg->intpin +'a' -1, cfg->intline); 674 if (cfg->pp_cap) { 675 uint16_t status; 676 677 status = pci_read_config(cfg->dev, cfg->pp_status, 2); 678 printf("\tpowerspec %d supports D0%s%s D3 current D%d\n", 679 cfg->pp_cap & PCIM_PCAP_SPEC, 680 cfg->pp_cap & PCIM_PCAP_D1SUPP ? " D1" : "", 681 cfg->pp_cap & PCIM_PCAP_D2SUPP ? " D2" : "", 682 status & PCIM_PSTAT_DMASK); 683 } 684 } 685} 686 687static int 688pci_porten(device_t pcib, int b, int s, int f) 689{ 690 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2) 691 & PCIM_CMD_PORTEN) != 0; 692} 693 694static int 695pci_memen(device_t pcib, int b, int s, int f) 696{ 697 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2) 698 & PCIM_CMD_MEMEN) != 0; 699} 700 701/* 702 * Add a resource based on a pci map register. Return 1 if the map 703 * register is a 32bit map register or 2 if it is a 64bit register. 704 */ 705static int 706pci_add_map(device_t pcib, int b, int s, int f, int reg, 707 struct resource_list *rl) 708{ 709 uint32_t map; 710 uint64_t base; 711 uint8_t ln2size; 712 uint8_t ln2range; 713 uint32_t testval; 714 uint16_t cmd; 715 int type; 716 717 map = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4); 718 719 if (map == 0 || map == 0xffffffff) 720 return (1); /* skip invalid entry */ 721 722 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, 0xffffffff, 4); 723 testval = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4); 724 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, map, 4); 725 726 base = pci_mapbase(map); 727 if (pci_maptype(map) & PCI_MAPMEM) 728 type = SYS_RES_MEMORY; 729 else 730 type = SYS_RES_IOPORT; 731 ln2size = pci_mapsize(testval); 732 ln2range = pci_maprange(testval); 733 if (ln2range == 64) { 734 /* Read the other half of a 64bit map register */ 735 base |= (uint64_t) PCIB_READ_CONFIG(pcib, b, s, f, reg + 4, 4) << 32; 736 } 737 738 if (bootverbose) { 739 printf("\tmap[%02x]: type %x, range %2d, base %08x, size %2d", 740 reg, pci_maptype(map), ln2range, 741 (unsigned int) base, ln2size); 742 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) 743 printf(", port disabled\n"); 744 else if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) 745 printf(", memory disabled\n"); 746 else 747 printf(", enabled\n"); 748 } 749 750 /* 751 * This code theoretically does the right thing, but has 752 * undesirable side effects in some cases where 753 * peripherals respond oddly to having these bits 754 * enabled. Leave them alone by default. 755 */ 756 if (pci_enable_io_modes) { 757 /* Turn on resources that have been left off by a lazy BIOS */ 758 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) { 759 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2); 760 cmd |= PCIM_CMD_PORTEN; 761 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2); 762 } 763 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) { 764 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2); 765 cmd |= PCIM_CMD_MEMEN; 766 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2); 767 } 768 } else { 769 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) 770 return (1); 771 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) 772 return (1); 773 } 774 resource_list_add(rl, type, reg, base, base + (1 << ln2size) - 1, 775 (1 << ln2size)); 776 777 return ((ln2range == 64) ? 2 : 1); 778} 779 780static void 781pci_add_resources(device_t pcib, device_t bus, device_t dev) 782{ 783 struct pci_devinfo *dinfo = device_get_ivars(dev); 784 pcicfgregs *cfg = &dinfo->cfg; 785 struct resource_list *rl = &dinfo->resources; 786 struct pci_quirk *q; 787 int b, i, irq, f, s; 788 789 b = cfg->bus; 790 s = cfg->slot; 791 f = cfg->func; 792 for (i = 0; i < cfg->nummaps;) { 793 i += pci_add_map(pcib, b, s, f, PCIR_MAPS + i*4, rl); 794 } 795 796 for (q = &pci_quirks[0]; q->devid; q++) { 797 if (q->devid == ((cfg->device << 16) | cfg->vendor) 798 && q->type == PCI_QUIRK_MAP_REG) 799 pci_add_map(pcib, b, s, f, q->arg1, rl); 800 } 801 802 if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline)) { 803#if defined(__ia64__) || (defined(__i386__) && !defined(SMP)) 804 /* 805 * Try to re-route interrupts. Sometimes the BIOS or 806 * firmware may leave bogus values in these registers. 807 * If the re-route fails, then just stick with what we 808 * have. 809 */ 810 irq = PCI_ASSIGN_INTERRUPT(bus, dev); 811 if (PCI_INTERRUPT_VALID(irq)) { 812 pci_write_config(dev, PCIR_INTLINE, irq, 1); 813 cfg->intline = irq; 814 } else 815#endif 816 irq = cfg->intline; 817 resource_list_add(rl, SYS_RES_IRQ, 0, irq, irq, 1); 818 } 819} 820 821void 822pci_add_children(device_t dev, int busno, size_t dinfo_size) 823{ 824#define REG(n, w) PCIB_READ_CONFIG(pcib, busno, s, f, n, w) 825 device_t pcib = device_get_parent(dev); 826 struct pci_devinfo *dinfo; 827 int maxslots; 828 int s, f, pcifunchigh; 829 uint8_t hdrtype; 830 831 KASSERT(dinfo_size >= sizeof(struct pci_devinfo), 832 ("dinfo_size too small")); 833 maxslots = PCIB_MAXSLOTS(pcib); 834 for (s = 0; s <= maxslots; s++) { 835 pcifunchigh = 0; 836 f = 0; 837 hdrtype = REG(PCIR_HDRTYPE, 1); 838 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE) 839 continue; 840 if (hdrtype & PCIM_MFDEV) 841 pcifunchigh = PCI_FUNCMAX; 842 for (f = 0; f <= pcifunchigh; f++) { 843 dinfo = pci_read_device(pcib, busno, s, f, dinfo_size); 844 if (dinfo != NULL) { 845 pci_add_child(dev, dinfo); 846 } 847 } 848 } 849#undef REG 850} 851 852void 853pci_add_child(device_t bus, struct pci_devinfo *dinfo) 854{ 855 device_t pcib; 856 857 pcib = device_get_parent(bus); 858 dinfo->cfg.dev = device_add_child(bus, NULL, -1); 859 device_set_ivars(dinfo->cfg.dev, dinfo); 860 pci_add_resources(pcib, bus, dinfo->cfg.dev); 861 pci_print_verbose(dinfo); 862} 863 864static int 865pci_probe(device_t dev) 866{ 867 868 device_set_desc(dev, "PCI bus"); 869 870 /* Allow other subclasses to override this driver. */ 871 return (-1000); 872} 873 874static int 875pci_attach(device_t dev) 876{ 877 int busno; 878 879 /* 880 * Since there can be multiple independantly numbered PCI 881 * busses on some large alpha systems, we can't use the unit 882 * number to decide what bus we are probing. We ask the parent 883 * pcib what our bus number is. 884 */ 885 busno = pcib_get_bus(dev); 886 if (bootverbose) 887 device_printf(dev, "physical bus=%d\n", busno); 888 889 pci_add_children(dev, busno, sizeof(struct pci_devinfo)); 890 891 return (bus_generic_attach(dev)); 892} 893 894static void 895pci_load_vendor_data(void) 896{ 897 caddr_t vendordata, info; 898 899 if ((vendordata = preload_search_by_type("pci_vendor_data")) != NULL) { 900 info = preload_search_info(vendordata, MODINFO_ADDR); 901 pci_vendordata = *(char **)info; 902 info = preload_search_info(vendordata, MODINFO_SIZE); 903 pci_vendordata_size = *(size_t *)info; 904 /* terminate the database */ 905 pci_vendordata[pci_vendordata_size] = '\n'; 906 } 907} 908 909int 910pci_print_child(device_t dev, device_t child) 911{ 912 struct pci_devinfo *dinfo; 913 struct resource_list *rl; 914 int retval = 0; 915 916 dinfo = device_get_ivars(child); 917 rl = &dinfo->resources; 918 919 retval += bus_print_child_header(dev, child); 920 921 retval += resource_list_print_type(rl, "port", SYS_RES_IOPORT, "%#lx"); 922 retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#lx"); 923 retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%ld"); 924 if (device_get_flags(dev)) 925 retval += printf(" flags %#x", device_get_flags(dev)); 926 927 retval += printf(" at device %d.%d", pci_get_slot(child), 928 pci_get_function(child)); 929 930 retval += bus_print_child_footer(dev, child); 931 932 return (retval); 933} 934 935static struct 936{ 937 int class; 938 int subclass; 939 char *desc; 940} pci_nomatch_tab[] = { 941 {PCIC_OLD, -1, "old"}, 942 {PCIC_OLD, PCIS_OLD_NONVGA, "non-VGA display device"}, 943 {PCIC_OLD, PCIS_OLD_VGA, "VGA-compatible display device"}, 944 {PCIC_STORAGE, -1, "mass storage"}, 945 {PCIC_STORAGE, PCIS_STORAGE_SCSI, "SCSI"}, 946 {PCIC_STORAGE, PCIS_STORAGE_IDE, "ATA"}, 947 {PCIC_STORAGE, PCIS_STORAGE_FLOPPY, "floppy disk"}, 948 {PCIC_STORAGE, PCIS_STORAGE_IPI, "IPI"}, 949 {PCIC_STORAGE, PCIS_STORAGE_RAID, "RAID"}, 950 {PCIC_NETWORK, -1, "network"}, 951 {PCIC_NETWORK, PCIS_NETWORK_ETHERNET, "ethernet"}, 952 {PCIC_NETWORK, PCIS_NETWORK_TOKENRING, "token ring"}, 953 {PCIC_NETWORK, PCIS_NETWORK_FDDI, "fddi"}, 954 {PCIC_NETWORK, PCIS_NETWORK_ATM, "ATM"}, 955 {PCIC_DISPLAY, -1, "display"}, 956 {PCIC_DISPLAY, PCIS_DISPLAY_VGA, "VGA"}, 957 {PCIC_DISPLAY, PCIS_DISPLAY_XGA, "XGA"}, 958 {PCIC_MULTIMEDIA, -1, "multimedia"}, 959 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_VIDEO, "video"}, 960 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_AUDIO, "audio"}, 961 {PCIC_MEMORY, -1, "memory"}, 962 {PCIC_MEMORY, PCIS_MEMORY_RAM, "RAM"}, 963 {PCIC_MEMORY, PCIS_MEMORY_FLASH, "flash"}, 964 {PCIC_BRIDGE, -1, "bridge"}, 965 {PCIC_BRIDGE, PCIS_BRIDGE_HOST, "HOST-PCI"}, 966 {PCIC_BRIDGE, PCIS_BRIDGE_ISA, "PCI-ISA"}, 967 {PCIC_BRIDGE, PCIS_BRIDGE_EISA, "PCI-EISA"}, 968 {PCIC_BRIDGE, PCIS_BRIDGE_MCA, "PCI-MCA"}, 969 {PCIC_BRIDGE, PCIS_BRIDGE_PCI, "PCI-PCI"}, 970 {PCIC_BRIDGE, PCIS_BRIDGE_PCMCIA, "PCI-PCMCIA"}, 971 {PCIC_BRIDGE, PCIS_BRIDGE_NUBUS, "PCI-NuBus"}, 972 {PCIC_BRIDGE, PCIS_BRIDGE_CARDBUS, "PCI-CardBus"}, 973 {PCIC_BRIDGE, PCIS_BRIDGE_OTHER, "PCI-unknown"}, 974 {PCIC_SIMPLECOMM, -1, "simple comms"}, 975 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_UART, "UART"}, /* could detect 16550 */ 976 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_PAR, "parallel port"}, 977 {PCIC_BASEPERIPH, -1, "base peripheral"}, 978 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PIC, "interrupt controller"}, 979 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_DMA, "DMA controller"}, 980 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_TIMER, "timer"}, 981 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_RTC, "realtime clock"}, 982 {PCIC_INPUTDEV, -1, "input device"}, 983 {PCIC_INPUTDEV, PCIS_INPUTDEV_KEYBOARD, "keyboard"}, 984 {PCIC_INPUTDEV, PCIS_INPUTDEV_DIGITIZER,"digitizer"}, 985 {PCIC_INPUTDEV, PCIS_INPUTDEV_MOUSE, "mouse"}, 986 {PCIC_DOCKING, -1, "docking station"}, 987 {PCIC_PROCESSOR, -1, "processor"}, 988 {PCIC_SERIALBUS, -1, "serial bus"}, 989 {PCIC_SERIALBUS, PCIS_SERIALBUS_FW, "FireWire"}, 990 {PCIC_SERIALBUS, PCIS_SERIALBUS_ACCESS, "AccessBus"}, 991 {PCIC_SERIALBUS, PCIS_SERIALBUS_SSA, "SSA"}, 992 {PCIC_SERIALBUS, PCIS_SERIALBUS_USB, "USB"}, 993 {PCIC_SERIALBUS, PCIS_SERIALBUS_FC, "Fibre Channel"}, 994 {PCIC_SERIALBUS, PCIS_SERIALBUS_SMBUS, "SMBus"}, 995 {0, 0, NULL} 996}; 997 998void 999pci_probe_nomatch(device_t dev, device_t child) 1000{ 1001 int i; 1002 char *cp, *scp, *device; 1003 1004 /* 1005 * Look for a listing for this device in a loaded device database. 1006 */ 1007 if ((device = pci_describe_device(child)) != NULL) { 1008 device_printf(dev, "<%s>", device); 1009 free(device, M_DEVBUF); 1010 } else { 1011 /* 1012 * Scan the class/subclass descriptions for a general 1013 * description. 1014 */ 1015 cp = "unknown"; 1016 scp = NULL; 1017 for (i = 0; pci_nomatch_tab[i].desc != NULL; i++) { 1018 if (pci_nomatch_tab[i].class == pci_get_class(child)) { 1019 if (pci_nomatch_tab[i].subclass == -1) { 1020 cp = pci_nomatch_tab[i].desc; 1021 } else if (pci_nomatch_tab[i].subclass == 1022 pci_get_subclass(child)) { 1023 scp = pci_nomatch_tab[i].desc; 1024 } 1025 } 1026 } 1027 device_printf(dev, "<%s%s%s>", 1028 cp ? cp : "", 1029 ((cp != NULL) && (scp != NULL)) ? ", " : "", 1030 scp ? scp : ""); 1031 } 1032 printf(" at device %d.%d (no driver attached)\n", 1033 pci_get_slot(child), pci_get_function(child)); 1034 return; 1035} 1036 1037/* 1038 * Parse the PCI device database, if loaded, and return a pointer to a 1039 * description of the device. 1040 * 1041 * The database is flat text formatted as follows: 1042 * 1043 * Any line not in a valid format is ignored. 1044 * Lines are terminated with newline '\n' characters. 1045 * 1046 * A VENDOR line consists of the 4 digit (hex) vendor code, a TAB, then 1047 * the vendor name. 1048 * 1049 * A DEVICE line is entered immediately below the corresponding VENDOR ID. 1050 * - devices cannot be listed without a corresponding VENDOR line. 1051 * A DEVICE line consists of a TAB, the 4 digit (hex) device code, 1052 * another TAB, then the device name. 1053 */ 1054 1055/* 1056 * Assuming (ptr) points to the beginning of a line in the database, 1057 * return the vendor or device and description of the next entry. 1058 * The value of (vendor) or (device) inappropriate for the entry type 1059 * is set to -1. Returns nonzero at the end of the database. 1060 * 1061 * Note that this is slightly unrobust in the face of corrupt data; 1062 * we attempt to safeguard against this by spamming the end of the 1063 * database with a newline when we initialise. 1064 */ 1065static int 1066pci_describe_parse_line(char **ptr, int *vendor, int *device, char **desc) 1067{ 1068 char *cp = *ptr; 1069 int left; 1070 1071 *device = -1; 1072 *vendor = -1; 1073 **desc = '\0'; 1074 for (;;) { 1075 left = pci_vendordata_size - (cp - pci_vendordata); 1076 if (left <= 0) { 1077 *ptr = cp; 1078 return(1); 1079 } 1080 1081 /* vendor entry? */ 1082 if (*cp != '\t' && 1083 sscanf(cp, "%x\t%80[^\n]", vendor, *desc) == 2) 1084 break; 1085 /* device entry? */ 1086 if (*cp == '\t' && 1087 sscanf(cp, "%x\t%80[^\n]", device, *desc) == 2) 1088 break; 1089 1090 /* skip to next line */ 1091 while (*cp != '\n' && left > 0) { 1092 cp++; 1093 left--; 1094 } 1095 if (*cp == '\n') { 1096 cp++; 1097 left--; 1098 } 1099 } 1100 /* skip to next line */ 1101 while (*cp != '\n' && left > 0) { 1102 cp++; 1103 left--; 1104 } 1105 if (*cp == '\n' && left > 0) 1106 cp++; 1107 *ptr = cp; 1108 return(0); 1109} 1110 1111static char * 1112pci_describe_device(device_t dev) 1113{ 1114 int vendor, device; 1115 char *desc, *vp, *dp, *line; 1116 1117 desc = vp = dp = NULL; 1118 1119 /* 1120 * If we have no vendor data, we can't do anything. 1121 */ 1122 if (pci_vendordata == NULL) 1123 goto out; 1124 1125 /* 1126 * Scan the vendor data looking for this device 1127 */ 1128 line = pci_vendordata; 1129 if ((vp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL) 1130 goto out; 1131 for (;;) { 1132 if (pci_describe_parse_line(&line, &vendor, &device, &vp)) 1133 goto out; 1134 if (vendor == pci_get_vendor(dev)) 1135 break; 1136 } 1137 if ((dp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL) 1138 goto out; 1139 for (;;) { 1140 if (pci_describe_parse_line(&line, &vendor, &device, &dp)) { 1141 *dp = 0; 1142 break; 1143 } 1144 if (vendor != -1) { 1145 *dp = 0; 1146 break; 1147 } 1148 if (device == pci_get_device(dev)) 1149 break; 1150 } 1151 if (dp[0] == '\0') 1152 snprintf(dp, 80, "0x%x", pci_get_device(dev)); 1153 if ((desc = malloc(strlen(vp) + strlen(dp) + 3, M_DEVBUF, M_NOWAIT)) != 1154 NULL) 1155 sprintf(desc, "%s, %s", vp, dp); 1156 out: 1157 if (vp != NULL) 1158 free(vp, M_DEVBUF); 1159 if (dp != NULL) 1160 free(dp, M_DEVBUF); 1161 return(desc); 1162} 1163 1164int 1165pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 1166{ 1167 struct pci_devinfo *dinfo; 1168 pcicfgregs *cfg; 1169 1170 dinfo = device_get_ivars(child); 1171 cfg = &dinfo->cfg; 1172 1173 switch (which) { 1174 case PCI_IVAR_ETHADDR: 1175 /* 1176 * The generic accessor doesn't deal with failure, so 1177 * we set the return value, then return an error. 1178 */ 1179 *((uint8_t **) result) = NULL; 1180 return (EINVAL); 1181 case PCI_IVAR_SUBVENDOR: 1182 *result = cfg->subvendor; 1183 break; 1184 case PCI_IVAR_SUBDEVICE: 1185 *result = cfg->subdevice; 1186 break; 1187 case PCI_IVAR_VENDOR: 1188 *result = cfg->vendor; 1189 break; 1190 case PCI_IVAR_DEVICE: 1191 *result = cfg->device; 1192 break; 1193 case PCI_IVAR_DEVID: 1194 *result = (cfg->device << 16) | cfg->vendor; 1195 break; 1196 case PCI_IVAR_CLASS: 1197 *result = cfg->baseclass; 1198 break; 1199 case PCI_IVAR_SUBCLASS: 1200 *result = cfg->subclass; 1201 break; 1202 case PCI_IVAR_PROGIF: 1203 *result = cfg->progif; 1204 break; 1205 case PCI_IVAR_REVID: 1206 *result = cfg->revid; 1207 break; 1208 case PCI_IVAR_INTPIN: 1209 *result = cfg->intpin; 1210 break; 1211 case PCI_IVAR_IRQ: 1212 *result = cfg->intline; 1213 break; 1214 case PCI_IVAR_BUS: 1215 *result = cfg->bus; 1216 break; 1217 case PCI_IVAR_SLOT: 1218 *result = cfg->slot; 1219 break; 1220 case PCI_IVAR_FUNCTION: 1221 *result = cfg->func; 1222 break; 1223 default: 1224 return (ENOENT); 1225 } 1226 return (0); 1227} 1228 1229int 1230pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value) 1231{ 1232 struct pci_devinfo *dinfo; 1233 1234 dinfo = device_get_ivars(child); 1235 1236 switch (which) { 1237 case PCI_IVAR_INTPIN: 1238 dinfo->cfg.intpin = value; 1239 return (0); 1240 case PCI_IVAR_ETHADDR: 1241 case PCI_IVAR_SUBVENDOR: 1242 case PCI_IVAR_SUBDEVICE: 1243 case PCI_IVAR_VENDOR: 1244 case PCI_IVAR_DEVICE: 1245 case PCI_IVAR_DEVID: 1246 case PCI_IVAR_CLASS: 1247 case PCI_IVAR_SUBCLASS: 1248 case PCI_IVAR_PROGIF: 1249 case PCI_IVAR_REVID: 1250 case PCI_IVAR_IRQ: 1251 case PCI_IVAR_BUS: 1252 case PCI_IVAR_SLOT: 1253 case PCI_IVAR_FUNCTION: 1254 return (EINVAL); /* disallow for now */ 1255 1256 default: 1257 return (ENOENT); 1258 } 1259} 1260 1261 1262#include "opt_ddb.h" 1263#ifdef DDB 1264#include <ddb/ddb.h> 1265#include <sys/cons.h> 1266 1267/* 1268 * List resources based on pci map registers, used for within ddb 1269 */ 1270 1271DB_SHOW_COMMAND(pciregs, db_pci_dump) 1272{ 1273 struct pci_devinfo *dinfo; 1274 struct devlist *devlist_head; 1275 struct pci_conf *p; 1276 const char *name; 1277 int i, error, none_count, quit; 1278 1279 none_count = 0; 1280 /* get the head of the device queue */ 1281 devlist_head = &pci_devq; 1282 1283 /* 1284 * Go through the list of devices and print out devices 1285 */ 1286 db_setup_paging(db_simple_pager, &quit, DB_LINES_PER_PAGE); 1287 for (error = 0, i = 0, quit = 0, 1288 dinfo = STAILQ_FIRST(devlist_head); 1289 (dinfo != NULL) && (error == 0) && (i < pci_numdevs) && !quit; 1290 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) { 1291 1292 /* Populate pd_name and pd_unit */ 1293 name = NULL; 1294 if (dinfo->cfg.dev) 1295 name = device_get_name(dinfo->cfg.dev); 1296 1297 p = &dinfo->conf; 1298 db_printf("%s%d@pci%d:%d:%d:\tclass=0x%06x card=0x%08x " 1299 "chip=0x%08x rev=0x%02x hdr=0x%02x\n", 1300 (name && *name) ? name : "none", 1301 (name && *name) ? (int)device_get_unit(dinfo->cfg.dev) : 1302 none_count++, 1303 p->pc_sel.pc_bus, p->pc_sel.pc_dev, 1304 p->pc_sel.pc_func, (p->pc_class << 16) | 1305 (p->pc_subclass << 8) | p->pc_progif, 1306 (p->pc_subdevice << 16) | p->pc_subvendor, 1307 (p->pc_device << 16) | p->pc_vendor, 1308 p->pc_revid, p->pc_hdr); 1309 } 1310} 1311#endif /* DDB */ 1312 1313struct resource * 1314pci_alloc_resource(device_t dev, device_t child, int type, int *rid, 1315 u_long start, u_long end, u_long count, u_int flags) 1316{ 1317 struct pci_devinfo *dinfo = device_get_ivars(child); 1318 struct resource_list *rl = &dinfo->resources; 1319 pcicfgregs *cfg = &dinfo->cfg; 1320 1321 /* 1322 * Perform lazy resource allocation 1323 * 1324 * XXX add support here for SYS_RES_IOPORT and SYS_RES_MEMORY 1325 */ 1326 if (device_get_parent(child) == dev) { 1327 switch (type) { 1328 case SYS_RES_IRQ: 1329 /* 1330 * If the child device doesn't have an 1331 * interrupt routed and is deserving of an 1332 * interrupt, try to assign it one. 1333 */ 1334 if (!PCI_INTERRUPT_VALID(cfg->intline) && 1335 (cfg->intpin != 0)) { 1336 cfg->intline = PCI_ASSIGN_INTERRUPT(dev, child); 1337 if (PCI_INTERRUPT_VALID(cfg->intline)) { 1338 pci_write_config(child, PCIR_INTLINE, 1339 cfg->intline, 1); 1340 resource_list_add(rl, SYS_RES_IRQ, 0, 1341 cfg->intline, cfg->intline, 1); 1342 } 1343 } 1344 break; 1345 case SYS_RES_IOPORT: 1346 case SYS_RES_MEMORY: 1347 if (*rid < PCIR_MAPS + 4*cfg->nummaps) { 1348 /* 1349 * Enable the I/O mode. We should 1350 * also be allocating resources 1351 * too. XXX 1352 */ 1353 if (PCI_ENABLE_IO(dev, child, type)) 1354 return (NULL); 1355 } 1356 break; 1357 } 1358 } 1359 1360 return (resource_list_alloc(rl, dev, child, type, rid, 1361 start, end, count, flags)); 1362} 1363 1364void 1365pci_delete_resource(device_t dev, device_t child, int type, int rid) 1366{ 1367 struct pci_devinfo *dinfo; 1368 struct resource_list *rl; 1369 struct resource_list_entry *rle; 1370 1371 if (device_get_parent(child) != dev) 1372 return; 1373 1374 dinfo = device_get_ivars(child); 1375 rl = &dinfo->resources; 1376 rle = resource_list_find(rl, type, rid); 1377 if (rle) { 1378 if (rle->res) { 1379 if (rman_get_device(rle->res) != dev || 1380 rman_get_flags(rle->res) & RF_ACTIVE) { 1381 device_printf(dev, "delete_resource: " 1382 "Resource still owned by child, oops. " 1383 "(type=%d, rid=%d, addr=%lx)\n", 1384 rle->type, rle->rid, 1385 rman_get_start(rle->res)); 1386 return; 1387 } 1388 bus_release_resource(dev, type, rid, rle->res); 1389 } 1390 resource_list_delete(rl, type, rid); 1391 } 1392 /* 1393 * Why do we turn off the PCI configuration BAR when we delete a 1394 * resource? -- imp 1395 */ 1396 pci_write_config(child, rid, 0, 4); 1397 BUS_DELETE_RESOURCE(device_get_parent(dev), child, type, rid); 1398} 1399 1400struct resource_list * 1401pci_get_resource_list (device_t dev, device_t child) 1402{ 1403 struct pci_devinfo * dinfo = device_get_ivars(child); 1404 struct resource_list * rl = &dinfo->resources; 1405 1406 if (!rl) 1407 return (NULL); 1408 1409 return (rl); 1410} 1411 1412uint32_t 1413pci_read_config_method(device_t dev, device_t child, int reg, int width) 1414{ 1415 struct pci_devinfo *dinfo = device_get_ivars(child); 1416 pcicfgregs *cfg = &dinfo->cfg; 1417 1418 return (PCIB_READ_CONFIG(device_get_parent(dev), 1419 cfg->bus, cfg->slot, cfg->func, reg, width)); 1420} 1421 1422void 1423pci_write_config_method(device_t dev, device_t child, int reg, 1424 uint32_t val, int width) 1425{ 1426 struct pci_devinfo *dinfo = device_get_ivars(child); 1427 pcicfgregs *cfg = &dinfo->cfg; 1428 1429 PCIB_WRITE_CONFIG(device_get_parent(dev), 1430 cfg->bus, cfg->slot, cfg->func, reg, val, width); 1431} 1432 1433int 1434pci_child_location_str_method(device_t cbdev, device_t child, char *buf, 1435 size_t buflen) 1436{ 1437 struct pci_devinfo *dinfo; 1438 1439 dinfo = device_get_ivars(child); 1440 snprintf(buf, buflen, "slot=%d function=%d", pci_get_slot(child), 1441 pci_get_function(child)); 1442 return (0); 1443} 1444 1445int 1446pci_child_pnpinfo_str_method(device_t cbdev, device_t child, char *buf, 1447 size_t buflen) 1448{ 1449 struct pci_devinfo *dinfo; 1450 pcicfgregs *cfg; 1451 1452 dinfo = device_get_ivars(child); 1453 cfg = &dinfo->cfg; 1454 snprintf(buf, buflen, "vendor=0x%04x device=0x%04x subvendor=0x%04x " 1455 "subdevice=0x%04x class=0x%02x%02x%02x", cfg->vendor, cfg->device, 1456 cfg->subvendor, cfg->subdevice, cfg->baseclass, cfg->subclass, 1457 cfg->progif); 1458 return (0); 1459} 1460 1461int 1462pci_assign_interrupt_method(device_t dev, device_t child) 1463{ 1464 struct pci_devinfo *dinfo = device_get_ivars(child); 1465 pcicfgregs *cfg = &dinfo->cfg; 1466 1467 return (PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child, 1468 cfg->intpin)); 1469} 1470 1471static int 1472pci_modevent(module_t mod, int what, void *arg) 1473{ 1474 static dev_t pci_cdev; 1475 1476 switch (what) { 1477 case MOD_LOAD: 1478 STAILQ_INIT(&pci_devq); 1479 pci_generation = 0; 1480 pci_cdev = make_dev(&pcicdev, 0, UID_ROOT, GID_WHEEL, 0644, 1481 "pci"); 1482 pci_load_vendor_data(); 1483 break; 1484 1485 case MOD_UNLOAD: 1486 destroy_dev(pci_cdev); 1487 break; 1488 } 1489 1490 return (0); 1491} 1492