pci.c revision 111119
1/* 2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 3 * Copyright (c) 2000, Michael Smith <msmith@freebsd.org> 4 * Copyright (c) 2000, BSDi 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * $FreeBSD: head/sys/dev/pci/pci.c 111119 2003-02-19 05:47:46Z imp $ 29 * 30 */ 31 32#include "opt_bus.h" 33 34#include <sys/param.h> 35#include <sys/systm.h> 36#include <sys/malloc.h> 37#include <sys/module.h> 38#include <sys/linker.h> 39#include <sys/fcntl.h> 40#include <sys/conf.h> 41#include <sys/kernel.h> 42#include <sys/queue.h> 43#include <sys/sysctl.h> 44#include <sys/types.h> 45 46#include <vm/vm.h> 47#include <vm/pmap.h> 48#include <vm/vm_extern.h> 49 50#include <sys/bus.h> 51#include <machine/bus.h> 52#include <sys/rman.h> 53#include <machine/resource.h> 54 55#include <sys/pciio.h> 56#include <dev/pci/pcireg.h> 57#include <dev/pci/pcivar.h> 58#include <dev/pci/pci_private.h> 59 60#include "pcib_if.h" 61#include "pci_if.h" 62 63static u_int32_t pci_mapbase(unsigned mapreg); 64static int pci_maptype(unsigned mapreg); 65static int pci_mapsize(unsigned testval); 66static int pci_maprange(unsigned mapreg); 67static void pci_fixancient(pcicfgregs *cfg); 68 69static int pci_porten(device_t pcib, int b, int s, int f); 70static int pci_memen(device_t pcib, int b, int s, int f); 71static int pci_add_map(device_t pcib, int b, int s, int f, int reg, 72 struct resource_list *rl); 73static void pci_add_resources(device_t pcib, device_t dev); 74static int pci_probe(device_t dev); 75static int pci_attach(device_t dev); 76static void pci_load_vendor_data(void); 77static int pci_describe_parse_line(char **ptr, int *vendor, 78 int *device, char **desc); 79static char *pci_describe_device(device_t dev); 80static int pci_modevent(module_t mod, int what, void *arg); 81static void pci_hdrtypedata(device_t pcib, int b, int s, int f, 82 pcicfgregs *cfg); 83static void pci_read_extcap(device_t pcib, pcicfgregs *cfg); 84 85static device_method_t pci_methods[] = { 86 /* Device interface */ 87 DEVMETHOD(device_probe, pci_probe), 88 DEVMETHOD(device_attach, pci_attach), 89 DEVMETHOD(device_shutdown, bus_generic_shutdown), 90 DEVMETHOD(device_suspend, bus_generic_suspend), 91 DEVMETHOD(device_resume, bus_generic_resume), 92 93 /* Bus interface */ 94 DEVMETHOD(bus_print_child, pci_print_child), 95 DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch), 96 DEVMETHOD(bus_read_ivar, pci_read_ivar), 97 DEVMETHOD(bus_write_ivar, pci_write_ivar), 98 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 99 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 100 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 101 102 DEVMETHOD(bus_get_resource_list,pci_get_resource_list), 103 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource), 104 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource), 105 DEVMETHOD(bus_delete_resource, pci_delete_resource), 106 DEVMETHOD(bus_alloc_resource, pci_alloc_resource), 107 DEVMETHOD(bus_release_resource, bus_generic_rl_release_resource), 108 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 109 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 110 DEVMETHOD(bus_child_pnpinfo_str, pci_child_pnpinfo_str_method), 111 DEVMETHOD(bus_child_location_str, pci_child_location_str_method), 112 113 /* PCI interface */ 114 DEVMETHOD(pci_read_config, pci_read_config_method), 115 DEVMETHOD(pci_write_config, pci_write_config_method), 116 DEVMETHOD(pci_enable_busmaster, pci_enable_busmaster_method), 117 DEVMETHOD(pci_disable_busmaster, pci_disable_busmaster_method), 118 DEVMETHOD(pci_enable_io, pci_enable_io_method), 119 DEVMETHOD(pci_disable_io, pci_disable_io_method), 120 DEVMETHOD(pci_get_powerstate, pci_get_powerstate_method), 121 DEVMETHOD(pci_set_powerstate, pci_set_powerstate_method), 122 123 { 0, 0 } 124}; 125 126static driver_t pci_driver = { 127 "pci", 128 pci_methods, 129 0, /* no softc */ 130}; 131 132devclass_t pci_devclass; 133DRIVER_MODULE(pci, pcib, pci_driver, pci_devclass, pci_modevent, 0); 134MODULE_VERSION(pci, 1); 135 136static char *pci_vendordata; 137static size_t pci_vendordata_size; 138 139 140struct pci_quirk { 141 u_int32_t devid; /* Vendor/device of the card */ 142 int type; 143#define PCI_QUIRK_MAP_REG 1 /* PCI map register in weird place */ 144 int arg1; 145 int arg2; 146}; 147 148struct pci_quirk pci_quirks[] = { 149 /* The Intel 82371AB and 82443MX has a map register at offset 0x90. */ 150 { 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 151 { 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 152 /* As does the Serverworks OSB4 (the SMBus mapping register) */ 153 { 0x02001166, PCI_QUIRK_MAP_REG, 0x90, 0 }, 154 155 { 0 } 156}; 157 158/* map register information */ 159#define PCI_MAPMEM 0x01 /* memory map */ 160#define PCI_MAPMEMP 0x02 /* prefetchable memory map */ 161#define PCI_MAPPORT 0x04 /* port map */ 162 163struct devlist pci_devq; 164u_int32_t pci_generation; 165u_int32_t pci_numdevs = 0; 166 167/* sysctl vars */ 168SYSCTL_NODE(_hw, OID_AUTO, pci, CTLFLAG_RD, 0, "PCI bus tuning parameters"); 169 170static int pci_enable_io_modes = 1; 171TUNABLE_INT("hw.pci.enable_io_modes", (int *)&pci_enable_io_modes); 172SYSCTL_INT(_hw_pci, OID_AUTO, enable_io_modes, CTLFLAG_RW, 173 &pci_enable_io_modes, 1, 174 "Enable I/O and memory bits in the config register. Some BIOSes do not\n\ 175enable these bits correctly. We'd like to do this all the time, but there\n\ 176are some peripherals that this causes problems with."); 177 178/* Find a device_t by bus/slot/function */ 179 180device_t 181pci_find_bsf(u_int8_t bus, u_int8_t slot, u_int8_t func) 182{ 183 struct pci_devinfo *dinfo; 184 185 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 186 if ((dinfo->cfg.bus == bus) && 187 (dinfo->cfg.slot == slot) && 188 (dinfo->cfg.func == func)) { 189 return (dinfo->cfg.dev); 190 } 191 } 192 193 return (NULL); 194} 195 196/* Find a device_t by vendor/device ID */ 197 198device_t 199pci_find_device(u_int16_t vendor, u_int16_t device) 200{ 201 struct pci_devinfo *dinfo; 202 203 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 204 if ((dinfo->cfg.vendor == vendor) && 205 (dinfo->cfg.device == device)) { 206 return (dinfo->cfg.dev); 207 } 208 } 209 210 return (NULL); 211} 212 213/* return base address of memory or port map */ 214 215static u_int32_t 216pci_mapbase(unsigned mapreg) 217{ 218 int mask = 0x03; 219 if ((mapreg & 0x01) == 0) 220 mask = 0x0f; 221 return (mapreg & ~mask); 222} 223 224/* return map type of memory or port map */ 225 226static int 227pci_maptype(unsigned mapreg) 228{ 229 static u_int8_t maptype[0x10] = { 230 PCI_MAPMEM, PCI_MAPPORT, 231 PCI_MAPMEM, 0, 232 PCI_MAPMEM, PCI_MAPPORT, 233 0, 0, 234 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT, 235 PCI_MAPMEM|PCI_MAPMEMP, 0, 236 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT, 237 0, 0, 238 }; 239 240 return maptype[mapreg & 0x0f]; 241} 242 243/* return log2 of map size decoded for memory or port map */ 244 245static int 246pci_mapsize(unsigned testval) 247{ 248 int ln2size; 249 250 testval = pci_mapbase(testval); 251 ln2size = 0; 252 if (testval != 0) { 253 while ((testval & 1) == 0) 254 { 255 ln2size++; 256 testval >>= 1; 257 } 258 } 259 return (ln2size); 260} 261 262/* return log2 of address range supported by map register */ 263 264static int 265pci_maprange(unsigned mapreg) 266{ 267 int ln2range = 0; 268 switch (mapreg & 0x07) { 269 case 0x00: 270 case 0x01: 271 case 0x05: 272 ln2range = 32; 273 break; 274 case 0x02: 275 ln2range = 20; 276 break; 277 case 0x04: 278 ln2range = 64; 279 break; 280 } 281 return (ln2range); 282} 283 284/* adjust some values from PCI 1.0 devices to match 2.0 standards ... */ 285 286static void 287pci_fixancient(pcicfgregs *cfg) 288{ 289 if (cfg->hdrtype != 0) 290 return; 291 292 /* PCI to PCI bridges use header type 1 */ 293 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI) 294 cfg->hdrtype = 1; 295} 296 297/* extract header type specific config data */ 298 299static void 300pci_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg) 301{ 302#define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 303 switch (cfg->hdrtype) { 304 case 0: 305 cfg->subvendor = REG(PCIR_SUBVEND_0, 2); 306 cfg->subdevice = REG(PCIR_SUBDEV_0, 2); 307 cfg->nummaps = PCI_MAXMAPS_0; 308 break; 309 case 1: 310 cfg->subvendor = REG(PCIR_SUBVEND_1, 2); 311 cfg->subdevice = REG(PCIR_SUBDEV_1, 2); 312 cfg->nummaps = PCI_MAXMAPS_1; 313 break; 314 case 2: 315 cfg->subvendor = REG(PCIR_SUBVEND_2, 2); 316 cfg->subdevice = REG(PCIR_SUBDEV_2, 2); 317 cfg->nummaps = PCI_MAXMAPS_2; 318 break; 319 } 320#undef REG 321} 322 323/* read configuration header into pcicfgregs structure */ 324 325struct pci_devinfo * 326pci_read_device(device_t pcib, int b, int s, int f, size_t size) 327{ 328#define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 329 pcicfgregs *cfg = NULL; 330 struct pci_devinfo *devlist_entry; 331 struct devlist *devlist_head; 332 333 devlist_head = &pci_devq; 334 335 devlist_entry = NULL; 336 337 if (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_DEVVENDOR, 4) != -1) { 338 devlist_entry = malloc(size, M_DEVBUF, M_WAITOK | M_ZERO); 339 if (devlist_entry == NULL) 340 return (NULL); 341 342 cfg = &devlist_entry->cfg; 343 344 cfg->bus = b; 345 cfg->slot = s; 346 cfg->func = f; 347 cfg->vendor = REG(PCIR_VENDOR, 2); 348 cfg->device = REG(PCIR_DEVICE, 2); 349 cfg->cmdreg = REG(PCIR_COMMAND, 2); 350 cfg->statreg = REG(PCIR_STATUS, 2); 351 cfg->baseclass = REG(PCIR_CLASS, 1); 352 cfg->subclass = REG(PCIR_SUBCLASS, 1); 353 cfg->progif = REG(PCIR_PROGIF, 1); 354 cfg->revid = REG(PCIR_REVID, 1); 355 cfg->hdrtype = REG(PCIR_HEADERTYPE, 1); 356 cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1); 357 cfg->lattimer = REG(PCIR_LATTIMER, 1); 358 cfg->intpin = REG(PCIR_INTPIN, 1); 359 cfg->intline = REG(PCIR_INTLINE, 1); 360 361 cfg->mingnt = REG(PCIR_MINGNT, 1); 362 cfg->maxlat = REG(PCIR_MAXLAT, 1); 363 364 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0; 365 cfg->hdrtype &= ~PCIM_MFDEV; 366 367 pci_fixancient(cfg); 368 pci_hdrtypedata(pcib, b, s, f, cfg); 369 370 if (REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT) 371 pci_read_extcap(pcib, cfg); 372 373 STAILQ_INSERT_TAIL(devlist_head, devlist_entry, pci_links); 374 375 devlist_entry->conf.pc_sel.pc_bus = cfg->bus; 376 devlist_entry->conf.pc_sel.pc_dev = cfg->slot; 377 devlist_entry->conf.pc_sel.pc_func = cfg->func; 378 devlist_entry->conf.pc_hdr = cfg->hdrtype; 379 380 devlist_entry->conf.pc_subvendor = cfg->subvendor; 381 devlist_entry->conf.pc_subdevice = cfg->subdevice; 382 devlist_entry->conf.pc_vendor = cfg->vendor; 383 devlist_entry->conf.pc_device = cfg->device; 384 385 devlist_entry->conf.pc_class = cfg->baseclass; 386 devlist_entry->conf.pc_subclass = cfg->subclass; 387 devlist_entry->conf.pc_progif = cfg->progif; 388 devlist_entry->conf.pc_revid = cfg->revid; 389 390 pci_numdevs++; 391 pci_generation++; 392 } 393 return (devlist_entry); 394#undef REG 395} 396 397static void 398pci_read_extcap(device_t pcib, pcicfgregs *cfg) 399{ 400#define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w) 401 int ptr, nextptr, ptrptr; 402 403 switch (cfg->hdrtype) { 404 case 0: 405 ptrptr = 0x34; 406 break; 407 case 2: 408 ptrptr = 0x14; 409 break; 410 default: 411 return; /* no extended capabilities support */ 412 } 413 nextptr = REG(ptrptr, 1); /* sanity check? */ 414 415 /* 416 * Read capability entries. 417 */ 418 while (nextptr != 0) { 419 /* Sanity check */ 420 if (nextptr > 255) { 421 printf("illegal PCI extended capability offset %d\n", 422 nextptr); 423 return; 424 } 425 /* Find the next entry */ 426 ptr = nextptr; 427 nextptr = REG(ptr + 1, 1); 428 429 /* Process this entry */ 430 switch (REG(ptr, 1)) { 431 case 0x01: /* PCI power management */ 432 if (cfg->pp_cap == 0) { 433 cfg->pp_cap = REG(ptr + PCIR_POWER_CAP, 2); 434 cfg->pp_status = ptr + PCIR_POWER_STATUS; 435 cfg->pp_pmcsr = ptr + PCIR_POWER_PMCSR; 436 if ((nextptr - ptr) > PCIR_POWER_DATA) 437 cfg->pp_data = ptr + PCIR_POWER_DATA; 438 } 439 break; 440 default: 441 break; 442 } 443 } 444#undef REG 445} 446 447/* free pcicfgregs structure and all depending data structures */ 448 449int 450pci_freecfg(struct pci_devinfo *dinfo) 451{ 452 struct devlist *devlist_head; 453 454 devlist_head = &pci_devq; 455 456 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links); 457 free(dinfo, M_DEVBUF); 458 459 /* increment the generation count */ 460 pci_generation++; 461 462 /* we're losing one device */ 463 pci_numdevs--; 464 return (0); 465} 466 467/* 468 * PCI power manangement 469 */ 470int 471pci_set_powerstate_method(device_t dev, device_t child, int state) 472{ 473 struct pci_devinfo *dinfo = device_get_ivars(child); 474 pcicfgregs *cfg = &dinfo->cfg; 475 u_int16_t status; 476 int result; 477 478 if (cfg->pp_cap != 0) { 479 status = PCI_READ_CONFIG(dev, child, cfg->pp_status, 2) & ~PCIM_PSTAT_DMASK; 480 result = 0; 481 switch (state) { 482 case PCI_POWERSTATE_D0: 483 status |= PCIM_PSTAT_D0; 484 break; 485 case PCI_POWERSTATE_D1: 486 if (cfg->pp_cap & PCIM_PCAP_D1SUPP) { 487 status |= PCIM_PSTAT_D1; 488 } else { 489 result = EOPNOTSUPP; 490 } 491 break; 492 case PCI_POWERSTATE_D2: 493 if (cfg->pp_cap & PCIM_PCAP_D2SUPP) { 494 status |= PCIM_PSTAT_D2; 495 } else { 496 result = EOPNOTSUPP; 497 } 498 break; 499 case PCI_POWERSTATE_D3: 500 status |= PCIM_PSTAT_D3; 501 break; 502 default: 503 result = EINVAL; 504 } 505 if (result == 0) 506 PCI_WRITE_CONFIG(dev, child, cfg->pp_status, status, 2); 507 } else { 508 result = ENXIO; 509 } 510 return(result); 511} 512 513int 514pci_get_powerstate_method(device_t dev, device_t child) 515{ 516 struct pci_devinfo *dinfo = device_get_ivars(child); 517 pcicfgregs *cfg = &dinfo->cfg; 518 u_int16_t status; 519 int result; 520 521 if (cfg->pp_cap != 0) { 522 status = PCI_READ_CONFIG(dev, child, cfg->pp_status, 2); 523 switch (status & PCIM_PSTAT_DMASK) { 524 case PCIM_PSTAT_D0: 525 result = PCI_POWERSTATE_D0; 526 break; 527 case PCIM_PSTAT_D1: 528 result = PCI_POWERSTATE_D1; 529 break; 530 case PCIM_PSTAT_D2: 531 result = PCI_POWERSTATE_D2; 532 break; 533 case PCIM_PSTAT_D3: 534 result = PCI_POWERSTATE_D3; 535 break; 536 default: 537 result = PCI_POWERSTATE_UNKNOWN; 538 break; 539 } 540 } else { 541 /* No support, device is always at D0 */ 542 result = PCI_POWERSTATE_D0; 543 } 544 return(result); 545} 546 547/* 548 * Some convenience functions for PCI device drivers. 549 */ 550 551static __inline void 552pci_set_command_bit(device_t dev, device_t child, u_int16_t bit) 553{ 554 u_int16_t command; 555 556 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 557 command |= bit; 558 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 559} 560 561static __inline void 562pci_clear_command_bit(device_t dev, device_t child, u_int16_t bit) 563{ 564 u_int16_t command; 565 566 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 567 command &= ~bit; 568 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 569} 570 571void 572pci_enable_busmaster_method(device_t dev, device_t child) 573{ 574 pci_set_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 575} 576 577void 578pci_disable_busmaster_method(device_t dev, device_t child) 579{ 580 pci_clear_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 581} 582 583void 584pci_enable_io_method(device_t dev, device_t child, int space) 585{ 586 switch(space) { 587 case SYS_RES_IOPORT: 588 pci_set_command_bit(dev, child, PCIM_CMD_PORTEN); 589 break; 590 case SYS_RES_MEMORY: 591 pci_set_command_bit(dev, child, PCIM_CMD_MEMEN); 592 break; 593 } 594} 595 596void 597pci_disable_io_method(device_t dev, device_t child, int space) 598{ 599 switch(space) { 600 case SYS_RES_IOPORT: 601 pci_clear_command_bit(dev, child, PCIM_CMD_PORTEN); 602 break; 603 case SYS_RES_MEMORY: 604 pci_clear_command_bit(dev, child, PCIM_CMD_MEMEN); 605 break; 606 } 607} 608 609/* 610 * New style pci driver. Parent device is either a pci-host-bridge or a 611 * pci-pci-bridge. Both kinds are represented by instances of pcib. 612 */ 613 614void 615pci_print_verbose(struct pci_devinfo *dinfo) 616{ 617 if (bootverbose) { 618 pcicfgregs *cfg = &dinfo->cfg; 619 620 printf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n", 621 cfg->vendor, cfg->device, cfg->revid); 622 printf("\tbus=%d, slot=%d, func=%d\n", 623 cfg->bus, cfg->slot, cfg->func); 624 printf("\tclass=%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n", 625 cfg->baseclass, cfg->subclass, cfg->progif, cfg->hdrtype, 626 cfg->mfdev); 627 printf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n", 628 cfg->cmdreg, cfg->statreg, cfg->cachelnsz); 629 printf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n", 630 cfg->lattimer, cfg->lattimer * 30, cfg->mingnt, 631 cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250); 632 if (cfg->intpin > 0) 633 printf("\tintpin=%c, irq=%d\n", 634 cfg->intpin +'a' -1, cfg->intline); 635 if (cfg->pp_cap) { 636 u_int16_t status; 637 638 status = pci_read_config(cfg->dev, cfg->pp_status, 2); 639 printf("\tpowerspec %d supports D0%s%s D3 current D%d\n", 640 cfg->pp_cap & PCIM_PCAP_SPEC, 641 cfg->pp_cap & PCIM_PCAP_D1SUPP ? " D1" : "", 642 cfg->pp_cap & PCIM_PCAP_D2SUPP ? " D2" : "", 643 status & PCIM_PSTAT_DMASK); 644 } 645 } 646} 647 648static int 649pci_porten(device_t pcib, int b, int s, int f) 650{ 651 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2) 652 & PCIM_CMD_PORTEN) != 0; 653} 654 655static int 656pci_memen(device_t pcib, int b, int s, int f) 657{ 658 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2) 659 & PCIM_CMD_MEMEN) != 0; 660} 661 662/* 663 * Add a resource based on a pci map register. Return 1 if the map 664 * register is a 32bit map register or 2 if it is a 64bit register. 665 */ 666static int 667pci_add_map(device_t pcib, int b, int s, int f, int reg, 668 struct resource_list *rl) 669{ 670 u_int32_t map; 671 u_int64_t base; 672 u_int8_t ln2size; 673 u_int8_t ln2range; 674 u_int32_t testval; 675 u_int16_t cmd; 676 int type; 677 678 map = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4); 679 680 if (map == 0 || map == 0xffffffff) 681 return (1); /* skip invalid entry */ 682 683 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, 0xffffffff, 4); 684 testval = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4); 685 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, map, 4); 686 687 base = pci_mapbase(map); 688 if (pci_maptype(map) & PCI_MAPMEM) 689 type = SYS_RES_MEMORY; 690 else 691 type = SYS_RES_IOPORT; 692 ln2size = pci_mapsize(testval); 693 ln2range = pci_maprange(testval); 694 if (ln2range == 64) { 695 /* Read the other half of a 64bit map register */ 696 base |= (u_int64_t) PCIB_READ_CONFIG(pcib, b, s, f, reg + 4, 4) << 32; 697 } 698 699 if (bootverbose) { 700 printf("\tmap[%02x]: type %x, range %2d, base %08x, size %2d", 701 reg, pci_maptype(map), ln2range, 702 (unsigned int) base, ln2size); 703 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) 704 printf(", port disabled\n"); 705 else if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) 706 printf(", memory disabled\n"); 707 else 708 printf(", enabled\n"); 709 } 710 711 /* 712 * This code theoretically does the right thing, but has 713 * undesirable side effects in some cases where 714 * peripherals respond oddly to having these bits 715 * enabled. Leave them alone by default. 716 */ 717 if (pci_enable_io_modes) { 718 /* Turn on resources that have been left off by a lazy BIOS */ 719 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) { 720 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2); 721 cmd |= PCIM_CMD_PORTEN; 722 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2); 723 } 724 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) { 725 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2); 726 cmd |= PCIM_CMD_MEMEN; 727 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2); 728 } 729 } else { 730 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) 731 return (1); 732 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) 733 return (1); 734 } 735 resource_list_add(rl, type, reg, base, base + (1 << ln2size) - 1, 736 (1 << ln2size)); 737 738 return ((ln2range == 64) ? 2 : 1); 739} 740 741static void 742pci_add_resources(device_t pcib, device_t dev) 743{ 744 struct pci_devinfo *dinfo = device_get_ivars(dev); 745 pcicfgregs *cfg = &dinfo->cfg; 746 struct resource_list *rl = &dinfo->resources; 747 struct pci_quirk *q; 748 int b, i, f, s; 749 750 b = cfg->bus; 751 s = cfg->slot; 752 f = cfg->func; 753 for (i = 0; i < cfg->nummaps;) { 754 i += pci_add_map(pcib, b, s, f, PCIR_MAPS + i*4, rl); 755 } 756 757 for (q = &pci_quirks[0]; q->devid; q++) { 758 if (q->devid == ((cfg->device << 16) | cfg->vendor) 759 && q->type == PCI_QUIRK_MAP_REG) 760 pci_add_map(pcib, b, s, f, q->arg1, rl); 761 } 762 763 if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline)) { 764#ifdef __ia64__ 765 /* 766 * Re-route interrupts on ia64 so that we can get the 767 * I/O SAPIC interrupt numbers (the BIOS leaves legacy 768 * PIC interrupt numbers in the intline registers). 769 */ 770 cfg->intline = PCIB_ROUTE_INTERRUPT(pcib, dev, cfg->intpin); 771#endif 772 resource_list_add(rl, SYS_RES_IRQ, 0, cfg->intline, 773 cfg->intline, 1); 774 } 775} 776 777void 778pci_add_children(device_t dev, int busno, size_t dinfo_size) 779{ 780 device_t pcib = device_get_parent(dev); 781 struct pci_devinfo *dinfo; 782 int maxslots; 783 int s, f, pcifunchigh; 784 785 KASSERT(dinfo_size >= sizeof(struct pci_devinfo), 786 ("dinfo_size too small")); 787 maxslots = PCIB_MAXSLOTS(pcib); 788 for (s = 0; s <= maxslots; s++) { 789 pcifunchigh = 0; 790 for (f = 0; f <= pcifunchigh; f++) { 791 dinfo = pci_read_device(pcib, busno, s, f, dinfo_size); 792 if (dinfo != NULL) { 793 if (dinfo->cfg.mfdev) 794 pcifunchigh = PCI_FUNCMAX; 795 pci_add_child(dev, dinfo); 796 } 797 } 798 } 799} 800 801void 802pci_add_child(device_t bus, struct pci_devinfo *dinfo) 803{ 804 device_t pcib; 805 806 pcib = device_get_parent(bus); 807 dinfo->cfg.dev = device_add_child(bus, NULL, -1); 808 device_set_ivars(dinfo->cfg.dev, dinfo); 809 pci_add_resources(pcib, dinfo->cfg.dev); 810 pci_print_verbose(dinfo); 811} 812 813static int 814pci_probe(device_t dev) 815{ 816 817 device_set_desc(dev, "PCI bus"); 818 819 /* Allow other subclasses to override this driver. */ 820 return (-1000); 821} 822 823static int 824pci_attach(device_t dev) 825{ 826 int busno; 827 828 /* 829 * Since there can be multiple independantly numbered PCI 830 * busses on some large alpha systems, we can't use the unit 831 * number to decide what bus we are probing. We ask the parent 832 * pcib what our bus number is. 833 */ 834 busno = pcib_get_bus(dev); 835 if (bootverbose) 836 device_printf(dev, "physical bus=%d\n", busno); 837 838 pci_add_children(dev, busno, sizeof(struct pci_devinfo)); 839 840 return (bus_generic_attach(dev)); 841} 842 843static void 844pci_load_vendor_data(void) 845{ 846 caddr_t vendordata, info; 847 848 if ((vendordata = preload_search_by_type("pci_vendor_data")) != NULL) { 849 info = preload_search_info(vendordata, MODINFO_ADDR); 850 pci_vendordata = *(char **)info; 851 info = preload_search_info(vendordata, MODINFO_SIZE); 852 pci_vendordata_size = *(size_t *)info; 853 /* terminate the database */ 854 pci_vendordata[pci_vendordata_size] = '\n'; 855 } 856} 857 858int 859pci_print_child(device_t dev, device_t child) 860{ 861 struct pci_devinfo *dinfo; 862 struct resource_list *rl; 863 pcicfgregs *cfg; 864 int retval = 0; 865 866 dinfo = device_get_ivars(child); 867 cfg = &dinfo->cfg; 868 rl = &dinfo->resources; 869 870 retval += bus_print_child_header(dev, child); 871 872 retval += resource_list_print_type(rl, "port", SYS_RES_IOPORT, "%#lx"); 873 retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#lx"); 874 retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%ld"); 875 if (device_get_flags(dev)) 876 retval += printf(" flags %#x", device_get_flags(dev)); 877 878 retval += printf(" at device %d.%d", pci_get_slot(child), 879 pci_get_function(child)); 880 881 retval += bus_print_child_footer(dev, child); 882 883 return (retval); 884} 885 886static struct 887{ 888 int class; 889 int subclass; 890 char *desc; 891} pci_nomatch_tab[] = { 892 {PCIC_OLD, -1, "old"}, 893 {PCIC_OLD, PCIS_OLD_NONVGA, "non-VGA display device"}, 894 {PCIC_OLD, PCIS_OLD_VGA, "VGA-compatible display device"}, 895 {PCIC_STORAGE, -1, "mass storage"}, 896 {PCIC_STORAGE, PCIS_STORAGE_SCSI, "SCSI"}, 897 {PCIC_STORAGE, PCIS_STORAGE_IDE, "ATA"}, 898 {PCIC_STORAGE, PCIS_STORAGE_FLOPPY, "floppy disk"}, 899 {PCIC_STORAGE, PCIS_STORAGE_IPI, "IPI"}, 900 {PCIC_STORAGE, PCIS_STORAGE_RAID, "RAID"}, 901 {PCIC_NETWORK, -1, "network"}, 902 {PCIC_NETWORK, PCIS_NETWORK_ETHERNET, "ethernet"}, 903 {PCIC_NETWORK, PCIS_NETWORK_TOKENRING, "token ring"}, 904 {PCIC_NETWORK, PCIS_NETWORK_FDDI, "fddi"}, 905 {PCIC_NETWORK, PCIS_NETWORK_ATM, "ATM"}, 906 {PCIC_DISPLAY, -1, "display"}, 907 {PCIC_DISPLAY, PCIS_DISPLAY_VGA, "VGA"}, 908 {PCIC_DISPLAY, PCIS_DISPLAY_XGA, "XGA"}, 909 {PCIC_MULTIMEDIA, -1, "multimedia"}, 910 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_VIDEO, "video"}, 911 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_AUDIO, "audio"}, 912 {PCIC_MEMORY, -1, "memory"}, 913 {PCIC_MEMORY, PCIS_MEMORY_RAM, "RAM"}, 914 {PCIC_MEMORY, PCIS_MEMORY_FLASH, "flash"}, 915 {PCIC_BRIDGE, -1, "bridge"}, 916 {PCIC_BRIDGE, PCIS_BRIDGE_HOST, "HOST-PCI"}, 917 {PCIC_BRIDGE, PCIS_BRIDGE_ISA, "PCI-ISA"}, 918 {PCIC_BRIDGE, PCIS_BRIDGE_EISA, "PCI-EISA"}, 919 {PCIC_BRIDGE, PCIS_BRIDGE_MCA, "PCI-MCA"}, 920 {PCIC_BRIDGE, PCIS_BRIDGE_PCI, "PCI-PCI"}, 921 {PCIC_BRIDGE, PCIS_BRIDGE_PCMCIA, "PCI-PCMCIA"}, 922 {PCIC_BRIDGE, PCIS_BRIDGE_NUBUS, "PCI-NuBus"}, 923 {PCIC_BRIDGE, PCIS_BRIDGE_CARDBUS, "PCI-CardBus"}, 924 {PCIC_BRIDGE, PCIS_BRIDGE_OTHER, "PCI-unknown"}, 925 {PCIC_SIMPLECOMM, -1, "simple comms"}, 926 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_UART, "UART"}, /* could detect 16550 */ 927 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_PAR, "parallel port"}, 928 {PCIC_BASEPERIPH, -1, "base peripheral"}, 929 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PIC, "interrupt controller"}, 930 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_DMA, "DMA controller"}, 931 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_TIMER, "timer"}, 932 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_RTC, "realtime clock"}, 933 {PCIC_INPUTDEV, -1, "input device"}, 934 {PCIC_INPUTDEV, PCIS_INPUTDEV_KEYBOARD, "keyboard"}, 935 {PCIC_INPUTDEV, PCIS_INPUTDEV_DIGITIZER,"digitizer"}, 936 {PCIC_INPUTDEV, PCIS_INPUTDEV_MOUSE, "mouse"}, 937 {PCIC_DOCKING, -1, "docking station"}, 938 {PCIC_PROCESSOR, -1, "processor"}, 939 {PCIC_SERIALBUS, -1, "serial bus"}, 940 {PCIC_SERIALBUS, PCIS_SERIALBUS_FW, "FireWire"}, 941 {PCIC_SERIALBUS, PCIS_SERIALBUS_ACCESS, "AccessBus"}, 942 {PCIC_SERIALBUS, PCIS_SERIALBUS_SSA, "SSA"}, 943 {PCIC_SERIALBUS, PCIS_SERIALBUS_USB, "USB"}, 944 {PCIC_SERIALBUS, PCIS_SERIALBUS_FC, "Fibre Channel"}, 945 {PCIC_SERIALBUS, PCIS_SERIALBUS_SMBUS, "SMBus"}, 946 {0, 0, NULL} 947}; 948 949void 950pci_probe_nomatch(device_t dev, device_t child) 951{ 952 int i; 953 char *cp, *scp, *device; 954 955 /* 956 * Look for a listing for this device in a loaded device database. 957 */ 958 if ((device = pci_describe_device(child)) != NULL) { 959 device_printf(dev, "<%s>", device); 960 free(device, M_DEVBUF); 961 } else { 962 /* 963 * Scan the class/subclass descriptions for a general 964 * description. 965 */ 966 cp = "unknown"; 967 scp = NULL; 968 for (i = 0; pci_nomatch_tab[i].desc != NULL; i++) { 969 if (pci_nomatch_tab[i].class == pci_get_class(child)) { 970 if (pci_nomatch_tab[i].subclass == -1) { 971 cp = pci_nomatch_tab[i].desc; 972 } else if (pci_nomatch_tab[i].subclass == 973 pci_get_subclass(child)) { 974 scp = pci_nomatch_tab[i].desc; 975 } 976 } 977 } 978 device_printf(dev, "<%s%s%s>", 979 cp ? cp : "", 980 ((cp != NULL) && (scp != NULL)) ? ", " : "", 981 scp ? scp : ""); 982 } 983 printf(" at device %d.%d (no driver attached)\n", 984 pci_get_slot(child), pci_get_function(child)); 985 return; 986} 987 988/* 989 * Parse the PCI device database, if loaded, and return a pointer to a 990 * description of the device. 991 * 992 * The database is flat text formatted as follows: 993 * 994 * Any line not in a valid format is ignored. 995 * Lines are terminated with newline '\n' characters. 996 * 997 * A VENDOR line consists of the 4 digit (hex) vendor code, a TAB, then 998 * the vendor name. 999 * 1000 * A DEVICE line is entered immediately below the corresponding VENDOR ID. 1001 * - devices cannot be listed without a corresponding VENDOR line. 1002 * A DEVICE line consists of a TAB, the 4 digit (hex) device code, 1003 * another TAB, then the device name. 1004 */ 1005 1006/* 1007 * Assuming (ptr) points to the beginning of a line in the database, 1008 * return the vendor or device and description of the next entry. 1009 * The value of (vendor) or (device) inappropriate for the entry type 1010 * is set to -1. Returns nonzero at the end of the database. 1011 * 1012 * Note that this is slightly unrobust in the face of corrupt data; 1013 * we attempt to safeguard against this by spamming the end of the 1014 * database with a newline when we initialise. 1015 */ 1016static int 1017pci_describe_parse_line(char **ptr, int *vendor, int *device, char **desc) 1018{ 1019 char *cp = *ptr; 1020 int left; 1021 1022 *device = -1; 1023 *vendor = -1; 1024 **desc = '\0'; 1025 for (;;) { 1026 left = pci_vendordata_size - (cp - pci_vendordata); 1027 if (left <= 0) { 1028 *ptr = cp; 1029 return(1); 1030 } 1031 1032 /* vendor entry? */ 1033 if (*cp != '\t' && 1034 sscanf(cp, "%x\t%80[^\n]", vendor, *desc) == 2) 1035 break; 1036 /* device entry? */ 1037 if (*cp == '\t' && 1038 sscanf(cp, "%x\t%80[^\n]", device, *desc) == 2) 1039 break; 1040 1041 /* skip to next line */ 1042 while (*cp != '\n' && left > 0) { 1043 cp++; 1044 left--; 1045 } 1046 if (*cp == '\n') { 1047 cp++; 1048 left--; 1049 } 1050 } 1051 /* skip to next line */ 1052 while (*cp != '\n' && left > 0) { 1053 cp++; 1054 left--; 1055 } 1056 if (*cp == '\n' && left > 0) 1057 cp++; 1058 *ptr = cp; 1059 return(0); 1060} 1061 1062static char * 1063pci_describe_device(device_t dev) 1064{ 1065 int vendor, device; 1066 char *desc, *vp, *dp, *line; 1067 1068 desc = vp = dp = NULL; 1069 1070 /* 1071 * If we have no vendor data, we can't do anything. 1072 */ 1073 if (pci_vendordata == NULL) 1074 goto out; 1075 1076 /* 1077 * Scan the vendor data looking for this device 1078 */ 1079 line = pci_vendordata; 1080 if ((vp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL) 1081 goto out; 1082 for (;;) { 1083 if (pci_describe_parse_line(&line, &vendor, &device, &vp)) 1084 goto out; 1085 if (vendor == pci_get_vendor(dev)) 1086 break; 1087 } 1088 if ((dp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL) 1089 goto out; 1090 for (;;) { 1091 if (pci_describe_parse_line(&line, &vendor, &device, &dp)) { 1092 *dp = 0; 1093 break; 1094 } 1095 if (vendor != -1) { 1096 *dp = 0; 1097 break; 1098 } 1099 if (device == pci_get_device(dev)) 1100 break; 1101 } 1102 if (dp[0] == '\0') 1103 snprintf(dp, 80, "0x%x", pci_get_device(dev)); 1104 if ((desc = malloc(strlen(vp) + strlen(dp) + 3, M_DEVBUF, M_NOWAIT)) != 1105 NULL) 1106 sprintf(desc, "%s, %s", vp, dp); 1107 out: 1108 if (vp != NULL) 1109 free(vp, M_DEVBUF); 1110 if (dp != NULL) 1111 free(dp, M_DEVBUF); 1112 return(desc); 1113} 1114 1115int 1116pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 1117{ 1118 struct pci_devinfo *dinfo; 1119 pcicfgregs *cfg; 1120 1121 dinfo = device_get_ivars(child); 1122 cfg = &dinfo->cfg; 1123 1124 switch (which) { 1125 case PCI_IVAR_ETHADDR: 1126 /* 1127 * The generic accessor doesn't deal with failure, so 1128 * we set the return value, then return an error. 1129 */ 1130 *((u_int8_t **) result) = NULL; 1131 return (EINVAL); 1132 case PCI_IVAR_SUBVENDOR: 1133 *result = cfg->subvendor; 1134 break; 1135 case PCI_IVAR_SUBDEVICE: 1136 *result = cfg->subdevice; 1137 break; 1138 case PCI_IVAR_VENDOR: 1139 *result = cfg->vendor; 1140 break; 1141 case PCI_IVAR_DEVICE: 1142 *result = cfg->device; 1143 break; 1144 case PCI_IVAR_DEVID: 1145 *result = (cfg->device << 16) | cfg->vendor; 1146 break; 1147 case PCI_IVAR_CLASS: 1148 *result = cfg->baseclass; 1149 break; 1150 case PCI_IVAR_SUBCLASS: 1151 *result = cfg->subclass; 1152 break; 1153 case PCI_IVAR_PROGIF: 1154 *result = cfg->progif; 1155 break; 1156 case PCI_IVAR_REVID: 1157 *result = cfg->revid; 1158 break; 1159 case PCI_IVAR_INTPIN: 1160 *result = cfg->intpin; 1161 break; 1162 case PCI_IVAR_IRQ: 1163 *result = cfg->intline; 1164 break; 1165 case PCI_IVAR_BUS: 1166 *result = cfg->bus; 1167 break; 1168 case PCI_IVAR_SLOT: 1169 *result = cfg->slot; 1170 break; 1171 case PCI_IVAR_FUNCTION: 1172 *result = cfg->func; 1173 break; 1174 default: 1175 return (ENOENT); 1176 } 1177 return (0); 1178} 1179 1180int 1181pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value) 1182{ 1183 struct pci_devinfo *dinfo; 1184 pcicfgregs *cfg; 1185 1186 dinfo = device_get_ivars(child); 1187 cfg = &dinfo->cfg; 1188 1189 switch (which) { 1190 case PCI_IVAR_ETHADDR: 1191 case PCI_IVAR_SUBVENDOR: 1192 case PCI_IVAR_SUBDEVICE: 1193 case PCI_IVAR_VENDOR: 1194 case PCI_IVAR_DEVICE: 1195 case PCI_IVAR_DEVID: 1196 case PCI_IVAR_CLASS: 1197 case PCI_IVAR_SUBCLASS: 1198 case PCI_IVAR_PROGIF: 1199 case PCI_IVAR_REVID: 1200 case PCI_IVAR_INTPIN: 1201 case PCI_IVAR_IRQ: 1202 case PCI_IVAR_BUS: 1203 case PCI_IVAR_SLOT: 1204 case PCI_IVAR_FUNCTION: 1205 return (EINVAL); /* disallow for now */ 1206 1207 default: 1208 return (ENOENT); 1209 } 1210 return (0); 1211} 1212 1213 1214#include "opt_ddb.h" 1215#ifdef DDB 1216#include <ddb/ddb.h> 1217#include <sys/cons.h> 1218 1219/* 1220 * List resources based on pci map registers, used for within ddb 1221 */ 1222 1223DB_SHOW_COMMAND(pciregs, db_pci_dump) 1224{ 1225 struct pci_devinfo *dinfo; 1226 struct devlist *devlist_head; 1227 struct pci_conf *p; 1228 const char *name; 1229 int i, error, none_count, nl; 1230 1231 none_count = 0; 1232 nl = 0; 1233 /* get the head of the device queue */ 1234 devlist_head = &pci_devq; 1235 1236 /* 1237 * Go through the list of devices and print out devices 1238 */ 1239 for (error = 0, i = 0, 1240 dinfo = STAILQ_FIRST(devlist_head); 1241 (dinfo != NULL) && (error == 0) && (i < pci_numdevs); 1242 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) { 1243 1244 /* Populate pd_name and pd_unit */ 1245 name = NULL; 1246 if (dinfo->cfg.dev) 1247 name = device_get_name(dinfo->cfg.dev); 1248 1249 p = &dinfo->conf; 1250 /* 1251 * XXX just take 20 for now... 1252 */ 1253 if (nl++ == 20) { 1254 int c; 1255 1256 db_printf("--More--"); 1257 c = cngetc(); 1258 db_printf("\r"); 1259 /* 1260 * A whole screenfull or just one line? 1261 */ 1262 switch (c) { 1263 case '\n': /* just one line */ 1264 nl = 20; 1265 break; 1266 case ' ': 1267 nl = 0; /* another screenfull */ 1268 break; 1269 default: /* exit */ 1270 db_printf("\n"); 1271 return; 1272 } 1273 } 1274 1275 db_printf("%s%d@pci%d:%d:%d:\tclass=0x%06x card=0x%08x " 1276 "chip=0x%08x rev=0x%02x hdr=0x%02x\n", 1277 (name && *name) ? name : "none", 1278 (name && *name) ? (int)device_get_unit(dinfo->cfg.dev) : 1279 none_count++, 1280 p->pc_sel.pc_bus, p->pc_sel.pc_dev, 1281 p->pc_sel.pc_func, (p->pc_class << 16) | 1282 (p->pc_subclass << 8) | p->pc_progif, 1283 (p->pc_subdevice << 16) | p->pc_subvendor, 1284 (p->pc_device << 16) | p->pc_vendor, 1285 p->pc_revid, p->pc_hdr); 1286 } 1287} 1288#endif /* DDB */ 1289 1290struct resource * 1291pci_alloc_resource(device_t dev, device_t child, int type, int *rid, 1292 u_long start, u_long end, u_long count, u_int flags) 1293{ 1294 struct pci_devinfo *dinfo = device_get_ivars(child); 1295 struct resource_list *rl = &dinfo->resources; 1296 pcicfgregs *cfg = &dinfo->cfg; 1297 1298 /* 1299 * Perform lazy resource allocation 1300 * 1301 * XXX add support here for SYS_RES_IOPORT and SYS_RES_MEMORY 1302 */ 1303 if (device_get_parent(child) == dev) { 1304 /* 1305 * If the child device doesn't have an interrupt routed 1306 * and is deserving of an interrupt, try to assign it one. 1307 */ 1308 if ((type == SYS_RES_IRQ) && 1309 !PCI_INTERRUPT_VALID(cfg->intline) && 1310 (cfg->intpin != 0)) { 1311 cfg->intline = PCIB_ROUTE_INTERRUPT( 1312 device_get_parent(dev), child, cfg->intpin); 1313 if (PCI_INTERRUPT_VALID(cfg->intline)) { 1314 pci_write_config(child, PCIR_INTLINE, 1315 cfg->intline, 1); 1316 resource_list_add(rl, SYS_RES_IRQ, 0, 1317 cfg->intline, cfg->intline, 1); 1318 } 1319 } 1320 } 1321 1322 return (resource_list_alloc(rl, dev, child, type, rid, 1323 start, end, count, flags)); 1324} 1325 1326void 1327pci_delete_resource(device_t dev, device_t child, int type, int rid) 1328{ 1329 struct pci_devinfo *dinfo; 1330 struct resource_list *rl; 1331 struct resource_list_entry *rle; 1332 1333 if (device_get_parent(child) != dev) 1334 return; 1335 1336 dinfo = device_get_ivars(child); 1337 rl = &dinfo->resources; 1338 rle = resource_list_find(rl, type, rid); 1339 if (rle) { 1340 if (rle->res) { 1341 if (rman_get_device(rle->res) != dev || 1342 rman_get_flags(rle->res) & RF_ACTIVE) { 1343 device_printf(dev, "delete_resource: " 1344 "Resource still owned by child, oops. " 1345 "(type=%d, rid=%d, addr=%lx)\n", 1346 rle->type, rle->rid, 1347 rman_get_start(rle->res)); 1348 return; 1349 } 1350 bus_release_resource(dev, type, rid, rle->res); 1351 } 1352 resource_list_delete(rl, type, rid); 1353 } 1354 /* 1355 * Why do we turn off the PCI configuration BAR when we delete a 1356 * resource? -- imp 1357 */ 1358 pci_write_config(child, rid, 0, 4); 1359 BUS_DELETE_RESOURCE(device_get_parent(dev), child, type, rid); 1360} 1361 1362struct resource_list * 1363pci_get_resource_list (device_t dev, device_t child) 1364{ 1365 struct pci_devinfo * dinfo = device_get_ivars(child); 1366 struct resource_list * rl = &dinfo->resources; 1367 1368 if (!rl) 1369 return (NULL); 1370 1371 return (rl); 1372} 1373 1374u_int32_t 1375pci_read_config_method(device_t dev, device_t child, int reg, int width) 1376{ 1377 struct pci_devinfo *dinfo = device_get_ivars(child); 1378 pcicfgregs *cfg = &dinfo->cfg; 1379 1380 return (PCIB_READ_CONFIG(device_get_parent(dev), 1381 cfg->bus, cfg->slot, cfg->func, reg, width)); 1382} 1383 1384void 1385pci_write_config_method(device_t dev, device_t child, int reg, 1386 u_int32_t val, int width) 1387{ 1388 struct pci_devinfo *dinfo = device_get_ivars(child); 1389 pcicfgregs *cfg = &dinfo->cfg; 1390 1391 PCIB_WRITE_CONFIG(device_get_parent(dev), 1392 cfg->bus, cfg->slot, cfg->func, reg, val, width); 1393} 1394 1395int 1396pci_child_location_str_method(device_t cbdev, device_t child, char *buf, 1397 size_t buflen) 1398{ 1399 struct pci_devinfo *dinfo; 1400 pcicfgregs *cfg; 1401 1402 dinfo = device_get_ivars(child); 1403 cfg = &dinfo->cfg; 1404 snprintf(buf, buflen, "slot=%d function=%d", pci_get_slot(child), 1405 pci_get_function(child)); 1406 return (0); 1407} 1408 1409int 1410pci_child_pnpinfo_str_method(device_t cbdev, device_t child, char *buf, 1411 size_t buflen) 1412{ 1413 struct pci_devinfo *dinfo; 1414 pcicfgregs *cfg; 1415 1416 dinfo = device_get_ivars(child); 1417 cfg = &dinfo->cfg; 1418 snprintf(buf, buflen, "vendor=0x%04x device=0x%04x subvendor=0x%04x " 1419 "subdevice=0x%04x class=0x%02x%02x%02x", cfg->vendor, cfg->device, 1420 cfg->subvendor, cfg->subdevice, cfg->baseclass, cfg->subclass, 1421 cfg->progif); 1422 return (0); 1423} 1424 1425static int 1426pci_modevent(module_t mod, int what, void *arg) 1427{ 1428 static dev_t pci_cdev; 1429 1430 switch (what) { 1431 case MOD_LOAD: 1432 STAILQ_INIT(&pci_devq); 1433 pci_generation = 0; 1434 pci_cdev = make_dev(&pcicdev, 0, UID_ROOT, GID_WHEEL, 0644, 1435 "pci"); 1436 pci_load_vendor_data(); 1437 break; 1438 1439 case MOD_UNLOAD: 1440 destroy_dev(pci_cdev); 1441 break; 1442 } 1443 1444 return (0); 1445} 1446