pci.c revision 110974
1/* 2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 3 * Copyright (c) 2000, Michael Smith <msmith@freebsd.org> 4 * Copyright (c) 2000, BSDi 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * $FreeBSD: head/sys/dev/pci/pci.c 110974 2003-02-16 02:02:44Z imp $ 29 * 30 */ 31 32#include "opt_bus.h" 33 34#include <sys/param.h> 35#include <sys/systm.h> 36#include <sys/malloc.h> 37#include <sys/module.h> 38#include <sys/linker.h> 39#include <sys/fcntl.h> 40#include <sys/conf.h> 41#include <sys/kernel.h> 42#include <sys/queue.h> 43#include <sys/sysctl.h> 44#include <sys/types.h> 45 46#include <vm/vm.h> 47#include <vm/pmap.h> 48#include <vm/vm_extern.h> 49 50#include <sys/bus.h> 51#include <machine/bus.h> 52#include <sys/rman.h> 53#include <machine/resource.h> 54 55#include <sys/pciio.h> 56#include <dev/pci/pcireg.h> 57#include <dev/pci/pcivar.h> 58#include <dev/pci/pci_private.h> 59 60#include "pcib_if.h" 61#include "pci_if.h" 62 63static u_int32_t pci_mapbase(unsigned mapreg); 64static int pci_maptype(unsigned mapreg); 65static int pci_mapsize(unsigned testval); 66static int pci_maprange(unsigned mapreg); 67static void pci_fixancient(pcicfgregs *cfg); 68 69static int pci_porten(device_t pcib, int b, int s, int f); 70static int pci_memen(device_t pcib, int b, int s, int f); 71static int pci_add_map(device_t pcib, int b, int s, int f, int reg, 72 struct resource_list *rl); 73static void pci_add_resources(device_t pcib, device_t dev); 74static int pci_probe(device_t dev); 75static int pci_attach(device_t dev); 76static void pci_load_vendor_data(void); 77static int pci_describe_parse_line(char **ptr, int *vendor, 78 int *device, char **desc); 79static char *pci_describe_device(device_t dev); 80static int pci_modevent(module_t mod, int what, void *arg); 81 82static device_method_t pci_methods[] = { 83 /* Device interface */ 84 DEVMETHOD(device_probe, pci_probe), 85 DEVMETHOD(device_attach, pci_attach), 86 DEVMETHOD(device_shutdown, bus_generic_shutdown), 87 DEVMETHOD(device_suspend, bus_generic_suspend), 88 DEVMETHOD(device_resume, bus_generic_resume), 89 90 /* Bus interface */ 91 DEVMETHOD(bus_print_child, pci_print_child), 92 DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch), 93 DEVMETHOD(bus_read_ivar, pci_read_ivar), 94 DEVMETHOD(bus_write_ivar, pci_write_ivar), 95 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 96 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 97 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 98 99 DEVMETHOD(bus_get_resource_list,pci_get_resource_list), 100 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource), 101 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource), 102 DEVMETHOD(bus_delete_resource, pci_delete_resource), 103 DEVMETHOD(bus_alloc_resource, pci_alloc_resource), 104 DEVMETHOD(bus_release_resource, bus_generic_rl_release_resource), 105 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 106 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 107 108 /* PCI interface */ 109 DEVMETHOD(pci_read_config, pci_read_config_method), 110 DEVMETHOD(pci_write_config, pci_write_config_method), 111 DEVMETHOD(pci_enable_busmaster, pci_enable_busmaster_method), 112 DEVMETHOD(pci_disable_busmaster, pci_disable_busmaster_method), 113 DEVMETHOD(pci_enable_io, pci_enable_io_method), 114 DEVMETHOD(pci_disable_io, pci_disable_io_method), 115 DEVMETHOD(pci_get_powerstate, pci_get_powerstate_method), 116 DEVMETHOD(pci_set_powerstate, pci_set_powerstate_method), 117 118 { 0, 0 } 119}; 120 121static driver_t pci_driver = { 122 "pci", 123 pci_methods, 124 0, /* no softc */ 125}; 126 127devclass_t pci_devclass; 128DRIVER_MODULE(pci, pcib, pci_driver, pci_devclass, pci_modevent, 0); 129MODULE_VERSION(pci, 1); 130 131static char *pci_vendordata; 132static size_t pci_vendordata_size; 133 134 135struct pci_quirk { 136 u_int32_t devid; /* Vendor/device of the card */ 137 int type; 138#define PCI_QUIRK_MAP_REG 1 /* PCI map register in weird place */ 139 int arg1; 140 int arg2; 141}; 142 143struct pci_quirk pci_quirks[] = { 144 /* The Intel 82371AB and 82443MX has a map register at offset 0x90. */ 145 { 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 146 { 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 147 /* As does the Serverworks OSB4 (the SMBus mapping register) */ 148 { 0x02001166, PCI_QUIRK_MAP_REG, 0x90, 0 }, 149 150 { 0 } 151}; 152 153/* map register information */ 154#define PCI_MAPMEM 0x01 /* memory map */ 155#define PCI_MAPMEMP 0x02 /* prefetchable memory map */ 156#define PCI_MAPPORT 0x04 /* port map */ 157 158struct devlist pci_devq; 159u_int32_t pci_generation; 160u_int32_t pci_numdevs = 0; 161 162/* sysctl vars */ 163SYSCTL_NODE(_hw, OID_AUTO, pci, CTLFLAG_RD, 0, "PCI bus tuning parameters"); 164 165static int pci_enable_io_modes = 1; 166TUNABLE_INT("hw.pci.enable_io_modes", (int *)&pci_enable_io_modes); 167SYSCTL_INT(_hw_pci, OID_AUTO, enable_io_modes, CTLFLAG_RW, 168 &pci_enable_io_modes, 1, 169 "Enable I/O and memory bits in the config register. Some BIOSes do not\n\ 170enable these bits correctly. We'd like to do this all the time, but there\n\ 171are some peripherals that this causes problems with."); 172 173/* Find a device_t by bus/slot/function */ 174 175device_t 176pci_find_bsf(u_int8_t bus, u_int8_t slot, u_int8_t func) 177{ 178 struct pci_devinfo *dinfo; 179 180 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 181 if ((dinfo->cfg.bus == bus) && 182 (dinfo->cfg.slot == slot) && 183 (dinfo->cfg.func == func)) { 184 return (dinfo->cfg.dev); 185 } 186 } 187 188 return (NULL); 189} 190 191/* Find a device_t by vendor/device ID */ 192 193device_t 194pci_find_device(u_int16_t vendor, u_int16_t device) 195{ 196 struct pci_devinfo *dinfo; 197 198 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 199 if ((dinfo->cfg.vendor == vendor) && 200 (dinfo->cfg.device == device)) { 201 return (dinfo->cfg.dev); 202 } 203 } 204 205 return (NULL); 206} 207 208/* return base address of memory or port map */ 209 210static u_int32_t 211pci_mapbase(unsigned mapreg) 212{ 213 int mask = 0x03; 214 if ((mapreg & 0x01) == 0) 215 mask = 0x0f; 216 return (mapreg & ~mask); 217} 218 219/* return map type of memory or port map */ 220 221static int 222pci_maptype(unsigned mapreg) 223{ 224 static u_int8_t maptype[0x10] = { 225 PCI_MAPMEM, PCI_MAPPORT, 226 PCI_MAPMEM, 0, 227 PCI_MAPMEM, PCI_MAPPORT, 228 0, 0, 229 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT, 230 PCI_MAPMEM|PCI_MAPMEMP, 0, 231 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT, 232 0, 0, 233 }; 234 235 return maptype[mapreg & 0x0f]; 236} 237 238/* return log2 of map size decoded for memory or port map */ 239 240static int 241pci_mapsize(unsigned testval) 242{ 243 int ln2size; 244 245 testval = pci_mapbase(testval); 246 ln2size = 0; 247 if (testval != 0) { 248 while ((testval & 1) == 0) 249 { 250 ln2size++; 251 testval >>= 1; 252 } 253 } 254 return (ln2size); 255} 256 257/* return log2 of address range supported by map register */ 258 259static int 260pci_maprange(unsigned mapreg) 261{ 262 int ln2range = 0; 263 switch (mapreg & 0x07) { 264 case 0x00: 265 case 0x01: 266 case 0x05: 267 ln2range = 32; 268 break; 269 case 0x02: 270 ln2range = 20; 271 break; 272 case 0x04: 273 ln2range = 64; 274 break; 275 } 276 return (ln2range); 277} 278 279/* adjust some values from PCI 1.0 devices to match 2.0 standards ... */ 280 281static void 282pci_fixancient(pcicfgregs *cfg) 283{ 284 if (cfg->hdrtype != 0) 285 return; 286 287 /* PCI to PCI bridges use header type 1 */ 288 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI) 289 cfg->hdrtype = 1; 290} 291 292/* extract header type specific config data */ 293 294void 295pci_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg) 296{ 297#define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 298 switch (cfg->hdrtype) { 299 case 0: 300 cfg->subvendor = REG(PCIR_SUBVEND_0, 2); 301 cfg->subdevice = REG(PCIR_SUBDEV_0, 2); 302 cfg->nummaps = PCI_MAXMAPS_0; 303 break; 304 case 1: 305 cfg->subvendor = REG(PCIR_SUBVEND_1, 2); 306 cfg->subdevice = REG(PCIR_SUBDEV_1, 2); 307 cfg->nummaps = PCI_MAXMAPS_1; 308 break; 309 case 2: 310 cfg->subvendor = REG(PCIR_SUBVEND_2, 2); 311 cfg->subdevice = REG(PCIR_SUBDEV_2, 2); 312 cfg->nummaps = PCI_MAXMAPS_2; 313 break; 314 } 315#undef REG 316} 317 318/* read configuration header into pcicfgregs structure */ 319 320struct pci_devinfo * 321pci_read_device(device_t pcib, int b, int s, int f, size_t size) 322{ 323#define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 324 pcicfgregs *cfg = NULL; 325 struct pci_devinfo *devlist_entry; 326 struct devlist *devlist_head; 327 328 devlist_head = &pci_devq; 329 330 devlist_entry = NULL; 331 332 if (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_DEVVENDOR, 4) != -1) { 333 devlist_entry = malloc(size, M_DEVBUF, M_ZERO); 334 if (devlist_entry == NULL) 335 return (NULL); 336 337 cfg = &devlist_entry->cfg; 338 339 cfg->bus = b; 340 cfg->slot = s; 341 cfg->func = f; 342 cfg->vendor = REG(PCIR_VENDOR, 2); 343 cfg->device = REG(PCIR_DEVICE, 2); 344 cfg->cmdreg = REG(PCIR_COMMAND, 2); 345 cfg->statreg = REG(PCIR_STATUS, 2); 346 cfg->baseclass = REG(PCIR_CLASS, 1); 347 cfg->subclass = REG(PCIR_SUBCLASS, 1); 348 cfg->progif = REG(PCIR_PROGIF, 1); 349 cfg->revid = REG(PCIR_REVID, 1); 350 cfg->hdrtype = REG(PCIR_HEADERTYPE, 1); 351 cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1); 352 cfg->lattimer = REG(PCIR_LATTIMER, 1); 353 cfg->intpin = REG(PCIR_INTPIN, 1); 354 cfg->intline = REG(PCIR_INTLINE, 1); 355 356 cfg->mingnt = REG(PCIR_MINGNT, 1); 357 cfg->maxlat = REG(PCIR_MAXLAT, 1); 358 359 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0; 360 cfg->hdrtype &= ~PCIM_MFDEV; 361 362 pci_fixancient(cfg); 363 pci_hdrtypedata(pcib, b, s, f, cfg); 364 365 if (REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT) 366 pci_read_extcap(pcib, cfg); 367 368 STAILQ_INSERT_TAIL(devlist_head, devlist_entry, pci_links); 369 370 devlist_entry->conf.pc_sel.pc_bus = cfg->bus; 371 devlist_entry->conf.pc_sel.pc_dev = cfg->slot; 372 devlist_entry->conf.pc_sel.pc_func = cfg->func; 373 devlist_entry->conf.pc_hdr = cfg->hdrtype; 374 375 devlist_entry->conf.pc_subvendor = cfg->subvendor; 376 devlist_entry->conf.pc_subdevice = cfg->subdevice; 377 devlist_entry->conf.pc_vendor = cfg->vendor; 378 devlist_entry->conf.pc_device = cfg->device; 379 380 devlist_entry->conf.pc_class = cfg->baseclass; 381 devlist_entry->conf.pc_subclass = cfg->subclass; 382 devlist_entry->conf.pc_progif = cfg->progif; 383 devlist_entry->conf.pc_revid = cfg->revid; 384 385 pci_numdevs++; 386 pci_generation++; 387 } 388 return (devlist_entry); 389#undef REG 390} 391 392void 393pci_read_extcap(device_t pcib, pcicfgregs *cfg) 394{ 395#define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w) 396 int ptr, nextptr, ptrptr; 397 398 switch (cfg->hdrtype) { 399 case 0: 400 ptrptr = 0x34; 401 break; 402 case 2: 403 ptrptr = 0x14; 404 break; 405 default: 406 return; /* no extended capabilities support */ 407 } 408 nextptr = REG(ptrptr, 1); /* sanity check? */ 409 410 /* 411 * Read capability entries. 412 */ 413 while (nextptr != 0) { 414 /* Sanity check */ 415 if (nextptr > 255) { 416 printf("illegal PCI extended capability offset %d\n", 417 nextptr); 418 return; 419 } 420 /* Find the next entry */ 421 ptr = nextptr; 422 nextptr = REG(ptr + 1, 1); 423 424 /* Process this entry */ 425 switch (REG(ptr, 1)) { 426 case 0x01: /* PCI power management */ 427 if (cfg->pp_cap == 0) { 428 cfg->pp_cap = REG(ptr + PCIR_POWER_CAP, 2); 429 cfg->pp_status = ptr + PCIR_POWER_STATUS; 430 cfg->pp_pmcsr = ptr + PCIR_POWER_PMCSR; 431 if ((nextptr - ptr) > PCIR_POWER_DATA) 432 cfg->pp_data = ptr + PCIR_POWER_DATA; 433 } 434 break; 435 default: 436 break; 437 } 438 } 439#undef REG 440} 441 442/* free pcicfgregs structure and all depending data structures */ 443 444int 445pci_freecfg(struct pci_devinfo *dinfo) 446{ 447 struct devlist *devlist_head; 448 449 devlist_head = &pci_devq; 450 451 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links); 452 free(dinfo, M_DEVBUF); 453 454 /* increment the generation count */ 455 pci_generation++; 456 457 /* we're losing one device */ 458 pci_numdevs--; 459 return (0); 460} 461 462/* 463 * PCI power manangement 464 */ 465int 466pci_set_powerstate_method(device_t dev, device_t child, int state) 467{ 468 struct pci_devinfo *dinfo = device_get_ivars(child); 469 pcicfgregs *cfg = &dinfo->cfg; 470 u_int16_t status; 471 int result; 472 473 if (cfg->pp_cap != 0) { 474 status = PCI_READ_CONFIG(dev, child, cfg->pp_status, 2) & ~PCIM_PSTAT_DMASK; 475 result = 0; 476 switch (state) { 477 case PCI_POWERSTATE_D0: 478 status |= PCIM_PSTAT_D0; 479 break; 480 case PCI_POWERSTATE_D1: 481 if (cfg->pp_cap & PCIM_PCAP_D1SUPP) { 482 status |= PCIM_PSTAT_D1; 483 } else { 484 result = EOPNOTSUPP; 485 } 486 break; 487 case PCI_POWERSTATE_D2: 488 if (cfg->pp_cap & PCIM_PCAP_D2SUPP) { 489 status |= PCIM_PSTAT_D2; 490 } else { 491 result = EOPNOTSUPP; 492 } 493 break; 494 case PCI_POWERSTATE_D3: 495 status |= PCIM_PSTAT_D3; 496 break; 497 default: 498 result = EINVAL; 499 } 500 if (result == 0) 501 PCI_WRITE_CONFIG(dev, child, cfg->pp_status, status, 2); 502 } else { 503 result = ENXIO; 504 } 505 return(result); 506} 507 508int 509pci_get_powerstate_method(device_t dev, device_t child) 510{ 511 struct pci_devinfo *dinfo = device_get_ivars(child); 512 pcicfgregs *cfg = &dinfo->cfg; 513 u_int16_t status; 514 int result; 515 516 if (cfg->pp_cap != 0) { 517 status = PCI_READ_CONFIG(dev, child, cfg->pp_status, 2); 518 switch (status & PCIM_PSTAT_DMASK) { 519 case PCIM_PSTAT_D0: 520 result = PCI_POWERSTATE_D0; 521 break; 522 case PCIM_PSTAT_D1: 523 result = PCI_POWERSTATE_D1; 524 break; 525 case PCIM_PSTAT_D2: 526 result = PCI_POWERSTATE_D2; 527 break; 528 case PCIM_PSTAT_D3: 529 result = PCI_POWERSTATE_D3; 530 break; 531 default: 532 result = PCI_POWERSTATE_UNKNOWN; 533 break; 534 } 535 } else { 536 /* No support, device is always at D0 */ 537 result = PCI_POWERSTATE_D0; 538 } 539 return(result); 540} 541 542/* 543 * Some convenience functions for PCI device drivers. 544 */ 545 546static __inline void 547pci_set_command_bit(device_t dev, device_t child, u_int16_t bit) 548{ 549 u_int16_t command; 550 551 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 552 command |= bit; 553 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 554} 555 556static __inline void 557pci_clear_command_bit(device_t dev, device_t child, u_int16_t bit) 558{ 559 u_int16_t command; 560 561 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 562 command &= ~bit; 563 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 564} 565 566void 567pci_enable_busmaster_method(device_t dev, device_t child) 568{ 569 pci_set_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 570} 571 572void 573pci_disable_busmaster_method(device_t dev, device_t child) 574{ 575 pci_clear_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 576} 577 578void 579pci_enable_io_method(device_t dev, device_t child, int space) 580{ 581 switch(space) { 582 case SYS_RES_IOPORT: 583 pci_set_command_bit(dev, child, PCIM_CMD_PORTEN); 584 break; 585 case SYS_RES_MEMORY: 586 pci_set_command_bit(dev, child, PCIM_CMD_MEMEN); 587 break; 588 } 589} 590 591void 592pci_disable_io_method(device_t dev, device_t child, int space) 593{ 594 switch(space) { 595 case SYS_RES_IOPORT: 596 pci_clear_command_bit(dev, child, PCIM_CMD_PORTEN); 597 break; 598 case SYS_RES_MEMORY: 599 pci_clear_command_bit(dev, child, PCIM_CMD_MEMEN); 600 break; 601 } 602} 603 604/* 605 * New style pci driver. Parent device is either a pci-host-bridge or a 606 * pci-pci-bridge. Both kinds are represented by instances of pcib. 607 */ 608 609void 610pci_print_verbose(struct pci_devinfo *dinfo) 611{ 612 if (bootverbose) { 613 pcicfgregs *cfg = &dinfo->cfg; 614 615 printf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n", 616 cfg->vendor, cfg->device, cfg->revid); 617 printf("\tbus=%d, slot=%d, func=%d\n", 618 cfg->bus, cfg->slot, cfg->func); 619 printf("\tclass=%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n", 620 cfg->baseclass, cfg->subclass, cfg->progif, cfg->hdrtype, 621 cfg->mfdev); 622 printf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n", 623 cfg->cmdreg, cfg->statreg, cfg->cachelnsz); 624 printf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n", 625 cfg->lattimer, cfg->lattimer * 30, cfg->mingnt, 626 cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250); 627 if (cfg->intpin > 0) 628 printf("\tintpin=%c, irq=%d\n", 629 cfg->intpin +'a' -1, cfg->intline); 630 if (cfg->pp_cap) { 631 u_int16_t status; 632 633 status = pci_read_config(cfg->dev, cfg->pp_status, 2); 634 printf("\tpowerspec %d supports D0%s%s D3 current D%d\n", 635 cfg->pp_cap & PCIM_PCAP_SPEC, 636 cfg->pp_cap & PCIM_PCAP_D1SUPP ? " D1" : "", 637 cfg->pp_cap & PCIM_PCAP_D2SUPP ? " D2" : "", 638 status & PCIM_PSTAT_DMASK); 639 } 640 } 641} 642 643static int 644pci_porten(device_t pcib, int b, int s, int f) 645{ 646 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2) 647 & PCIM_CMD_PORTEN) != 0; 648} 649 650static int 651pci_memen(device_t pcib, int b, int s, int f) 652{ 653 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2) 654 & PCIM_CMD_MEMEN) != 0; 655} 656 657/* 658 * Add a resource based on a pci map register. Return 1 if the map 659 * register is a 32bit map register or 2 if it is a 64bit register. 660 */ 661static int 662pci_add_map(device_t pcib, int b, int s, int f, int reg, 663 struct resource_list *rl) 664{ 665 u_int32_t map; 666 u_int64_t base; 667 u_int8_t ln2size; 668 u_int8_t ln2range; 669 u_int32_t testval; 670 u_int16_t cmd; 671 int type; 672 673 map = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4); 674 675 if (map == 0 || map == 0xffffffff) 676 return (1); /* skip invalid entry */ 677 678 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, 0xffffffff, 4); 679 testval = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4); 680 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, map, 4); 681 682 base = pci_mapbase(map); 683 if (pci_maptype(map) & PCI_MAPMEM) 684 type = SYS_RES_MEMORY; 685 else 686 type = SYS_RES_IOPORT; 687 ln2size = pci_mapsize(testval); 688 ln2range = pci_maprange(testval); 689 if (ln2range == 64) { 690 /* Read the other half of a 64bit map register */ 691 base |= (u_int64_t) PCIB_READ_CONFIG(pcib, b, s, f, reg + 4, 4) << 32; 692 } 693 694 if (bootverbose) { 695 printf("\tmap[%02x]: type %x, range %2d, base %08x, size %2d", 696 reg, pci_maptype(map), ln2range, 697 (unsigned int) base, ln2size); 698 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) 699 printf(", port disabled\n"); 700 else if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) 701 printf(", memory disabled\n"); 702 else 703 printf(", enabled\n"); 704 } 705 706 /* 707 * This code theoretically does the right thing, but has 708 * undesirable side effects in some cases where 709 * peripherals respond oddly to having these bits 710 * enabled. Leave them alone by default. 711 */ 712 if (pci_enable_io_modes) { 713 /* Turn on resources that have been left off by a lazy BIOS */ 714 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) { 715 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2); 716 cmd |= PCIM_CMD_PORTEN; 717 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2); 718 } 719 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) { 720 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2); 721 cmd |= PCIM_CMD_MEMEN; 722 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2); 723 } 724 } else { 725 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) 726 return (1); 727 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) 728 return (1); 729 } 730 resource_list_add(rl, type, reg, base, base + (1 << ln2size) - 1, 731 (1 << ln2size)); 732 733 return ((ln2range == 64) ? 2 : 1); 734} 735 736static void 737pci_add_resources(device_t pcib, device_t dev) 738{ 739 struct pci_devinfo *dinfo = device_get_ivars(dev); 740 pcicfgregs *cfg = &dinfo->cfg; 741 struct resource_list *rl = &dinfo->resources; 742 struct pci_quirk *q; 743 int b, i, f, s; 744 745 b = cfg->bus; 746 s = cfg->slot; 747 f = cfg->func; 748 for (i = 0; i < cfg->nummaps;) { 749 i += pci_add_map(pcib, b, s, f, PCIR_MAPS + i*4, rl); 750 } 751 752 for (q = &pci_quirks[0]; q->devid; q++) { 753 if (q->devid == ((cfg->device << 16) | cfg->vendor) 754 && q->type == PCI_QUIRK_MAP_REG) 755 pci_add_map(pcib, b, s, f, q->arg1, rl); 756 } 757 758 if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline)) { 759#ifdef __ia64__ 760 /* 761 * Re-route interrupts on ia64 so that we can get the 762 * I/O SAPIC interrupt numbers (the BIOS leaves legacy 763 * PIC interrupt numbers in the intline registers). 764 */ 765 cfg->intline = PCIB_ROUTE_INTERRUPT(pcib, dev, cfg->intpin); 766#endif 767 resource_list_add(rl, SYS_RES_IRQ, 0, cfg->intline, 768 cfg->intline, 1); 769 } 770} 771 772void 773pci_add_children(device_t dev, int busno, size_t dinfo_size) 774{ 775 device_t pcib = device_get_parent(dev); 776 struct pci_devinfo *dinfo; 777 int maxslots; 778 int s, f, pcifunchigh; 779 780 KASSERT(dinfo_size >= sizeof(struct pci_devinfo), 781 ("dinfo_size too small")); 782 maxslots = PCIB_MAXSLOTS(pcib); 783 for (s = 0; s <= maxslots; s++) { 784 pcifunchigh = 0; 785 for (f = 0; f <= pcifunchigh; f++) { 786 dinfo = pci_read_device(pcib, busno, s, f, dinfo_size); 787 if (dinfo != NULL) { 788 if (dinfo->cfg.mfdev) 789 pcifunchigh = PCI_FUNCMAX; 790 pci_add_child(dev, dinfo); 791 } 792 } 793 } 794} 795 796void 797pci_add_child(device_t bus, struct pci_devinfo *dinfo) 798{ 799 device_t pcib; 800 801 pcib = device_get_parent(bus); 802 dinfo->cfg.dev = device_add_child(bus, NULL, -1); 803 device_set_ivars(dinfo->cfg.dev, dinfo); 804 pci_add_resources(pcib, dinfo->cfg.dev); 805 pci_print_verbose(dinfo); 806} 807 808static int 809pci_probe(device_t dev) 810{ 811 812 device_set_desc(dev, "PCI bus"); 813 814 /* Allow other subclasses to override this driver. */ 815 return (-1000); 816} 817 818static int 819pci_attach(device_t dev) 820{ 821 int busno; 822 823 /* 824 * Since there can be multiple independantly numbered PCI 825 * busses on some large alpha systems, we can't use the unit 826 * number to decide what bus we are probing. We ask the parent 827 * pcib what our bus number is. 828 */ 829 busno = pcib_get_bus(dev); 830 if (bootverbose) 831 device_printf(dev, "physical bus=%d\n", busno); 832 833 pci_add_children(dev, busno, sizeof(struct pci_devinfo)); 834 835 return (bus_generic_attach(dev)); 836} 837 838static void 839pci_load_vendor_data(void) 840{ 841 caddr_t vendordata, info; 842 843 if ((vendordata = preload_search_by_type("pci_vendor_data")) != NULL) { 844 info = preload_search_info(vendordata, MODINFO_ADDR); 845 pci_vendordata = *(char **)info; 846 info = preload_search_info(vendordata, MODINFO_SIZE); 847 pci_vendordata_size = *(size_t *)info; 848 /* terminate the database */ 849 pci_vendordata[pci_vendordata_size] = '\n'; 850 } 851} 852 853int 854pci_print_child(device_t dev, device_t child) 855{ 856 struct pci_devinfo *dinfo; 857 struct resource_list *rl; 858 pcicfgregs *cfg; 859 int retval = 0; 860 861 dinfo = device_get_ivars(child); 862 cfg = &dinfo->cfg; 863 rl = &dinfo->resources; 864 865 retval += bus_print_child_header(dev, child); 866 867 retval += resource_list_print_type(rl, "port", SYS_RES_IOPORT, "%#lx"); 868 retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#lx"); 869 retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%ld"); 870 if (device_get_flags(dev)) 871 retval += printf(" flags %#x", device_get_flags(dev)); 872 873 retval += printf(" at device %d.%d", pci_get_slot(child), 874 pci_get_function(child)); 875 876 retval += bus_print_child_footer(dev, child); 877 878 return (retval); 879} 880 881static struct 882{ 883 int class; 884 int subclass; 885 char *desc; 886} pci_nomatch_tab[] = { 887 {PCIC_OLD, -1, "old"}, 888 {PCIC_OLD, PCIS_OLD_NONVGA, "non-VGA display device"}, 889 {PCIC_OLD, PCIS_OLD_VGA, "VGA-compatible display device"}, 890 {PCIC_STORAGE, -1, "mass storage"}, 891 {PCIC_STORAGE, PCIS_STORAGE_SCSI, "SCSI"}, 892 {PCIC_STORAGE, PCIS_STORAGE_IDE, "ATA"}, 893 {PCIC_STORAGE, PCIS_STORAGE_FLOPPY, "floppy disk"}, 894 {PCIC_STORAGE, PCIS_STORAGE_IPI, "IPI"}, 895 {PCIC_STORAGE, PCIS_STORAGE_RAID, "RAID"}, 896 {PCIC_NETWORK, -1, "network"}, 897 {PCIC_NETWORK, PCIS_NETWORK_ETHERNET, "ethernet"}, 898 {PCIC_NETWORK, PCIS_NETWORK_TOKENRING, "token ring"}, 899 {PCIC_NETWORK, PCIS_NETWORK_FDDI, "fddi"}, 900 {PCIC_NETWORK, PCIS_NETWORK_ATM, "ATM"}, 901 {PCIC_DISPLAY, -1, "display"}, 902 {PCIC_DISPLAY, PCIS_DISPLAY_VGA, "VGA"}, 903 {PCIC_DISPLAY, PCIS_DISPLAY_XGA, "XGA"}, 904 {PCIC_MULTIMEDIA, -1, "multimedia"}, 905 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_VIDEO, "video"}, 906 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_AUDIO, "audio"}, 907 {PCIC_MEMORY, -1, "memory"}, 908 {PCIC_MEMORY, PCIS_MEMORY_RAM, "RAM"}, 909 {PCIC_MEMORY, PCIS_MEMORY_FLASH, "flash"}, 910 {PCIC_BRIDGE, -1, "bridge"}, 911 {PCIC_BRIDGE, PCIS_BRIDGE_HOST, "HOST-PCI"}, 912 {PCIC_BRIDGE, PCIS_BRIDGE_ISA, "PCI-ISA"}, 913 {PCIC_BRIDGE, PCIS_BRIDGE_EISA, "PCI-EISA"}, 914 {PCIC_BRIDGE, PCIS_BRIDGE_MCA, "PCI-MCA"}, 915 {PCIC_BRIDGE, PCIS_BRIDGE_PCI, "PCI-PCI"}, 916 {PCIC_BRIDGE, PCIS_BRIDGE_PCMCIA, "PCI-PCMCIA"}, 917 {PCIC_BRIDGE, PCIS_BRIDGE_NUBUS, "PCI-NuBus"}, 918 {PCIC_BRIDGE, PCIS_BRIDGE_CARDBUS, "PCI-CardBus"}, 919 {PCIC_BRIDGE, PCIS_BRIDGE_OTHER, "PCI-unknown"}, 920 {PCIC_SIMPLECOMM, -1, "simple comms"}, 921 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_UART, "UART"}, /* could detect 16550 */ 922 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_PAR, "parallel port"}, 923 {PCIC_BASEPERIPH, -1, "base peripheral"}, 924 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PIC, "interrupt controller"}, 925 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_DMA, "DMA controller"}, 926 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_TIMER, "timer"}, 927 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_RTC, "realtime clock"}, 928 {PCIC_INPUTDEV, -1, "input device"}, 929 {PCIC_INPUTDEV, PCIS_INPUTDEV_KEYBOARD, "keyboard"}, 930 {PCIC_INPUTDEV, PCIS_INPUTDEV_DIGITIZER,"digitizer"}, 931 {PCIC_INPUTDEV, PCIS_INPUTDEV_MOUSE, "mouse"}, 932 {PCIC_DOCKING, -1, "docking station"}, 933 {PCIC_PROCESSOR, -1, "processor"}, 934 {PCIC_SERIALBUS, -1, "serial bus"}, 935 {PCIC_SERIALBUS, PCIS_SERIALBUS_FW, "FireWire"}, 936 {PCIC_SERIALBUS, PCIS_SERIALBUS_ACCESS, "AccessBus"}, 937 {PCIC_SERIALBUS, PCIS_SERIALBUS_SSA, "SSA"}, 938 {PCIC_SERIALBUS, PCIS_SERIALBUS_USB, "USB"}, 939 {PCIC_SERIALBUS, PCIS_SERIALBUS_FC, "Fibre Channel"}, 940 {PCIC_SERIALBUS, PCIS_SERIALBUS_SMBUS, "SMBus"}, 941 {0, 0, NULL} 942}; 943 944void 945pci_probe_nomatch(device_t dev, device_t child) 946{ 947 int i; 948 char *cp, *scp, *device; 949 950 /* 951 * Look for a listing for this device in a loaded device database. 952 */ 953 if ((device = pci_describe_device(child)) != NULL) { 954 device_printf(dev, "<%s>", device); 955 free(device, M_DEVBUF); 956 } else { 957 /* 958 * Scan the class/subclass descriptions for a general 959 * description. 960 */ 961 cp = "unknown"; 962 scp = NULL; 963 for (i = 0; pci_nomatch_tab[i].desc != NULL; i++) { 964 if (pci_nomatch_tab[i].class == pci_get_class(child)) { 965 if (pci_nomatch_tab[i].subclass == -1) { 966 cp = pci_nomatch_tab[i].desc; 967 } else if (pci_nomatch_tab[i].subclass == 968 pci_get_subclass(child)) { 969 scp = pci_nomatch_tab[i].desc; 970 } 971 } 972 } 973 device_printf(dev, "<%s%s%s>", 974 cp ? cp : "", 975 ((cp != NULL) && (scp != NULL)) ? ", " : "", 976 scp ? scp : ""); 977 } 978 printf(" at device %d.%d (no driver attached)\n", 979 pci_get_slot(child), pci_get_function(child)); 980 return; 981} 982 983/* 984 * Parse the PCI device database, if loaded, and return a pointer to a 985 * description of the device. 986 * 987 * The database is flat text formatted as follows: 988 * 989 * Any line not in a valid format is ignored. 990 * Lines are terminated with newline '\n' characters. 991 * 992 * A VENDOR line consists of the 4 digit (hex) vendor code, a TAB, then 993 * the vendor name. 994 * 995 * A DEVICE line is entered immediately below the corresponding VENDOR ID. 996 * - devices cannot be listed without a corresponding VENDOR line. 997 * A DEVICE line consists of a TAB, the 4 digit (hex) device code, 998 * another TAB, then the device name. 999 */ 1000 1001/* 1002 * Assuming (ptr) points to the beginning of a line in the database, 1003 * return the vendor or device and description of the next entry. 1004 * The value of (vendor) or (device) inappropriate for the entry type 1005 * is set to -1. Returns nonzero at the end of the database. 1006 * 1007 * Note that this is slightly unrobust in the face of corrupt data; 1008 * we attempt to safeguard against this by spamming the end of the 1009 * database with a newline when we initialise. 1010 */ 1011static int 1012pci_describe_parse_line(char **ptr, int *vendor, int *device, char **desc) 1013{ 1014 char *cp = *ptr; 1015 int left; 1016 1017 *device = -1; 1018 *vendor = -1; 1019 **desc = '\0'; 1020 for (;;) { 1021 left = pci_vendordata_size - (cp - pci_vendordata); 1022 if (left <= 0) { 1023 *ptr = cp; 1024 return(1); 1025 } 1026 1027 /* vendor entry? */ 1028 if (*cp != '\t' && 1029 sscanf(cp, "%x\t%80[^\n]", vendor, *desc) == 2) 1030 break; 1031 /* device entry? */ 1032 if (*cp == '\t' && 1033 sscanf(cp, "%x\t%80[^\n]", device, *desc) == 2) 1034 break; 1035 1036 /* skip to next line */ 1037 while (*cp != '\n' && left > 0) { 1038 cp++; 1039 left--; 1040 } 1041 if (*cp == '\n') { 1042 cp++; 1043 left--; 1044 } 1045 } 1046 /* skip to next line */ 1047 while (*cp != '\n' && left > 0) { 1048 cp++; 1049 left--; 1050 } 1051 if (*cp == '\n' && left > 0) 1052 cp++; 1053 *ptr = cp; 1054 return(0); 1055} 1056 1057static char * 1058pci_describe_device(device_t dev) 1059{ 1060 int vendor, device; 1061 char *desc, *vp, *dp, *line; 1062 1063 desc = vp = dp = NULL; 1064 1065 /* 1066 * If we have no vendor data, we can't do anything. 1067 */ 1068 if (pci_vendordata == NULL) 1069 goto out; 1070 1071 /* 1072 * Scan the vendor data looking for this device 1073 */ 1074 line = pci_vendordata; 1075 if ((vp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL) 1076 goto out; 1077 for (;;) { 1078 if (pci_describe_parse_line(&line, &vendor, &device, &vp)) 1079 goto out; 1080 if (vendor == pci_get_vendor(dev)) 1081 break; 1082 } 1083 if ((dp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL) 1084 goto out; 1085 for (;;) { 1086 if (pci_describe_parse_line(&line, &vendor, &device, &dp)) { 1087 *dp = 0; 1088 break; 1089 } 1090 if (vendor != -1) { 1091 *dp = 0; 1092 break; 1093 } 1094 if (device == pci_get_device(dev)) 1095 break; 1096 } 1097 if (dp[0] == '\0') 1098 snprintf(dp, 80, "0x%x", pci_get_device(dev)); 1099 if ((desc = malloc(strlen(vp) + strlen(dp) + 3, M_DEVBUF, M_NOWAIT)) != 1100 NULL) 1101 sprintf(desc, "%s, %s", vp, dp); 1102 out: 1103 if (vp != NULL) 1104 free(vp, M_DEVBUF); 1105 if (dp != NULL) 1106 free(dp, M_DEVBUF); 1107 return(desc); 1108} 1109 1110int 1111pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 1112{ 1113 struct pci_devinfo *dinfo; 1114 pcicfgregs *cfg; 1115 1116 dinfo = device_get_ivars(child); 1117 cfg = &dinfo->cfg; 1118 1119 switch (which) { 1120 case PCI_IVAR_ETHADDR: 1121 /* 1122 * The generic accessor doesn't deal with failure, so 1123 * we set the return value, then return an error. 1124 */ 1125 *((u_int8_t **) result) = NULL; 1126 return (EINVAL); 1127 case PCI_IVAR_SUBVENDOR: 1128 *result = cfg->subvendor; 1129 break; 1130 case PCI_IVAR_SUBDEVICE: 1131 *result = cfg->subdevice; 1132 break; 1133 case PCI_IVAR_VENDOR: 1134 *result = cfg->vendor; 1135 break; 1136 case PCI_IVAR_DEVICE: 1137 *result = cfg->device; 1138 break; 1139 case PCI_IVAR_DEVID: 1140 *result = (cfg->device << 16) | cfg->vendor; 1141 break; 1142 case PCI_IVAR_CLASS: 1143 *result = cfg->baseclass; 1144 break; 1145 case PCI_IVAR_SUBCLASS: 1146 *result = cfg->subclass; 1147 break; 1148 case PCI_IVAR_PROGIF: 1149 *result = cfg->progif; 1150 break; 1151 case PCI_IVAR_REVID: 1152 *result = cfg->revid; 1153 break; 1154 case PCI_IVAR_INTPIN: 1155 *result = cfg->intpin; 1156 break; 1157 case PCI_IVAR_IRQ: 1158 *result = cfg->intline; 1159 break; 1160 case PCI_IVAR_BUS: 1161 *result = cfg->bus; 1162 break; 1163 case PCI_IVAR_SLOT: 1164 *result = cfg->slot; 1165 break; 1166 case PCI_IVAR_FUNCTION: 1167 *result = cfg->func; 1168 break; 1169 default: 1170 return (ENOENT); 1171 } 1172 return (0); 1173} 1174 1175int 1176pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value) 1177{ 1178 struct pci_devinfo *dinfo; 1179 pcicfgregs *cfg; 1180 1181 dinfo = device_get_ivars(child); 1182 cfg = &dinfo->cfg; 1183 1184 switch (which) { 1185 case PCI_IVAR_ETHADDR: 1186 case PCI_IVAR_SUBVENDOR: 1187 case PCI_IVAR_SUBDEVICE: 1188 case PCI_IVAR_VENDOR: 1189 case PCI_IVAR_DEVICE: 1190 case PCI_IVAR_DEVID: 1191 case PCI_IVAR_CLASS: 1192 case PCI_IVAR_SUBCLASS: 1193 case PCI_IVAR_PROGIF: 1194 case PCI_IVAR_REVID: 1195 case PCI_IVAR_INTPIN: 1196 case PCI_IVAR_IRQ: 1197 case PCI_IVAR_BUS: 1198 case PCI_IVAR_SLOT: 1199 case PCI_IVAR_FUNCTION: 1200 return (EINVAL); /* disallow for now */ 1201 1202 default: 1203 return (ENOENT); 1204 } 1205 return (0); 1206} 1207 1208 1209#include "opt_ddb.h" 1210#ifdef DDB 1211#include <ddb/ddb.h> 1212#include <sys/cons.h> 1213 1214/* 1215 * List resources based on pci map registers, used for within ddb 1216 */ 1217 1218DB_SHOW_COMMAND(pciregs, db_pci_dump) 1219{ 1220 struct pci_devinfo *dinfo; 1221 struct devlist *devlist_head; 1222 struct pci_conf *p; 1223 const char *name; 1224 int i, error, none_count, nl; 1225 1226 none_count = 0; 1227 nl = 0; 1228 /* get the head of the device queue */ 1229 devlist_head = &pci_devq; 1230 1231 /* 1232 * Go through the list of devices and print out devices 1233 */ 1234 for (error = 0, i = 0, 1235 dinfo = STAILQ_FIRST(devlist_head); 1236 (dinfo != NULL) && (error == 0) && (i < pci_numdevs); 1237 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) { 1238 1239 /* Populate pd_name and pd_unit */ 1240 name = NULL; 1241 if (dinfo->cfg.dev) 1242 name = device_get_name(dinfo->cfg.dev); 1243 1244 p = &dinfo->conf; 1245 /* 1246 * XXX just take 20 for now... 1247 */ 1248 if (nl++ == 20) { 1249 int c; 1250 1251 db_printf("--More--"); 1252 c = cngetc(); 1253 db_printf("\r"); 1254 /* 1255 * A whole screenfull or just one line? 1256 */ 1257 switch (c) { 1258 case '\n': /* just one line */ 1259 nl = 20; 1260 break; 1261 case ' ': 1262 nl = 0; /* another screenfull */ 1263 break; 1264 default: /* exit */ 1265 db_printf("\n"); 1266 return; 1267 } 1268 } 1269 1270 db_printf("%s%d@pci%d:%d:%d:\tclass=0x%06x card=0x%08x " 1271 "chip=0x%08x rev=0x%02x hdr=0x%02x\n", 1272 (name && *name) ? name : "none", 1273 (name && *name) ? (int)device_get_unit(dinfo->cfg.dev) : 1274 none_count++, 1275 p->pc_sel.pc_bus, p->pc_sel.pc_dev, 1276 p->pc_sel.pc_func, (p->pc_class << 16) | 1277 (p->pc_subclass << 8) | p->pc_progif, 1278 (p->pc_subdevice << 16) | p->pc_subvendor, 1279 (p->pc_device << 16) | p->pc_vendor, 1280 p->pc_revid, p->pc_hdr); 1281 } 1282} 1283#endif /* DDB */ 1284 1285struct resource * 1286pci_alloc_resource(device_t dev, device_t child, int type, int *rid, 1287 u_long start, u_long end, u_long count, u_int flags) 1288{ 1289 struct pci_devinfo *dinfo = device_get_ivars(child); 1290 struct resource_list *rl = &dinfo->resources; 1291 pcicfgregs *cfg = &dinfo->cfg; 1292 1293 /* 1294 * Perform lazy resource allocation 1295 * 1296 * XXX add support here for SYS_RES_IOPORT and SYS_RES_MEMORY 1297 */ 1298 if (device_get_parent(child) == dev) { 1299 /* 1300 * If the child device doesn't have an interrupt routed 1301 * and is deserving of an interrupt, try to assign it one. 1302 */ 1303 if ((type == SYS_RES_IRQ) && 1304 !PCI_INTERRUPT_VALID(cfg->intline) && 1305 (cfg->intpin != 0)) { 1306 cfg->intline = PCIB_ROUTE_INTERRUPT( 1307 device_get_parent(dev), child, cfg->intpin); 1308 if (PCI_INTERRUPT_VALID(cfg->intline)) { 1309 pci_write_config(child, PCIR_INTLINE, 1310 cfg->intline, 1); 1311 resource_list_add(rl, SYS_RES_IRQ, 0, 1312 cfg->intline, cfg->intline, 1); 1313 } 1314 } 1315 } 1316 1317 return (resource_list_alloc(rl, dev, child, type, rid, 1318 start, end, count, flags)); 1319} 1320 1321void 1322pci_delete_resource(device_t dev, device_t child, int type, int rid) 1323{ 1324 struct pci_devinfo *dinfo; 1325 struct resource_list *rl; 1326 struct resource_list_entry *rle; 1327 1328 if (device_get_parent(child) != dev) 1329 return; 1330 1331 dinfo = device_get_ivars(child); 1332 rl = &dinfo->resources; 1333 rle = resource_list_find(rl, type, rid); 1334 if (rle) { 1335 if (rle->res) { 1336 if (rman_get_device(rle->res) != dev || 1337 rman_get_flags(rle->res) & RF_ACTIVE) { 1338 device_printf(dev, "delete_resource: " 1339 "Resource still owned by child, oops. " 1340 "(type=%d, rid=%d, addr=%lx)\n", 1341 rle->type, rle->rid, 1342 rman_get_start(rle->res)); 1343 return; 1344 } 1345 bus_release_resource(dev, type, rid, rle->res); 1346 } 1347 resource_list_delete(rl, type, rid); 1348 } 1349 /* 1350 * Why do we turn off the PCI configuration BAR when we delete a 1351 * resource? -- imp 1352 */ 1353 pci_write_config(child, rid, 0, 4); 1354 BUS_DELETE_RESOURCE(device_get_parent(dev), child, type, rid); 1355} 1356 1357struct resource_list * 1358pci_get_resource_list (device_t dev, device_t child) 1359{ 1360 struct pci_devinfo * dinfo = device_get_ivars(child); 1361 struct resource_list * rl = &dinfo->resources; 1362 1363 if (!rl) 1364 return (NULL); 1365 1366 return (rl); 1367} 1368 1369u_int32_t 1370pci_read_config_method(device_t dev, device_t child, int reg, int width) 1371{ 1372 struct pci_devinfo *dinfo = device_get_ivars(child); 1373 pcicfgregs *cfg = &dinfo->cfg; 1374 1375 return (PCIB_READ_CONFIG(device_get_parent(dev), 1376 cfg->bus, cfg->slot, cfg->func, reg, width)); 1377} 1378 1379void 1380pci_write_config_method(device_t dev, device_t child, int reg, 1381 u_int32_t val, int width) 1382{ 1383 struct pci_devinfo *dinfo = device_get_ivars(child); 1384 pcicfgregs *cfg = &dinfo->cfg; 1385 1386 PCIB_WRITE_CONFIG(device_get_parent(dev), 1387 cfg->bus, cfg->slot, cfg->func, reg, val, width); 1388} 1389 1390static int 1391pci_modevent(module_t mod, int what, void *arg) 1392{ 1393 static dev_t pci_cdev; 1394 1395 switch (what) { 1396 case MOD_LOAD: 1397 STAILQ_INIT(&pci_devq); 1398 pci_generation = 0; 1399 pci_cdev = make_dev(&pcicdev, 0, UID_ROOT, GID_WHEEL, 0644, 1400 "pci"); 1401 pci_load_vendor_data(); 1402 break; 1403 1404 case MOD_UNLOAD: 1405 destroy_dev(pci_cdev); 1406 break; 1407 } 1408 1409 return (0); 1410} 1411