pci.c revision 101243
1/* 2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 3 * Copyright (c) 2000, Michael Smith <msmith@freebsd.org> 4 * Copyright (c) 2000, BSDi 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * $FreeBSD: head/sys/dev/pci/pci.c 101243 2002-08-02 22:26:03Z imp $ 29 * 30 */ 31 32#include "opt_bus.h" 33 34#include <sys/param.h> 35#include <sys/systm.h> 36#include <sys/malloc.h> 37#include <sys/module.h> 38#include <sys/linker.h> 39#include <sys/fcntl.h> 40#include <sys/conf.h> 41#include <sys/kernel.h> 42#include <sys/queue.h> 43#include <sys/sysctl.h> 44#include <sys/types.h> 45 46#include <vm/vm.h> 47#include <vm/pmap.h> 48#include <vm/vm_extern.h> 49 50#include <sys/bus.h> 51#include <machine/bus.h> 52#include <sys/rman.h> 53#include <machine/resource.h> 54 55#include <sys/pciio.h> 56#include <dev/pci/pcireg.h> 57#include <dev/pci/pcivar.h> 58#include <dev/pci/pci_private.h> 59 60#include "pcib_if.h" 61#include "pci_if.h" 62 63static u_int32_t pci_mapbase(unsigned mapreg); 64static int pci_maptype(unsigned mapreg); 65static int pci_mapsize(unsigned testval); 66static int pci_maprange(unsigned mapreg); 67static void pci_fixancient(pcicfgregs *cfg); 68static void pci_hdrtypedata(device_t pcib, int b, int s, int f, 69 pcicfgregs *cfg); 70static void pci_read_extcap(device_t pcib, pcicfgregs *cfg); 71 72static int pci_porten(device_t pcib, int b, int s, int f); 73static int pci_memen(device_t pcib, int b, int s, int f); 74static int pci_add_map(device_t pcib, int b, int s, int f, int reg, 75 struct resource_list *rl); 76static void pci_add_resources(device_t pcib, int b, int s, int f, 77 device_t dev); 78static void pci_add_children(device_t dev, int busno); 79static int pci_probe(device_t dev); 80static int pci_describe_parse_line(char **ptr, int *vendor, 81 int *device, char **desc); 82static char *pci_describe_device(device_t dev); 83static int pci_modevent(module_t mod, int what, void *arg); 84 85static device_method_t pci_methods[] = { 86 /* Device interface */ 87 DEVMETHOD(device_probe, pci_probe), 88 DEVMETHOD(device_attach, bus_generic_attach), 89 DEVMETHOD(device_shutdown, bus_generic_shutdown), 90 DEVMETHOD(device_suspend, bus_generic_suspend), 91 DEVMETHOD(device_resume, bus_generic_resume), 92 93 /* Bus interface */ 94 DEVMETHOD(bus_print_child, pci_print_child), 95 DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch), 96 DEVMETHOD(bus_read_ivar, pci_read_ivar), 97 DEVMETHOD(bus_write_ivar, pci_write_ivar), 98 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 99 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 100 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 101 102 DEVMETHOD(bus_get_resource_list,pci_get_resource_list), 103 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource), 104 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource), 105 DEVMETHOD(bus_delete_resource, pci_delete_resource), 106 DEVMETHOD(bus_alloc_resource, pci_alloc_resource), 107 DEVMETHOD(bus_release_resource, bus_generic_rl_release_resource), 108 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 109 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 110 111 /* PCI interface */ 112 DEVMETHOD(pci_read_config, pci_read_config_method), 113 DEVMETHOD(pci_write_config, pci_write_config_method), 114 DEVMETHOD(pci_enable_busmaster, pci_enable_busmaster_method), 115 DEVMETHOD(pci_disable_busmaster, pci_disable_busmaster_method), 116 DEVMETHOD(pci_enable_io, pci_enable_io_method), 117 DEVMETHOD(pci_disable_io, pci_disable_io_method), 118 DEVMETHOD(pci_get_powerstate, pci_get_powerstate_method), 119 DEVMETHOD(pci_set_powerstate, pci_set_powerstate_method), 120 121 { 0, 0 } 122}; 123 124static driver_t pci_driver = { 125 "pci", 126 pci_methods, 127 0, /* no softc */ 128}; 129 130static devclass_t pci_devclass; 131DRIVER_MODULE(pci, pcib, pci_driver, pci_devclass, pci_modevent, 0); 132DRIVER_MODULE(pci, acpi_pcib, pci_driver, pci_devclass, pci_modevent, 0); 133MODULE_VERSION(pci, 1); 134 135static char *pci_vendordata; 136static size_t pci_vendordata_size; 137 138 139struct pci_quirk { 140 u_int32_t devid; /* Vendor/device of the card */ 141 int type; 142#define PCI_QUIRK_MAP_REG 1 /* PCI map register in weird place */ 143 int arg1; 144 int arg2; 145}; 146 147struct pci_quirk pci_quirks[] = { 148 /* The Intel 82371AB and 82443MX has a map register at offset 0x90. */ 149 { 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 150 { 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 151 /* As does the Serverworks OSB4 (the SMBus mapping register) */ 152 { 0x02001166, PCI_QUIRK_MAP_REG, 0x90, 0 }, 153 154 { 0 } 155}; 156 157/* map register information */ 158#define PCI_MAPMEM 0x01 /* memory map */ 159#define PCI_MAPMEMP 0x02 /* prefetchable memory map */ 160#define PCI_MAPPORT 0x04 /* port map */ 161 162struct devlist pci_devq; 163u_int32_t pci_generation; 164u_int32_t pci_numdevs = 0; 165 166/* sysctl vars */ 167SYSCTL_NODE(_hw, OID_AUTO, pci, CTLFLAG_RD, 0, "PCI bus tuning parameters"); 168 169int pci_enable_io_modes = 1; 170TUNABLE_INT("hw.pci.enable_io_modes", (int *)&pci_enable_io_modes); 171SYSCTL_INT(_hw_pci, OID_AUTO, enable_io_modes, CTLFLAG_RW, 172 &pci_enable_io_modes, 1, 173 "Enable I/O and memory bits in the config register. Some BIOSes do not\n\ 174enable these bits correctly. We'd like to do this all the time, but there\n\ 175are some peripherals that this causes problems with."); 176 177/* Find a device_t by bus/slot/function */ 178 179device_t 180pci_find_bsf (u_int8_t bus, u_int8_t slot, u_int8_t func) 181{ 182 struct pci_devinfo *dinfo; 183 184 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 185 if ((dinfo->cfg.bus == bus) && 186 (dinfo->cfg.slot == slot) && 187 (dinfo->cfg.func == func)) { 188 return (dinfo->cfg.dev); 189 } 190 } 191 192 return (NULL); 193} 194 195/* Find a device_t by vendor/device ID */ 196 197device_t 198pci_find_device (u_int16_t vendor, u_int16_t device) 199{ 200 struct pci_devinfo *dinfo; 201 202 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 203 if ((dinfo->cfg.vendor == vendor) && 204 (dinfo->cfg.device == device)) { 205 return (dinfo->cfg.dev); 206 } 207 } 208 209 return (NULL); 210} 211 212/* return base address of memory or port map */ 213 214static u_int32_t 215pci_mapbase(unsigned mapreg) 216{ 217 int mask = 0x03; 218 if ((mapreg & 0x01) == 0) 219 mask = 0x0f; 220 return (mapreg & ~mask); 221} 222 223/* return map type of memory or port map */ 224 225static int 226pci_maptype(unsigned mapreg) 227{ 228 static u_int8_t maptype[0x10] = { 229 PCI_MAPMEM, PCI_MAPPORT, 230 PCI_MAPMEM, 0, 231 PCI_MAPMEM, PCI_MAPPORT, 232 0, 0, 233 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT, 234 PCI_MAPMEM|PCI_MAPMEMP, 0, 235 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT, 236 0, 0, 237 }; 238 239 return maptype[mapreg & 0x0f]; 240} 241 242/* return log2 of map size decoded for memory or port map */ 243 244static int 245pci_mapsize(unsigned testval) 246{ 247 int ln2size; 248 249 testval = pci_mapbase(testval); 250 ln2size = 0; 251 if (testval != 0) { 252 while ((testval & 1) == 0) 253 { 254 ln2size++; 255 testval >>= 1; 256 } 257 } 258 return (ln2size); 259} 260 261/* return log2 of address range supported by map register */ 262 263static int 264pci_maprange(unsigned mapreg) 265{ 266 int ln2range = 0; 267 switch (mapreg & 0x07) { 268 case 0x00: 269 case 0x01: 270 case 0x05: 271 ln2range = 32; 272 break; 273 case 0x02: 274 ln2range = 20; 275 break; 276 case 0x04: 277 ln2range = 64; 278 break; 279 } 280 return (ln2range); 281} 282 283/* adjust some values from PCI 1.0 devices to match 2.0 standards ... */ 284 285static void 286pci_fixancient(pcicfgregs *cfg) 287{ 288 if (cfg->hdrtype != 0) 289 return; 290 291 /* PCI to PCI bridges use header type 1 */ 292 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI) 293 cfg->hdrtype = 1; 294} 295 296/* extract header type specific config data */ 297 298static void 299pci_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg) 300{ 301#define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 302 switch (cfg->hdrtype) { 303 case 0: 304 cfg->subvendor = REG(PCIR_SUBVEND_0, 2); 305 cfg->subdevice = REG(PCIR_SUBDEV_0, 2); 306 cfg->nummaps = PCI_MAXMAPS_0; 307 break; 308 case 1: 309 cfg->subvendor = REG(PCIR_SUBVEND_1, 2); 310 cfg->subdevice = REG(PCIR_SUBDEV_1, 2); 311 cfg->nummaps = PCI_MAXMAPS_1; 312 break; 313 case 2: 314 cfg->subvendor = REG(PCIR_SUBVEND_2, 2); 315 cfg->subdevice = REG(PCIR_SUBDEV_2, 2); 316 cfg->nummaps = PCI_MAXMAPS_2; 317 break; 318 } 319#undef REG 320} 321 322/* read configuration header into pcicfgregs structure */ 323 324struct pci_devinfo * 325pci_read_device(device_t pcib, int b, int s, int f, size_t size) 326{ 327#define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 328 pcicfgregs *cfg = NULL; 329 struct pci_devinfo *devlist_entry; 330 struct devlist *devlist_head; 331 332 devlist_head = &pci_devq; 333 334 devlist_entry = NULL; 335 336 if (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_DEVVENDOR, 4) != -1) { 337 devlist_entry = malloc(size, M_DEVBUF, M_WAITOK | M_ZERO); 338 if (devlist_entry == NULL) 339 return (NULL); 340 341 cfg = &devlist_entry->cfg; 342 343 cfg->bus = b; 344 cfg->slot = s; 345 cfg->func = f; 346 cfg->vendor = REG(PCIR_VENDOR, 2); 347 cfg->device = REG(PCIR_DEVICE, 2); 348 cfg->cmdreg = REG(PCIR_COMMAND, 2); 349 cfg->statreg = REG(PCIR_STATUS, 2); 350 cfg->baseclass = REG(PCIR_CLASS, 1); 351 cfg->subclass = REG(PCIR_SUBCLASS, 1); 352 cfg->progif = REG(PCIR_PROGIF, 1); 353 cfg->revid = REG(PCIR_REVID, 1); 354 cfg->hdrtype = REG(PCIR_HEADERTYPE, 1); 355 cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1); 356 cfg->lattimer = REG(PCIR_LATTIMER, 1); 357 cfg->intpin = REG(PCIR_INTPIN, 1); 358 cfg->intline = REG(PCIR_INTLINE, 1); 359 360 cfg->mingnt = REG(PCIR_MINGNT, 1); 361 cfg->maxlat = REG(PCIR_MAXLAT, 1); 362 363 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0; 364 cfg->hdrtype &= ~PCIM_MFDEV; 365 366 pci_fixancient(cfg); 367 pci_hdrtypedata(pcib, b, s, f, cfg); 368 369 if (REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT) 370 pci_read_extcap(pcib, cfg); 371 372 STAILQ_INSERT_TAIL(devlist_head, devlist_entry, pci_links); 373 374 devlist_entry->conf.pc_sel.pc_bus = cfg->bus; 375 devlist_entry->conf.pc_sel.pc_dev = cfg->slot; 376 devlist_entry->conf.pc_sel.pc_func = cfg->func; 377 devlist_entry->conf.pc_hdr = cfg->hdrtype; 378 379 devlist_entry->conf.pc_subvendor = cfg->subvendor; 380 devlist_entry->conf.pc_subdevice = cfg->subdevice; 381 devlist_entry->conf.pc_vendor = cfg->vendor; 382 devlist_entry->conf.pc_device = cfg->device; 383 384 devlist_entry->conf.pc_class = cfg->baseclass; 385 devlist_entry->conf.pc_subclass = cfg->subclass; 386 devlist_entry->conf.pc_progif = cfg->progif; 387 devlist_entry->conf.pc_revid = cfg->revid; 388 389 pci_numdevs++; 390 pci_generation++; 391 } 392 return (devlist_entry); 393#undef REG 394} 395 396static void 397pci_read_extcap(device_t pcib, pcicfgregs *cfg) 398{ 399#define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w) 400 int ptr, nextptr, ptrptr; 401 402 switch (cfg->hdrtype) { 403 case 0: 404 ptrptr = 0x34; 405 break; 406 case 2: 407 ptrptr = 0x14; 408 break; 409 default: 410 return; /* no extended capabilities support */ 411 } 412 nextptr = REG(ptrptr, 1); /* sanity check? */ 413 414 /* 415 * Read capability entries. 416 */ 417 while (nextptr != 0) { 418 /* Sanity check */ 419 if (nextptr > 255) { 420 printf("illegal PCI extended capability offset %d\n", 421 nextptr); 422 return; 423 } 424 /* Find the next entry */ 425 ptr = nextptr; 426 nextptr = REG(ptr + 1, 1); 427 428 /* Process this entry */ 429 switch (REG(ptr, 1)) { 430 case 0x01: /* PCI power management */ 431 if (cfg->pp_cap == 0) { 432 cfg->pp_cap = REG(ptr + PCIR_POWER_CAP, 2); 433 cfg->pp_status = ptr + PCIR_POWER_STATUS; 434 cfg->pp_pmcsr = ptr + PCIR_POWER_PMCSR; 435 if ((nextptr - ptr) > PCIR_POWER_DATA) 436 cfg->pp_data = ptr + PCIR_POWER_DATA; 437 } 438 break; 439 default: 440 break; 441 } 442 } 443#undef REG 444} 445 446/* free pcicfgregs structure and all depending data structures */ 447 448int 449pci_freecfg(struct pci_devinfo *dinfo) 450{ 451 struct devlist *devlist_head; 452 453 devlist_head = &pci_devq; 454 455 /* XXX this hasn't been tested */ 456 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links); 457 free(dinfo, M_DEVBUF); 458 459 /* increment the generation count */ 460 pci_generation++; 461 462 /* we're losing one device */ 463 pci_numdevs--; 464 return (0); 465} 466 467/* 468 * PCI power manangement 469 */ 470int 471pci_set_powerstate_method(device_t dev, device_t child, int state) 472{ 473 struct pci_devinfo *dinfo = device_get_ivars(child); 474 pcicfgregs *cfg = &dinfo->cfg; 475 u_int16_t status; 476 int result; 477 478 if (cfg->pp_cap != 0) { 479 status = PCI_READ_CONFIG(dev, child, cfg->pp_status, 2) & ~PCIM_PSTAT_DMASK; 480 result = 0; 481 switch (state) { 482 case PCI_POWERSTATE_D0: 483 status |= PCIM_PSTAT_D0; 484 break; 485 case PCI_POWERSTATE_D1: 486 if (cfg->pp_cap & PCIM_PCAP_D1SUPP) { 487 status |= PCIM_PSTAT_D1; 488 } else { 489 result = EOPNOTSUPP; 490 } 491 break; 492 case PCI_POWERSTATE_D2: 493 if (cfg->pp_cap & PCIM_PCAP_D2SUPP) { 494 status |= PCIM_PSTAT_D2; 495 } else { 496 result = EOPNOTSUPP; 497 } 498 break; 499 case PCI_POWERSTATE_D3: 500 status |= PCIM_PSTAT_D3; 501 break; 502 default: 503 result = EINVAL; 504 } 505 if (result == 0) 506 PCI_WRITE_CONFIG(dev, child, cfg->pp_status, status, 2); 507 } else { 508 result = ENXIO; 509 } 510 return(result); 511} 512 513int 514pci_get_powerstate_method(device_t dev, device_t child) 515{ 516 struct pci_devinfo *dinfo = device_get_ivars(child); 517 pcicfgregs *cfg = &dinfo->cfg; 518 u_int16_t status; 519 int result; 520 521 if (cfg->pp_cap != 0) { 522 status = PCI_READ_CONFIG(dev, child, cfg->pp_status, 2); 523 switch (status & PCIM_PSTAT_DMASK) { 524 case PCIM_PSTAT_D0: 525 result = PCI_POWERSTATE_D0; 526 break; 527 case PCIM_PSTAT_D1: 528 result = PCI_POWERSTATE_D1; 529 break; 530 case PCIM_PSTAT_D2: 531 result = PCI_POWERSTATE_D2; 532 break; 533 case PCIM_PSTAT_D3: 534 result = PCI_POWERSTATE_D3; 535 break; 536 default: 537 result = PCI_POWERSTATE_UNKNOWN; 538 break; 539 } 540 } else { 541 /* No support, device is always at D0 */ 542 result = PCI_POWERSTATE_D0; 543 } 544 return(result); 545} 546 547/* 548 * Some convenience functions for PCI device drivers. 549 */ 550 551static __inline void 552pci_set_command_bit(device_t dev, device_t child, u_int16_t bit) 553{ 554 u_int16_t command; 555 556 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 557 command |= bit; 558 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 559} 560 561static __inline void 562pci_clear_command_bit(device_t dev, device_t child, u_int16_t bit) 563{ 564 u_int16_t command; 565 566 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 567 command &= ~bit; 568 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 569} 570 571void 572pci_enable_busmaster_method(device_t dev, device_t child) 573{ 574 pci_set_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 575} 576 577void 578pci_disable_busmaster_method(device_t dev, device_t child) 579{ 580 pci_clear_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 581} 582 583void 584pci_enable_io_method(device_t dev, device_t child, int space) 585{ 586 switch(space) { 587 case SYS_RES_IOPORT: 588 pci_set_command_bit(dev, child, PCIM_CMD_PORTEN); 589 break; 590 case SYS_RES_MEMORY: 591 pci_set_command_bit(dev, child, PCIM_CMD_MEMEN); 592 break; 593 } 594} 595 596void 597pci_disable_io_method(device_t dev, device_t child, int space) 598{ 599 switch(space) { 600 case SYS_RES_IOPORT: 601 pci_clear_command_bit(dev, child, PCIM_CMD_PORTEN); 602 break; 603 case SYS_RES_MEMORY: 604 pci_clear_command_bit(dev, child, PCIM_CMD_MEMEN); 605 break; 606 } 607} 608 609/* 610 * New style pci driver. Parent device is either a pci-host-bridge or a 611 * pci-pci-bridge. Both kinds are represented by instances of pcib. 612 */ 613 614void 615pci_print_verbose(struct pci_devinfo *dinfo) 616{ 617 if (bootverbose) { 618 pcicfgregs *cfg = &dinfo->cfg; 619 620 printf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n", 621 cfg->vendor, cfg->device, cfg->revid); 622 printf("\tbus=%d, slot=%d, func=%d\n", 623 cfg->bus, cfg->slot, cfg->func); 624 printf("\tclass=%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n", 625 cfg->baseclass, cfg->subclass, cfg->progif, cfg->hdrtype, 626 cfg->mfdev); 627#ifdef PCI_DEBUG 628 printf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n", 629 cfg->cmdreg, cfg->statreg, cfg->cachelnsz); 630 printf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n", 631 cfg->lattimer, cfg->lattimer * 30, cfg->mingnt, 632 cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250); 633#endif /* PCI_DEBUG */ 634 if (cfg->intpin > 0) 635 printf("\tintpin=%c, irq=%d\n", 636 cfg->intpin +'a' -1, cfg->intline); 637 if (cfg->pp_cap) { 638 u_int16_t status; 639 640 status = pci_read_config(cfg->dev, cfg->pp_status, 2); 641 printf("\tpowerspec %d supports D0%s%s D3 current D%d\n", 642 cfg->pp_cap & PCIM_PCAP_SPEC, 643 cfg->pp_cap & PCIM_PCAP_D1SUPP ? " D1" : "", 644 cfg->pp_cap & PCIM_PCAP_D2SUPP ? " D2" : "", 645 status & PCIM_PSTAT_DMASK); 646 } 647 } 648} 649 650static int 651pci_porten(device_t pcib, int b, int s, int f) 652{ 653 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2) 654 & PCIM_CMD_PORTEN) != 0; 655} 656 657static int 658pci_memen(device_t pcib, int b, int s, int f) 659{ 660 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2) 661 & PCIM_CMD_MEMEN) != 0; 662} 663 664/* 665 * Add a resource based on a pci map register. Return 1 if the map 666 * register is a 32bit map register or 2 if it is a 64bit register. 667 */ 668static int 669pci_add_map(device_t pcib, int b, int s, int f, int reg, 670 struct resource_list *rl) 671{ 672 u_int32_t map; 673 u_int64_t base; 674 u_int8_t ln2size; 675 u_int8_t ln2range; 676 u_int32_t testval; 677 u_int16_t cmd; 678 int type; 679 680 map = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4); 681 682 if (map == 0 || map == 0xffffffff) 683 return (1); /* skip invalid entry */ 684 685 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, 0xffffffff, 4); 686 testval = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4); 687 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, map, 4); 688 689 base = pci_mapbase(map); 690 if (pci_maptype(map) & PCI_MAPMEM) 691 type = SYS_RES_MEMORY; 692 else 693 type = SYS_RES_IOPORT; 694 ln2size = pci_mapsize(testval); 695 ln2range = pci_maprange(testval); 696 if (ln2range == 64) { 697 /* Read the other half of a 64bit map register */ 698 base |= (u_int64_t) PCIB_READ_CONFIG(pcib, b, s, f, reg + 4, 4) << 32; 699 } 700 701 if (bootverbose) { 702 printf("\tmap[%02x]: type %x, range %2d, base %08x, size %2d", 703 reg, pci_maptype(map), ln2range, 704 (unsigned int) base, ln2size); 705 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) 706 printf(", port disabled\n"); 707 else if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) 708 printf(", memory disabled\n"); 709 else 710 printf(", enabled\n"); 711 } 712 713 /* 714 * This code theoretically does the right thing, but has 715 * undesirable side effects in some cases where 716 * peripherals respond oddly to having these bits 717 * enabled. Leave them alone by default. 718 */ 719 if (pci_enable_io_modes) { 720 /* Turn on resources that have been left off by a lazy BIOS */ 721 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) { 722 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2); 723 cmd |= PCIM_CMD_PORTEN; 724 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2); 725 } 726 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) { 727 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2); 728 cmd |= PCIM_CMD_MEMEN; 729 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2); 730 } 731 } else { 732 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) 733 return (1); 734 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) 735 return (1); 736 } 737 resource_list_add(rl, type, reg, base, base + (1 << ln2size) - 1, 738 (1 << ln2size)); 739 740 return ((ln2range == 64) ? 2 : 1); 741} 742 743static void 744pci_add_resources(device_t pcib, int b, int s, int f, device_t dev) 745{ 746 struct pci_devinfo *dinfo = device_get_ivars(dev); 747 pcicfgregs *cfg = &dinfo->cfg; 748 struct resource_list *rl = &dinfo->resources; 749 struct pci_quirk *q; 750 int i; 751 752 for (i = 0; i < cfg->nummaps;) { 753 i += pci_add_map(pcib, b, s, f, PCIR_MAPS + i*4, rl); 754 } 755 756 for (q = &pci_quirks[0]; q->devid; q++) { 757 if (q->devid == ((cfg->device << 16) | cfg->vendor) 758 && q->type == PCI_QUIRK_MAP_REG) 759 pci_add_map(pcib, b, s, f, q->arg1, rl); 760 } 761 762 if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline)) { 763#ifdef __ia64__ 764 /* 765 * Re-route interrupts on ia64 so that we can get the 766 * I/O SAPIC interrupt numbers (the BIOS leaves legacy 767 * PIC interrupt numbers in the intline registers). 768 */ 769 cfg->intline = PCIB_ROUTE_INTERRUPT(pcib, dev, cfg->intpin); 770#endif 771 resource_list_add(rl, SYS_RES_IRQ, 0, cfg->intline, 772 cfg->intline, 1); 773 } 774} 775 776static void 777pci_add_children(device_t dev, int busno) 778{ 779 device_t pcib = device_get_parent(dev); 780 int maxslots; 781 int s, f; 782 783 maxslots = PCIB_MAXSLOTS(pcib); 784 785 for (s = 0; s <= maxslots; s++) { 786 int pcifunchigh = 0; 787 for (f = 0; f <= pcifunchigh; f++) { 788 struct pci_devinfo *dinfo = pci_read_device(pcib, 789 busno, s, f, sizeof(struct pci_devinfo)); 790 if (dinfo != NULL) { 791 if (dinfo->cfg.mfdev) 792 pcifunchigh = PCI_FUNCMAX; 793 794 dinfo->cfg.dev = device_add_child(dev, NULL, -1); 795 device_set_ivars(dinfo->cfg.dev, dinfo); 796 pci_add_resources(pcib, busno, s, f, 797 dinfo->cfg.dev); 798 pci_print_verbose(dinfo); 799 } 800 } 801 } 802} 803 804static int 805pci_probe(device_t dev) 806{ 807 static int once, busno; 808 caddr_t vendordata, info; 809 810 device_set_desc(dev, "PCI bus"); 811 812 if (bootverbose) 813 device_printf(dev, "physical bus=%d\n", pcib_get_bus(dev)); 814 815 /* 816 * Since there can be multiple independantly numbered PCI 817 * busses on some large alpha systems, we can't use the unit 818 * number to decide what bus we are probing. We ask the parent 819 * pcib what our bus number is. 820 */ 821 busno = pcib_get_bus(dev); 822 if (busno < 0) 823 return (ENXIO); 824 pci_add_children(dev, busno); 825 826 if (!once) { 827 make_dev(&pcicdev, 0, UID_ROOT, GID_WHEEL, 0644, "pci"); 828 if ((vendordata = preload_search_by_type("pci_vendor_data")) 829 != NULL) { 830 info = preload_search_info(vendordata, MODINFO_ADDR); 831 pci_vendordata = *(char **)info; 832 info = preload_search_info(vendordata, MODINFO_SIZE); 833 pci_vendordata_size = *(size_t *)info; 834 /* terminate the database */ 835 pci_vendordata[pci_vendordata_size] = '\n'; 836 } 837 once++; 838 } 839 840 return (0); 841} 842 843int 844pci_print_child(device_t dev, device_t child) 845{ 846 struct pci_devinfo *dinfo; 847 struct resource_list *rl; 848 pcicfgregs *cfg; 849 int retval = 0; 850 851 dinfo = device_get_ivars(child); 852 cfg = &dinfo->cfg; 853 rl = &dinfo->resources; 854 855 retval += bus_print_child_header(dev, child); 856 857 retval += resource_list_print_type(rl, "port", SYS_RES_IOPORT, "%#lx"); 858 retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#lx"); 859 retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%ld"); 860 if (device_get_flags(dev)) 861 retval += printf(" flags %#x", device_get_flags(dev)); 862 863 retval += printf(" at device %d.%d", pci_get_slot(child), 864 pci_get_function(child)); 865 866 retval += bus_print_child_footer(dev, child); 867 868 return (retval); 869} 870 871static struct 872{ 873 int class; 874 int subclass; 875 char *desc; 876} pci_nomatch_tab[] = { 877 {PCIC_OLD, -1, "old"}, 878 {PCIC_OLD, PCIS_OLD_NONVGA, "non-VGA display device"}, 879 {PCIC_OLD, PCIS_OLD_VGA, "VGA-compatible display device"}, 880 {PCIC_STORAGE, -1, "mass storage"}, 881 {PCIC_STORAGE, PCIS_STORAGE_SCSI, "SCSI"}, 882 {PCIC_STORAGE, PCIS_STORAGE_IDE, "ATA"}, 883 {PCIC_STORAGE, PCIS_STORAGE_FLOPPY, "floppy disk"}, 884 {PCIC_STORAGE, PCIS_STORAGE_IPI, "IPI"}, 885 {PCIC_STORAGE, PCIS_STORAGE_RAID, "RAID"}, 886 {PCIC_NETWORK, -1, "network"}, 887 {PCIC_NETWORK, PCIS_NETWORK_ETHERNET, "ethernet"}, 888 {PCIC_NETWORK, PCIS_NETWORK_TOKENRING, "token ring"}, 889 {PCIC_NETWORK, PCIS_NETWORK_FDDI, "fddi"}, 890 {PCIC_NETWORK, PCIS_NETWORK_ATM, "ATM"}, 891 {PCIC_DISPLAY, -1, "display"}, 892 {PCIC_DISPLAY, PCIS_DISPLAY_VGA, "VGA"}, 893 {PCIC_DISPLAY, PCIS_DISPLAY_XGA, "XGA"}, 894 {PCIC_MULTIMEDIA, -1, "multimedia"}, 895 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_VIDEO, "video"}, 896 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_AUDIO, "audio"}, 897 {PCIC_MEMORY, -1, "memory"}, 898 {PCIC_MEMORY, PCIS_MEMORY_RAM, "RAM"}, 899 {PCIC_MEMORY, PCIS_MEMORY_FLASH, "flash"}, 900 {PCIC_BRIDGE, -1, "bridge"}, 901 {PCIC_BRIDGE, PCIS_BRIDGE_HOST, "HOST-PCI"}, 902 {PCIC_BRIDGE, PCIS_BRIDGE_ISA, "PCI-ISA"}, 903 {PCIC_BRIDGE, PCIS_BRIDGE_EISA, "PCI-EISA"}, 904 {PCIC_BRIDGE, PCIS_BRIDGE_MCA, "PCI-MCA"}, 905 {PCIC_BRIDGE, PCIS_BRIDGE_PCI, "PCI-PCI"}, 906 {PCIC_BRIDGE, PCIS_BRIDGE_PCMCIA, "PCI-PCMCIA"}, 907 {PCIC_BRIDGE, PCIS_BRIDGE_NUBUS, "PCI-NuBus"}, 908 {PCIC_BRIDGE, PCIS_BRIDGE_CARDBUS, "PCI-CardBus"}, 909 {PCIC_BRIDGE, PCIS_BRIDGE_OTHER, "PCI-unknown"}, 910 {PCIC_SIMPLECOMM, -1, "simple comms"}, 911 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_UART, "UART"}, /* could detect 16550 */ 912 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_PAR, "parallel port"}, 913 {PCIC_BASEPERIPH, -1, "base peripheral"}, 914 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PIC, "interrupt controller"}, 915 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_DMA, "DMA controller"}, 916 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_TIMER, "timer"}, 917 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_RTC, "realtime clock"}, 918 {PCIC_INPUTDEV, -1, "input device"}, 919 {PCIC_INPUTDEV, PCIS_INPUTDEV_KEYBOARD, "keyboard"}, 920 {PCIC_INPUTDEV, PCIS_INPUTDEV_DIGITIZER,"digitizer"}, 921 {PCIC_INPUTDEV, PCIS_INPUTDEV_MOUSE, "mouse"}, 922 {PCIC_DOCKING, -1, "docking station"}, 923 {PCIC_PROCESSOR, -1, "processor"}, 924 {PCIC_SERIALBUS, -1, "serial bus"}, 925 {PCIC_SERIALBUS, PCIS_SERIALBUS_FW, "FireWire"}, 926 {PCIC_SERIALBUS, PCIS_SERIALBUS_ACCESS, "AccessBus"}, 927 {PCIC_SERIALBUS, PCIS_SERIALBUS_SSA, "SSA"}, 928 {PCIC_SERIALBUS, PCIS_SERIALBUS_USB, "USB"}, 929 {PCIC_SERIALBUS, PCIS_SERIALBUS_FC, "Fibre Channel"}, 930 {PCIC_SERIALBUS, PCIS_SERIALBUS_SMBUS, "SMBus"}, 931 {0, 0, NULL} 932}; 933 934void 935pci_probe_nomatch(device_t dev, device_t child) 936{ 937 int i; 938 char *cp, *scp, *device; 939 940 /* 941 * Look for a listing for this device in a loaded device database. 942 */ 943 if ((device = pci_describe_device(child)) != NULL) { 944 device_printf(dev, "<%s>", device); 945 free(device, M_DEVBUF); 946 } else { 947 /* 948 * Scan the class/subclass descriptions for a general 949 * description. 950 */ 951 cp = "unknown"; 952 scp = NULL; 953 for (i = 0; pci_nomatch_tab[i].desc != NULL; i++) { 954 if (pci_nomatch_tab[i].class == pci_get_class(child)) { 955 if (pci_nomatch_tab[i].subclass == -1) { 956 cp = pci_nomatch_tab[i].desc; 957 } else if (pci_nomatch_tab[i].subclass == 958 pci_get_subclass(child)) { 959 scp = pci_nomatch_tab[i].desc; 960 } 961 } 962 } 963 device_printf(dev, "<%s%s%s>", 964 cp ? : "", ((cp != NULL) && (scp != NULL)) ? ", " : "", 965 scp ? : ""); 966 } 967 printf(" at device %d.%d (no driver attached)\n", 968 pci_get_slot(child), pci_get_function(child)); 969 return; 970} 971 972/* 973 * Parse the PCI device database, if loaded, and return a pointer to a 974 * description of the device. 975 * 976 * The database is flat text formatted as follows: 977 * 978 * Any line not in a valid format is ignored. 979 * Lines are terminated with newline '\n' characters. 980 * 981 * A VENDOR line consists of the 4 digit (hex) vendor code, a TAB, then 982 * the vendor name. 983 * 984 * A DEVICE line is entered immediately below the corresponding VENDOR ID. 985 * - devices cannot be listed without a corresponding VENDOR line. 986 * A DEVICE line consists of a TAB, the 4 digit (hex) device code, 987 * another TAB, then the device name. 988 */ 989 990/* 991 * Assuming (ptr) points to the beginning of a line in the database, 992 * return the vendor or device and description of the next entry. 993 * The value of (vendor) or (device) inappropriate for the entry type 994 * is set to -1. Returns nonzero at the end of the database. 995 * 996 * Note that this is slightly unrobust in the face of corrupt data; 997 * we attempt to safeguard against this by spamming the end of the 998 * database with a newline when we initialise. 999 */ 1000static int 1001pci_describe_parse_line(char **ptr, int *vendor, int *device, char **desc) 1002{ 1003 char *cp = *ptr; 1004 int left; 1005 1006 *device = -1; 1007 *vendor = -1; 1008 **desc = '\0'; 1009 for (;;) { 1010 left = pci_vendordata_size - (cp - pci_vendordata); 1011 if (left <= 0) { 1012 *ptr = cp; 1013 return(1); 1014 } 1015 1016 /* vendor entry? */ 1017 if (*cp != '\t' && 1018 sscanf(cp, "%x\t%80[^\n]", vendor, *desc) == 2) 1019 break; 1020 /* device entry? */ 1021 if (*cp == '\t' && 1022 sscanf(cp, "%x\t%80[^\n]", device, *desc) == 2) 1023 break; 1024 1025 /* skip to next line */ 1026 while (*cp != '\n' && left > 0) { 1027 cp++; 1028 left--; 1029 } 1030 if (*cp == '\n') { 1031 cp++; 1032 left--; 1033 } 1034 } 1035 /* skip to next line */ 1036 while (*cp != '\n' && left > 0) { 1037 cp++; 1038 left--; 1039 } 1040 if (*cp == '\n' && left > 0) 1041 cp++; 1042 *ptr = cp; 1043 return(0); 1044} 1045 1046static char * 1047pci_describe_device(device_t dev) 1048{ 1049 int vendor, device; 1050 char *desc, *vp, *dp, *line; 1051 1052 desc = vp = dp = NULL; 1053 1054 /* 1055 * If we have no vendor data, we can't do anything. 1056 */ 1057 if (pci_vendordata == NULL) 1058 goto out; 1059 1060 /* 1061 * Scan the vendor data looking for this device 1062 */ 1063 line = pci_vendordata; 1064 if ((vp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL) 1065 goto out; 1066 for (;;) { 1067 if (pci_describe_parse_line(&line, &vendor, &device, &vp)) 1068 goto out; 1069 if (vendor == pci_get_vendor(dev)) 1070 break; 1071 } 1072 if ((dp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL) 1073 goto out; 1074 for (;;) { 1075 if (pci_describe_parse_line(&line, &vendor, &device, &dp)) { 1076 *dp = 0; 1077 break; 1078 } 1079 if (vendor != -1) { 1080 *dp = 0; 1081 break; 1082 } 1083 if (device == pci_get_device(dev)) 1084 break; 1085 } 1086 if (dp[0] == '\0') 1087 snprintf(dp, 80, "0x%x", pci_get_device(dev)); 1088 if ((desc = malloc(strlen(vp) + strlen(dp) + 3, M_DEVBUF, M_NOWAIT)) != 1089 NULL) 1090 sprintf(desc, "%s, %s", vp, dp); 1091 out: 1092 if (vp != NULL) 1093 free(vp, M_DEVBUF); 1094 if (dp != NULL) 1095 free(dp, M_DEVBUF); 1096 return(desc); 1097} 1098 1099int 1100pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 1101{ 1102 struct pci_devinfo *dinfo; 1103 pcicfgregs *cfg; 1104 1105 dinfo = device_get_ivars(child); 1106 cfg = &dinfo->cfg; 1107 1108 switch (which) { 1109 case PCI_IVAR_SUBVENDOR: 1110 *result = cfg->subvendor; 1111 break; 1112 case PCI_IVAR_SUBDEVICE: 1113 *result = cfg->subdevice; 1114 break; 1115 case PCI_IVAR_VENDOR: 1116 *result = cfg->vendor; 1117 break; 1118 case PCI_IVAR_DEVICE: 1119 *result = cfg->device; 1120 break; 1121 case PCI_IVAR_DEVID: 1122 *result = (cfg->device << 16) | cfg->vendor; 1123 break; 1124 case PCI_IVAR_CLASS: 1125 *result = cfg->baseclass; 1126 break; 1127 case PCI_IVAR_SUBCLASS: 1128 *result = cfg->subclass; 1129 break; 1130 case PCI_IVAR_PROGIF: 1131 *result = cfg->progif; 1132 break; 1133 case PCI_IVAR_REVID: 1134 *result = cfg->revid; 1135 break; 1136 case PCI_IVAR_INTPIN: 1137 *result = cfg->intpin; 1138 break; 1139 case PCI_IVAR_IRQ: 1140 *result = cfg->intline; 1141 break; 1142 case PCI_IVAR_BUS: 1143 *result = cfg->bus; 1144 break; 1145 case PCI_IVAR_SLOT: 1146 *result = cfg->slot; 1147 break; 1148 case PCI_IVAR_FUNCTION: 1149 *result = cfg->func; 1150 break; 1151 default: 1152 return (ENOENT); 1153 } 1154 return (0); 1155} 1156 1157int 1158pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value) 1159{ 1160 struct pci_devinfo *dinfo; 1161 pcicfgregs *cfg; 1162 1163 dinfo = device_get_ivars(child); 1164 cfg = &dinfo->cfg; 1165 1166 switch (which) { 1167 case PCI_IVAR_SUBVENDOR: 1168 case PCI_IVAR_SUBDEVICE: 1169 case PCI_IVAR_VENDOR: 1170 case PCI_IVAR_DEVICE: 1171 case PCI_IVAR_DEVID: 1172 case PCI_IVAR_CLASS: 1173 case PCI_IVAR_SUBCLASS: 1174 case PCI_IVAR_PROGIF: 1175 case PCI_IVAR_REVID: 1176 case PCI_IVAR_INTPIN: 1177 case PCI_IVAR_IRQ: 1178 case PCI_IVAR_BUS: 1179 case PCI_IVAR_SLOT: 1180 case PCI_IVAR_FUNCTION: 1181 return (EINVAL); /* disallow for now */ 1182 1183 default: 1184 return (ENOENT); 1185 } 1186 return (0); 1187} 1188 1189struct resource * 1190pci_alloc_resource(device_t dev, device_t child, int type, int *rid, 1191 u_long start, u_long end, u_long count, u_int flags) 1192{ 1193 struct pci_devinfo *dinfo = device_get_ivars(child); 1194 struct resource_list *rl = &dinfo->resources; 1195 pcicfgregs *cfg = &dinfo->cfg; 1196 1197 /* 1198 * Perform lazy resource allocation 1199 * 1200 * XXX add support here for SYS_RES_IOPORT and SYS_RES_MEMORY 1201 */ 1202 if (device_get_parent(child) == dev) { 1203 /* 1204 * If device doesn't have an interrupt routed, and is 1205 * deserving of an interrupt, try to assign it one. 1206 */ 1207 if ((type == SYS_RES_IRQ) && 1208 !PCI_INTERRUPT_VALID(cfg->intline) && 1209 (cfg->intpin != 0)) { 1210 cfg->intline = PCIB_ROUTE_INTERRUPT( 1211 device_get_parent(dev), child, cfg->intpin); 1212 if (PCI_INTERRUPT_VALID(cfg->intline)) { 1213 pci_write_config(child, PCIR_INTLINE, 1214 cfg->intline, 1); 1215 resource_list_add(rl, SYS_RES_IRQ, 0, 1216 cfg->intline, cfg->intline, 1); 1217 } 1218 } 1219 } 1220 1221 return (resource_list_alloc(rl, dev, child, type, rid, 1222 start, end, count, flags)); 1223} 1224 1225void 1226pci_delete_resource(device_t dev, device_t child, int type, int rid) 1227{ 1228 struct pci_devinfo *dinfo; 1229 struct resource_list *rl; 1230 struct resource_list_entry *rle; 1231 1232 if (device_get_parent(child) != dev) 1233 return; 1234 1235 dinfo = device_get_ivars(child); 1236 rl = &dinfo->resources; 1237 rle = resource_list_find(rl, type, rid); 1238 if (rle) { 1239 if (rle->res) { 1240 if (rle->res->r_dev != dev || 1241 rman_get_flags(rle->res) & RF_ACTIVE) { 1242 device_printf(dev, "delete_resource: " 1243 "Resource still owned by child, oops. " 1244 "(type=%d, rid=%d, addr=%lx)\n", 1245 rle->type, rle->rid, 1246 rman_get_start(rle->res)); 1247 return; 1248 } 1249 bus_release_resource(dev, type, rid, rle->res); 1250 } 1251 resource_list_delete(rl, type, rid); 1252 } 1253 /* 1254 * Why do we turn off the PCI configuration BAR when we delete a 1255 * resource? -- imp 1256 */ 1257 pci_write_config(child, rid, 0, 4); 1258 BUS_DELETE_RESOURCE(device_get_parent(dev), child, type, rid); 1259} 1260 1261struct resource_list * 1262pci_get_resource_list (device_t dev, device_t child) 1263{ 1264 struct pci_devinfo * dinfo = device_get_ivars(child); 1265 struct resource_list * rl = &dinfo->resources; 1266 1267 if (!rl) 1268 return (NULL); 1269 1270 return (rl); 1271} 1272 1273u_int32_t 1274pci_read_config_method(device_t dev, device_t child, int reg, int width) 1275{ 1276 struct pci_devinfo *dinfo = device_get_ivars(child); 1277 pcicfgregs *cfg = &dinfo->cfg; 1278 1279 return (PCIB_READ_CONFIG(device_get_parent(dev), 1280 cfg->bus, cfg->slot, cfg->func, reg, width)); 1281} 1282 1283void 1284pci_write_config_method(device_t dev, device_t child, int reg, 1285 u_int32_t val, int width) 1286{ 1287 struct pci_devinfo *dinfo = device_get_ivars(child); 1288 pcicfgregs *cfg = &dinfo->cfg; 1289 1290 PCIB_WRITE_CONFIG(device_get_parent(dev), 1291 cfg->bus, cfg->slot, cfg->func, reg, val, width); 1292} 1293 1294static int 1295pci_modevent(module_t mod, int what, void *arg) 1296{ 1297 switch (what) { 1298 case MOD_LOAD: 1299 STAILQ_INIT(&pci_devq); 1300 pci_generation = 0; 1301 break; 1302 1303 case MOD_UNLOAD: 1304 break; 1305 } 1306 1307 return (0); 1308} 1309