pci.c revision 21965
1/************************************************************************** 2** 3** $FreeBSD: head/sys/dev/pci/pci.c 21965 1997-01-23 22:58:03Z se $ 4** 5** General subroutines for the PCI bus. 6** pci_configure () 7** 8** FreeBSD 9** 10**------------------------------------------------------------------------- 11** 12** Copyright (c) 1994 Wolfgang Stanglmeier. All rights reserved. 13** 14** Redistribution and use in source and binary forms, with or without 15** modification, are permitted provided that the following conditions 16** are met: 17** 1. Redistributions of source code must retain the above copyright 18** notice, this list of conditions and the following disclaimer. 19** 2. Redistributions in binary form must reproduce the above copyright 20** notice, this list of conditions and the following disclaimer in the 21** documentation and/or other materials provided with the distribution. 22** 3. The name of the author may not be used to endorse or promote products 23** derived from this software without specific prior written permission. 24** 25** THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 26** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 27** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 28** IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 29** INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 30** NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 31** DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 32** THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 34** THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35** 36*************************************************************************** 37*/ 38 39#include "pci.h" 40#if NPCI > 0 41 42/*======================================================== 43** 44** #includes and declarations 45** 46**======================================================== 47*/ 48 49#include <sys/param.h> 50#include <sys/systm.h> 51#include <sys/malloc.h> 52#include <sys/errno.h> 53#include <sys/kernel.h> 54#include <sys/proc.h> /* declaration of wakeup(), used by vm.h */ 55#include <sys/conf.h> 56#ifdef DEVFS 57#include <sys/devfsext.h> 58#endif /* DEVFS */ 59#include <sys/fcntl.h> 60 61#include <vm/vm.h> 62#include <vm/vm_param.h> 63#include <vm/pmap.h> 64 65 66#include <i386/isa/isa_device.h> /* XXX inthand2_t */ 67 68#include <pci/pcivar.h> 69#include <pci/pcireg.h> 70#include <pci/pcibus.h> 71#include <pci/pci_ioctl.h> 72 73#define PCI_MAX_IRQ (16) 74 75 76/*======================================================== 77** 78** Structs and Functions 79** 80**======================================================== 81*/ 82 83struct pcicb { 84 struct pcicb *pcicb_next; 85 struct pcicb *pcicb_up; 86 struct pcicb *pcicb_down; 87 pcici_t pcicb_bridge; 88 89 u_char pcicb_bus; 90 u_char pcicb_subordinate; 91 u_int pcicb_mfrom; 92 u_int pcicb_mupto; 93 u_int pcicb_mamount; 94 u_short pcicb_pfrom; 95 u_short pcicb_pupto; 96 u_short pcicb_pamount; 97 u_char pcicb_bfrom; 98 u_char pcicb_bupto; 99 100 u_long pcicb_iobase; 101 u_long pcicb_iolimit; 102 u_long pcicb_membase; 103 u_long pcicb_memlimit; 104 u_long pcicb_p_membase; 105 u_long pcicb_p_memlimit; 106}; 107 108struct pci_lkm { 109 struct pci_device *dvp; 110 struct pci_lkm *next; 111}; 112 113static void 114not_supported (pcici_t tag, u_long type); 115 116static void 117pci_bus_config (void); 118 119static void 120pci_rescan (void); 121 122static void pci_attach (int bus, int dev, int func, 123 struct pci_device *dvp, const char *name); 124 125static int 126pci_bridge_config (void); 127 128static int 129pci_mfdev (int bus, int device); 130 131static void pci_remember (int bus, int dev, int func, struct pci_device *dvp); 132 133/*======================================================== 134** 135** Variables 136** 137**======================================================== 138*/ 139 140/* 141** log2 of safe burst len (in words) 142*/ 143 144unsigned pci_max_burst_len = 3; /* 2=16Byte, 3=32Byte, 4=64Byte, ... */ 145unsigned pci_mechanism = 0; 146unsigned pci_maxdevice = 0; 147unsigned pciroots = 0; /* XXX pcisupport.c increments this 148 * for the Orion host to PCI bridge 149 * UGLY hack ... :( Will be changed :) 150 */ 151/*-------------------------------------------------------- 152** 153** Local variables. 154** 155**-------------------------------------------------------- 156*/ 157 158static struct pcibus *pcibus; 159 160static int pci_conf_count; 161static int pci_info_done; 162static int pcibusmax; 163static struct pcicb *pcicb; 164 165static struct pci_conf *pci_dev_list; 166static unsigned pci_dev_list_count; 167static unsigned pci_dev_list_size; 168 169static struct pci_lkm *pci_lkm_head; 170 171/*----------------------------------------------------------------- 172** 173** The following functions are provided for the device driver 174** to read/write the configuration space. 175** 176** pci_conf_read(): 177** Read a long word from the pci configuration space. 178** Requires a tag (from pcitag) and the register 179** number (should be a long word alligned one). 180** 181** pci_conf_write(): 182** Writes a long word to the pci configuration space. 183** Requires a tag (from pcitag), the register number 184** (should be a long word alligned one), and a value. 185** 186**----------------------------------------------------------------- 187*/ 188 189u_long 190pci_conf_read (pcici_t tag, u_long reg) 191{ 192 return (pcibus->pb_read (tag, reg)); 193} 194 195void 196pci_conf_write (pcici_t tag, u_long reg, u_long data) 197{ 198 pcibus->pb_write (tag, reg, data); 199} 200 201/*======================================================== 202** 203** Subroutines for configuration. 204** 205**======================================================== 206*/ 207 208static void 209pci_register_io (struct pcicb * cb, u_int base, u_int limit) 210{ 211#ifdef PCI_BRIDGE_DEBUG 212 if (bootverbose) 213 printf ("register_io: bus=%d base=%x limit=%x\n", 214 cb->pcicb_bus, base, limit); 215#endif 216 217 if (!cb->pcicb_pfrom || base < cb->pcicb_pfrom) 218 cb->pcicb_pfrom = base; 219 if (limit > cb->pcicb_pupto) 220 cb->pcicb_pupto = limit; 221 222 /* 223 ** XXX should set bridge io mapping here 224 ** but it can be mapped in 4k blocks only, 225 ** leading to conflicts with isa/eisa .. 226 */ 227} 228 229static void 230pci_register_memory (struct pcicb * cb, u_int base, u_int limit) 231{ 232#ifdef PCI_BRIDGE_DEBUG 233 if (bootverbose) 234 printf ("register_mem: bus=%d base=%x limit=%x\n", 235 cb->pcicb_bus, base, limit); 236#endif 237 238 if (!cb->pcicb_mfrom || base < cb->pcicb_mfrom) 239 cb->pcicb_mfrom = base; 240 if (limit > cb->pcicb_mupto) 241 cb->pcicb_mupto = limit; 242 /* 243 ** set the bridges mapping 244 ** 245 ** XXX should handle the 1Mb granularity. 246 */ 247 if (cb->pcicb_bridge.tag) { 248 pci_conf_write(cb->pcicb_bridge, 249 PCI_PCI_BRIDGE_MEM_REG, 250 (cb->pcicb_memlimit & 0xffff0000) | 251 (cb->pcicb_membase >> 16)); 252 if (bootverbose) 253 printf ("\t[pci%d uses memory from %x to %x]\n", 254 cb->pcicb_bus, 255 (unsigned) cb->pcicb_membase, 256 (unsigned) cb->pcicb_memlimit); 257 } 258} 259 260/* 261** XXX This function is neither complete nor tested. 262** It's only used if the bios hasn't done it's job 263** of mapping the pci devices in the physical memory. 264*/ 265 266static u_int 267pci_memalloc (struct pcicb * cb, u_int addr, u_int size) 268{ 269 u_int result = 0, limit=0, newbase=0; 270#ifdef PCI_BRIDGE_DEBUG 271 if (bootverbose) 272 printf ("memalloc: bus=%d addr=%x size=%x ..\n", 273 cb->pcicb_bus, addr, size); 274#endif 275 276 if (!cb) goto done; 277 278 if (!cb->pcicb_membase) { 279 printf ("memalloc: bus%d: membase not set.\n", 280 cb->pcicb_bus); 281 goto done; 282 } 283 284 /* 285 ** get upper allocation limit 286 */ 287 limit = cb->pcicb_memlimit; 288 if (cb->pcicb_mfrom && cb->pcicb_mfrom <= limit) 289 limit = cb->pcicb_mfrom-1; 290 291 /* 292 ** address fixed, and impossible to allocate ? 293 */ 294 if (addr && addr+size-1 > limit) 295 goto done; 296 297 /* 298 ** get possible address 299 */ 300 301 result = addr; 302 if (!result) result = ((limit + 1) / size - 1) * size; 303 304 /* 305 ** if not local available, request from parent. 306 */ 307 308 if (result < cb->pcicb_membase) { 309 newbase = pci_memalloc (cb->pcicb_up, result, size); 310 if (newbase) cb->pcicb_membase = result; 311 else result=0; 312 } 313done: 314 if (result) 315 pci_register_memory (cb, result, result+size-1); 316 317#ifdef PCI_BRIDGE_DEBUG 318 printf ("memalloc: bus=%d addr=%x size=%x --> %x (limit=%x).\n", 319 cb->pcicb_bus, addr, size, result, limit); 320#endif 321 322 return (result); 323} 324 325/*======================================================== 326** 327** pci_bridge_config() 328** 329** Configuration of a pci bridge. 330** 331**======================================================== 332*/ 333 334static int 335pci_bridge_config (void) 336{ 337 pcici_t tag; 338 struct pcicb* parent; 339 340 tag = pcicb->pcicb_bridge; 341 if (tag.tag) { 342 343 if (!pcicb->pcicb_bus) { 344 u_int data; 345 /* 346 ** Get the lowest available bus number. 347 */ 348 pcicb->pcicb_bus = ++pcibusmax; 349 350 /* 351 ** and configure the bridge 352 */ 353 data = pci_conf_read (tag, PCI_PCI_BRIDGE_BUS_REG); 354 data = PCI_PRIMARY_BUS_INSERT(data, pcicb->pcicb_up->pcicb_bus); 355 data = PCI_SECONDARY_BUS_INSERT(data, pcicb->pcicb_bus); 356 data = PCI_SUBORDINATE_BUS_INSERT(data, pcicb->pcicb_bus); 357 pci_conf_write (tag, PCI_PCI_BRIDGE_BUS_REG, data); 358 359 /* 360 ** Propagate the new upper bus number limit. 361 */ 362 for (parent = pcicb->pcicb_up; parent != NULL; 363 parent = parent->pcicb_up) 364 { 365 if (parent->pcicb_subordinate >= pcicb->pcicb_bus) 366 continue; 367 parent->pcicb_subordinate = pcicb->pcicb_bus; 368 if (!parent->pcicb_bridge.tag) 369 continue; 370 data = pci_conf_read 371 (parent->pcicb_bridge, PCI_PCI_BRIDGE_BUS_REG); 372 data = PCI_SUBORDINATE_BUS_INSERT 373 (data, pcicb->pcicb_bus); 374 pci_conf_write (parent->pcicb_bridge, 375 PCI_PCI_BRIDGE_BUS_REG, data); 376 } 377 } 378 379 if (!pcicb->pcicb_membase) { 380 u_int size = 0x100000; 381 pcicb->pcicb_membase = pci_memalloc (pcicb->pcicb_up, 0, size); 382 if (pcicb->pcicb_membase) 383 pcicb->pcicb_memlimit = pcicb->pcicb_membase+size-1; 384 } 385 } 386 return pcicb->pcicb_bus; 387} 388 389/*======================================================== 390** 391** pci_attach() 392** 393** Attach one device 394** 395**======================================================== 396*/ 397 398static void pci_attach (int bus, int dev, int func, 399 struct pci_device *dvp, const char *name) 400{ 401 u_long data; 402 int unit; 403 u_char reg; 404 u_char pciint; 405 int irq; 406 pcici_t tag = pcibus->pb_tag (bus, dev, func); 407 408 /* 409 ** Get and increment the unit. 410 */ 411 412 unit = (*dvp->pd_count)++; 413 414 /* 415 ** Announce this device 416 */ 417 418 printf ("%s%d <%s> rev %d", dvp->pd_name, unit, name, 419 (unsigned) pci_conf_read (tag, PCI_CLASS_REG) & 0xff); 420 421 /* 422 ** Get the int pin number (pci interrupt number a-d) 423 ** from the pci configuration space. 424 */ 425 426 data = pci_conf_read (tag, PCI_INTERRUPT_REG); 427 pciint = PCI_INTERRUPT_PIN_EXTRACT(data); 428 429 if (pciint) { 430 431 printf (" int %c irq ", 0x60+pciint); 432 433 irq = PCI_INTERRUPT_LINE_EXTRACT(data); 434 435 /* 436 ** If it's zero, the isa irq number is unknown, 437 ** and we cannot bind the pci interrupt. 438 */ 439 440 if (irq && (irq != 0xff)) 441 printf ("%d", irq); 442 else 443 printf ("??"); 444 }; 445 446 printf (" on pci%d:%d:%d\n", bus, dev, func); 447 448 /* 449 ** Read the current mapping, 450 ** and update the pcicb fields. 451 */ 452 453 for (reg=PCI_MAP_REG_START;reg<PCI_MAP_REG_END;reg+=4) { 454 u_int map, addr, size; 455 456 data = pci_conf_read(tag, PCI_CLASS_REG); 457 switch (data & (PCI_CLASS_MASK|PCI_SUBCLASS_MASK)) { 458 case PCI_CLASS_BRIDGE|PCI_SUBCLASS_BRIDGE_PCI: 459 continue; 460 }; 461 462 map = pci_conf_read (tag, reg); 463 if (!(map & PCI_MAP_MEMORY_ADDRESS_MASK)) 464 continue; 465 466 pci_conf_write (tag, reg, 0xffffffff); 467 data = pci_conf_read (tag, reg); 468 pci_conf_write (tag, reg, map); 469 470 switch (data & 7) { 471 472 default: 473 continue; 474 case 1: 475 case 5: 476 addr = map & PCI_MAP_IO_ADDRESS_MASK; 477 size = -(data & PCI_MAP_IO_ADDRESS_MASK); 478 size &= ~(addr ^ -addr); 479 480 pci_register_io (pcicb, addr, addr+size-1); 481 pcicb->pcicb_pamount += size; 482 break; 483 484 case 0: 485 case 2: 486 case 4: 487 size = -(data & PCI_MAP_MEMORY_ADDRESS_MASK); 488 addr = map & PCI_MAP_MEMORY_ADDRESS_MASK; 489 if (addr >= 0x100000) { 490 pci_register_memory (pcicb, addr, addr+size-1); 491 pcicb->pcicb_mamount += size; 492 }; 493 break; 494 }; 495 if (bootverbose) 496 printf ("\tmapreg[%02x] type=%d addr=%08x size=%04x.\n", 497 reg, map&7, addr, size); 498 }; 499 500 /* 501 ** attach device 502 ** may produce additional log messages, 503 ** i.e. when installing subdevices. 504 */ 505 506 (*dvp->pd_attach) (tag, unit); 507 508 /* 509 ** Special processing of certain classes 510 */ 511 512 data = pci_conf_read(tag, PCI_CLASS_REG); 513 514 switch (data & (PCI_CLASS_MASK|PCI_SUBCLASS_MASK)) { 515 struct pcicb *this, **link; 516 unsigned char primary, secondary, subordinate; 517 u_int command; 518 519 case PCI_CLASS_BRIDGE|PCI_SUBCLASS_BRIDGE_PCI: 520 521 /* 522 ** get current configuration of the bridge. 523 */ 524 data = pci_conf_read (tag, PCI_PCI_BRIDGE_BUS_REG); 525 primary = PCI_PRIMARY_BUS_EXTRACT (data); 526 secondary = PCI_SECONDARY_BUS_EXTRACT(data); 527 subordinate = PCI_SUBORDINATE_BUS_EXTRACT(data); 528#ifndef PCI_QUIET 529 if (bootverbose) { 530 printf ("\tbridge from pci%d to pci%d through %d.\n", 531 primary, secondary, subordinate); 532 printf ("\tmapping regs: io:%08lx mem:%08lx pmem:%08lx\n", 533 pci_conf_read (tag, PCI_PCI_BRIDGE_IO_REG), 534 pci_conf_read (tag, PCI_PCI_BRIDGE_MEM_REG), 535 pci_conf_read (tag, PCI_PCI_BRIDGE_PMEM_REG)); 536 } 537#endif 538 /* 539 ** check for uninitialized bridge. 540 */ 541 if (!(primary < secondary 542 && secondary <= subordinate 543 && bus == primary)) { 544 545 printf ("\tINCORRECTLY or NEVER CONFIGURED.\n"); 546 /* 547 ** disable this bridge 548 */ 549 pci_conf_write (tag, PCI_COMMAND_STATUS_REG, 0xffff0000); 550 secondary = 0; 551 subordinate = 0; 552 }; 553 554 /* 555 ** allocate bus descriptor for bus behind the bridge 556 */ 557 link = &pcicb->pcicb_down; 558 while (*link && (*link)->pcicb_bus < secondary) 559 link = &(*link)->pcicb_next; 560 561 this = malloc (sizeof (*this), M_DEVBUF, M_WAITOK); 562 563 /* 564 ** Initialize this descriptor so far. 565 ** (the initialization is completed just before 566 ** scanning the bus behind the bridge. 567 */ 568 bzero (this, sizeof(*this)); 569 this->pcicb_next = *link; 570 this->pcicb_up = pcicb; 571 this->pcicb_bridge = tag; 572 this->pcicb_bus = secondary; 573 this->pcicb_subordinate = subordinate; 574 575 command = pci_conf_read(tag,PCI_COMMAND_STATUS_REG); 576 577 if (command & PCI_COMMAND_IO_ENABLE){ 578 /* 579 ** Bridge was configured by the bios. 580 ** Read out the mapped io region. 581 */ 582 unsigned reg; 583 584 reg = pci_conf_read (tag, PCI_PCI_BRIDGE_IO_REG); 585 this->pcicb_iobase = PCI_PPB_IOBASE_EXTRACT (reg); 586 this->pcicb_iolimit = PCI_PPB_IOLIMIT_EXTRACT(reg); 587 588 /* 589 ** Note the used io space. 590 */ 591 pci_register_io (pcicb, this->pcicb_iobase, 592 this->pcicb_iolimit); 593 594 }; 595 596 if (command & PCI_COMMAND_MEM_ENABLE) { 597 /* 598 ** Bridge was configured by the bios. 599 ** Read out the mapped memory regions. 600 */ 601 unsigned reg; 602 603 /* 604 ** non prefetchable memory 605 */ 606 reg = pci_conf_read (tag, PCI_PCI_BRIDGE_MEM_REG); 607 this->pcicb_membase = PCI_PPB_MEMBASE_EXTRACT (reg); 608 this->pcicb_memlimit = PCI_PPB_MEMLIMIT_EXTRACT(reg); 609 610 /* 611 ** Register used memory space. 612 */ 613 pci_register_memory (pcicb, 614 this->pcicb_membase, 615 this->pcicb_memlimit); 616 617 /* 618 ** prefetchable memory 619 */ 620 reg = pci_conf_read (tag, PCI_PCI_BRIDGE_PMEM_REG); 621 this->pcicb_p_membase = PCI_PPB_MEMBASE_EXTRACT (reg); 622 this->pcicb_p_memlimit = PCI_PPB_MEMLIMIT_EXTRACT(reg); 623 624 /* 625 ** Register used memory space. 626 */ 627 pci_register_memory (pcicb, 628 this->pcicb_p_membase, 629 this->pcicb_p_memlimit); 630 } 631 632 /* 633 ** Link it in chain. 634 */ 635 *link=this; 636 637 /* 638 ** Update mapping info of parent bus. 639 */ 640 if (!pcicb->pcicb_bfrom||secondary< pcicb->pcicb_bfrom) 641 pcicb->pcicb_bfrom = secondary; 642 if (subordinate > pcicb->pcicb_bupto) 643 pcicb->pcicb_bupto = subordinate; 644 } 645} 646 647/*======================================================== 648** 649** pci_bus_config() 650** 651** Autoconfiguration of one pci bus. 652** 653**======================================================== 654*/ 655 656static int 657pci_mfdev (int bus, int device) 658{ 659 pcici_t tag0,tag1; 660 unsigned pci_id0, pci_id1; 661 662 /* 663 ** Detect a multi-function device that complies to the PCI 2.0 spec 664 */ 665 tag0 = pcibus->pb_tag (bus, device, 0); 666 if (pci_conf_read (tag0, PCI_HEADER_MISC) & PCI_HEADER_MULTIFUNCTION) 667 return 1; 668 669 /* 670 ** Well, as always: Theory and implementation of PCI ... 671 ** 672 ** If there is a valid device ID returned for function 1 AND 673 ** the device ID of function 0 and 1 is different OR 674 ** the first mapping register of 0 and 1 differs, 675 ** then assume a multi-function device anyway ... 676 ** 677 ** Example of such a broken device: ISA and IDE chip i83371FB (Triton) 678 */ 679 tag1 = pcibus->pb_tag (bus, device, 1); 680 pci_id1 = pci_conf_read (tag1, PCI_ID_REG); 681 682 if (pci_id1 != 0xffffffff) { 683 684 pci_id0 = pci_conf_read (tag0, PCI_ID_REG); 685 686 if (pci_id0 != pci_id1) 687 return 1; 688 689 if (pci_conf_read (tag0, PCI_MAP_REG_START) 690 != pci_conf_read (tag1, PCI_MAP_REG_START)) 691 return 1; 692 } 693 return 0; 694} 695 696static void 697pci_bus_config (void) 698{ 699 int bus_no; 700 u_char device; 701 u_char reg; 702 pcici_t tag, mtag; 703 pcidi_t type; 704 705 struct pci_device *dvp; 706 707 /* 708 ** first initialize the bridge (bus controller chip) 709 */ 710 bus_no = pci_bridge_config (); 711 712 printf ("Probing for devices on PCI bus %d:\n", bus_no); 713#ifndef PCI_QUIET 714 if (bootverbose && !pci_info_done) { 715 pci_info_done=1; 716 printf ("\tconfiguration mode %d allows %d devices.\n", 717 pci_mechanism, pci_maxdevice); 718 }; 719#endif 720 for (device=0; device<pci_maxdevice; device ++) { 721 char *name = NULL; 722 struct pci_device **dvpp; 723 int func, maxfunc = 0; 724 725 for (func=0; func <= maxfunc; func++) { 726 tag = pcibus->pb_tag (bus_no, device, func); 727 type = pci_conf_read (tag, PCI_ID_REG); 728 729 if ((!type) || (type==0xfffffffful)) continue; 730 731 /* 732 ** lookup device in ioconfiguration: 733 */ 734 735 dvpp = (struct pci_device **)pcidevice_set.ls_items; 736 737 while (dvp = *dvpp++) { 738 if (dvp->pd_probe) { 739 if (name=(*dvp->pd_probe)(tag, type)) 740 break; 741 } 742 }; 743 /* 744 ** check for mirrored devices. 745 */ 746 if (func != 0) { 747 goto real_device; 748 } 749 if (device & 0x10) { 750 mtag=pcibus->pb_tag (bus_no, 751 (u_char)(device & ~0x10), 0); 752 } else if (device & 0x08) { 753 mtag=pcibus->pb_tag (bus_no, 754 (u_char)(device & ~0x08), 0); 755 } else goto real_device; 756 757 if (type!=pci_conf_read (mtag, PCI_ID_REG)) 758 goto real_device; 759 760 for (reg=PCI_MAP_REG_START;reg<PCI_MAP_REG_END;reg+=4) 761 if (pci_conf_read(tag,reg)!=pci_conf_read(mtag,reg)) 762 goto real_device; 763 764#ifndef PCI_QUIET 765 if (dvp==NULL) continue; 766 if (bootverbose) 767 printf ("%s? <%s> mirrored on pci%d:%d\n", 768 dvp->pd_name, name, bus_no, device); 769#endif 770 continue; 771 772 real_device: 773 774#ifndef PCI_QUIET 775#ifdef PCI_BRIDGE_DEBUG 776 if (bootverbose) { 777 printf ("\tconfig header: 0x%08x 0x%08x 0x%08x 0x%08x\n", 778 pci_conf_read (tag, 0), 779 pci_conf_read (tag, 4), 780 pci_conf_read (tag, 8), 781 pci_conf_read (tag, 12)); 782 } 783#endif 784#endif 785 786 if (func == 0 && pci_mfdev (bus_no, device)) { 787 maxfunc = 7; 788 } 789 790 pci_remember(bus_no, device, func, dvp); 791 792 if (dvp==NULL) { 793#ifndef PCI_QUIET 794 if (pci_conf_count) 795 continue; 796 797 if (maxfunc == 0) 798 printf("%s%d:%d: ", 799 pcibus->pb_name, bus_no, device); 800 else 801 printf("%s%d:%d:%d: ", 802 pcibus->pb_name, bus_no, device, func); 803 not_supported (tag, type); 804#endif 805 continue; 806 }; 807 808 if (*name) { 809 pci_attach (bus_no, device, func, dvp, name); 810 } 811 } 812 } 813 814#ifndef PCI_QUIET 815 if (bootverbose) { 816 if (pcicb->pcicb_mamount) 817 printf ("%s%d: uses %d bytes of memory from %x upto %x.\n", 818 pcibus->pb_name, bus_no, 819 pcicb->pcicb_mamount, 820 pcicb->pcicb_mfrom, pcicb->pcicb_mupto); 821 if (pcicb->pcicb_pamount) 822 printf ("%s%d: uses %d bytes of I/O space from %x upto %x.\n", 823 pcibus->pb_name, bus_no, 824 pcicb->pcicb_pamount, 825 pcicb->pcicb_pfrom, pcicb->pcicb_pupto); 826 if (pcicb->pcicb_bfrom) 827 printf ("%s%d: subordinate busses from %x upto %x.\n", 828 pcibus->pb_name, bus_no, 829 pcicb->pcicb_bfrom, pcicb->pcicb_bupto); 830 } 831#endif 832} 833 834/*======================================================== 835** 836** pci_configure () 837** 838** Autoconfiguration of pci devices. 839** 840** Has to take care of mirrored devices, which are 841** entailed by incomplete decoding of pci address lines. 842** 843**======================================================== 844*/ 845 846void pci_configure() 847{ 848 struct pcibus **pbp = (struct pcibus**) pcibus_set.ls_items; 849 850 /* 851 ** check pci bus present 852 */ 853 854 while (!pci_maxdevice && (pcibus = *pbp++)) { 855 (*pcibus->pb_setup)(); 856 } 857 858 if (!pci_maxdevice) return; 859 860 /* 861 ** hello world .. 862 */ 863 864 pciroots = 1; 865 while (pciroots--) { 866 867 pcicb = malloc (sizeof (struct pcicb), M_DEVBUF, M_WAITOK); 868 if (pcicb == NULL) { 869 return; 870 } 871 bzero (pcicb, sizeof (struct pcicb)); 872 pcicb->pcicb_bus = pcibusmax; 873 pcicb->pcicb_iolimit = 0xffff; 874 pcicb->pcicb_membase = 0x02000000; 875 pcicb->pcicb_p_membase = 0x02000000; 876 pcicb->pcicb_memlimit = 0xffffffff; 877 pcicb->pcicb_p_memlimit = 0xffffffff; 878 879 while (pcicb != NULL) { 880 pci_bus_config (); 881 882 if (pcibusmax < pcicb->pcicb_bus) 883 (pcibusmax = pcicb->pcicb_bus); 884 885 if (pcicb->pcicb_down) { 886 pcicb = pcicb->pcicb_down; 887 continue; 888 }; 889 890 while (pcicb && !pcicb->pcicb_next) 891 pcicb = pcicb->pcicb_up; 892 893 if (pcicb) 894 pcicb = pcicb->pcicb_next; 895 } 896 pcibusmax++; 897 } 898 pci_conf_count++; 899} 900 901/*======================================================== 902** 903** pci_rescan () 904** 905** try to find lkm driver for device 906** 907** May be called more than once. 908** Any device is attached only once. 909** 910**======================================================== 911*/ 912 913static void pci_rescan() 914{ 915 int i; 916 for (i = 0; i < pci_dev_list_count; i++) 917 { 918 struct pci_lkm *lkm; 919 pcici_t tag; 920 struct pci_device *dvp; 921 pcidi_t type = pci_dev_list[i].pc_devid; 922 char *name = NULL; 923 int bus, dev, func; 924 925 if (pci_dev_list[i].pc_dvp) 926 continue; 927 928 bus = pci_dev_list[i].pc_sel.pc_bus; 929 dev = pci_dev_list[i].pc_sel.pc_dev; 930 func = pci_dev_list[i].pc_sel.pc_func; 931 932 tag = pcibus->pb_tag (bus, dev, func); 933 934 for (lkm = pci_lkm_head; lkm; lkm = lkm->next) { 935 dvp = lkm->dvp; 936 if (name=(*dvp->pd_probe)(tag, type)) 937 break; 938 } 939 if (name && *name) { 940 pcicb = pci_dev_list[i].pc_cb; 941 pci_attach (bus, dev, func, dvp, name); 942 pci_dev_list[i].pc_dvp = dvp; 943 } 944 } 945} 946 947/*======================================================== 948** 949** pci_register_lkm () 950** 951** Add LKM PCI driver's struct pci_device to pci_lkm chain 952** 953**======================================================== 954*/ 955 956int pci_register_lkm (struct pci_device *dvp) 957{ 958 struct pci_lkm *lkm; 959 960 if (!dvp || !dvp->pd_probe || !dvp->pd_attach) { 961 return -1; 962 } 963 964 lkm = malloc (sizeof (*lkm), M_DEVBUF, M_WAITOK); 965 if (!lkm) { 966 return -1; 967 } 968 969 lkm->dvp = dvp; 970 lkm->next = pci_lkm_head; 971 pci_lkm_head = lkm; 972 pci_rescan(); 973 return 0; 974} 975 976/*----------------------------------------------------------------------- 977** 978** Map device into port space. 979** 980** Actually the device should have been mapped by the bios. 981** This function only reads and verifies the value. 982** 983** PCI-Specification: 6.2.5.1: address maps 984** 985**----------------------------------------------------------------------- 986*/ 987 988int pci_map_port (pcici_t tag, u_long reg, u_short* pa) 989{ 990 unsigned data, ioaddr, iosize; 991 struct pcicb *link = pcicb; 992 993 /* 994 ** sanity check 995 */ 996 997 if (reg < PCI_MAP_REG_START || reg >= PCI_MAP_REG_END || (reg & 3)) { 998 printf ("pci_map_port failed: bad register=0x%x\n", 999 (unsigned)reg); 1000 return (0); 1001 }; 1002 1003 /* 1004 ** get size and type of port 1005 ** 1006 ** type is in the lowest two bits. 1007 ** If device requires 2^n bytes, the next 1008 ** n-2 bits are hardwired as 0. 1009 */ 1010 1011 ioaddr = pci_conf_read (tag, reg) & PCI_MAP_IO_ADDRESS_MASK; 1012 if (!ioaddr) { 1013 printf ("pci_map_port failed: not configured by bios.\n"); 1014 return (0); 1015 }; 1016 1017 pci_conf_write (tag, reg, 0xfffffffful); 1018 data = pci_conf_read (tag, reg); 1019 pci_conf_write (tag, reg, ioaddr); 1020 1021 if ((data & 0x03) != PCI_MAP_IO) { 1022 printf ("pci_map_port failed: bad port type=0x%x\n", 1023 (unsigned) data); 1024 return (0); 1025 }; 1026 iosize = -(data & PCI_MAP_IO_ADDRESS_MASK); 1027 iosize &= ~(ioaddr ^ -ioaddr); 1028 if (ioaddr < pcicb->pcicb_iobase 1029 || ioaddr + iosize -1 > pcicb->pcicb_iolimit) { 1030 printf ("pci_map_port failed: device's iorange 0x%x-0x%x " 1031 "is incompatible with its bridge's range 0x%x-0x%x\n", 1032 (unsigned) ioaddr, (unsigned) ioaddr + iosize - 1, 1033 (unsigned) pcicb->pcicb_iobase, 1034 (unsigned) pcicb->pcicb_iolimit); 1035 return (0); 1036 } 1037 1038#ifndef PCI_QUIET 1039 if (bootverbose) 1040 printf ("\treg%d: ioaddr=0x%x size=0x%x\n", 1041 (unsigned) reg, (unsigned) ioaddr, (unsigned) iosize); 1042#endif 1043 /* 1044 ** set the configuration register of and 1045 ** return the address to the driver. 1046 ** Make sure to enable each upstream bridge 1047 ** so I/O and DMA can go all the way. 1048 */ 1049 1050 for (;;) { 1051 data = pci_conf_read (tag, PCI_COMMAND_STATUS_REG) & 0xffff; 1052 data |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MASTER_ENABLE; 1053 (void) pci_conf_write(tag, PCI_COMMAND_STATUS_REG, data); 1054 if ((link = link->pcicb_up) == NULL) 1055 break; 1056 tag = link->pcicb_bridge; 1057 } 1058 1059 *pa = ioaddr; 1060 1061 return (1); 1062} 1063 1064/*----------------------------------------------------------------------- 1065** 1066** Map device into virtual and physical space 1067** 1068** Actually the device should have been mapped by the bios. 1069** This function only reads and verifies the value. 1070** 1071** PCI-Specification: 6.2.5.1: address maps 1072** 1073**----------------------------------------------------------------------- 1074*/ 1075 1076int pci_map_mem (pcici_t tag, u_long reg, vm_offset_t* va, vm_offset_t* pa) 1077{ 1078 struct pcicb *link = pcicb; 1079 unsigned data ,paddr; 1080 vm_size_t psize, poffs; 1081 vm_offset_t vaddr; 1082 1083 /* 1084 ** sanity check 1085 */ 1086 1087 if (reg < PCI_MAP_REG_START || reg >= PCI_MAP_REG_END || (reg & 3)) { 1088 printf ("pci_map_mem failed: bad register=0x%x\n", 1089 (unsigned)reg); 1090 return (0); 1091 }; 1092 1093 /* 1094 ** save old mapping, get size and type of memory 1095 ** 1096 ** type is in the lowest four bits. 1097 ** If device requires 2^n bytes, the next 1098 ** n-4 bits are read as 0. 1099 */ 1100 1101 paddr = pci_conf_read (tag, reg) & PCI_MAP_MEMORY_ADDRESS_MASK; 1102 pci_conf_write (tag, reg, 0xfffffffful); 1103 data = pci_conf_read (tag, reg); 1104 pci_conf_write (tag, reg, paddr); 1105 1106 /* 1107 ** check the type 1108 */ 1109 1110 if (!((data & PCI_MAP_MEMORY_TYPE_MASK) == PCI_MAP_MEMORY_TYPE_32BIT_1M 1111 && (paddr & ~0xfffff) == 0) 1112 && (data & PCI_MAP_MEMORY_TYPE_MASK) != PCI_MAP_MEMORY_TYPE_32BIT){ 1113 printf ("pci_map_mem failed: bad memory type=0x%x\n", 1114 (unsigned) data); 1115 return (0); 1116 }; 1117 1118 /* 1119 ** get the size. 1120 */ 1121 1122 psize = -(data & PCI_MAP_MEMORY_ADDRESS_MASK); 1123 1124 if (!paddr || paddr == PCI_MAP_MEMORY_ADDRESS_MASK) { 1125 paddr = pci_memalloc (pcicb, 0, psize); 1126 if (!paddr) { 1127 printf ("pci_map_mem: not configured by bios.\n"); 1128 return (0); 1129 }; 1130 pci_register_memory (pcicb, paddr, paddr+psize-1); 1131 }; 1132 1133 if (paddr < pcicb->pcicb_membase || 1134 paddr + psize - 1 > pcicb->pcicb_memlimit) { 1135 printf ("pci_map_mem failed: device's memrange 0x%x-0x%x is " 1136 "incompatible with its bridge's memrange 0x%x-0x%x\n", 1137 (unsigned) paddr, 1138 (unsigned) (paddr + psize - 1), 1139 (unsigned) pcicb->pcicb_membase, 1140 (unsigned) pcicb->pcicb_memlimit); 1141/* return (0);*/ 1142/* ACHTUNG: Ist der Code richtig, wenn eine PCI-PCI-Bridge fuer 1143 * die PCI-Slots verwendet wird, aber die Onboard-Devices direkt 1144 * an der CPU-PCI-Bridge haengen (Siehe Compaq Prolinea Problem) ??? 1145 */ 1146 } 1147 pci_conf_write (tag, reg, paddr); 1148 1149 /* 1150 ** Truncate paddr to page boundary. 1151 ** (Or does pmap_mapdev the job?) 1152 */ 1153 1154 poffs = paddr - trunc_page (paddr); 1155 vaddr = (vm_offset_t) pmap_mapdev (paddr-poffs, psize+poffs); 1156 1157 if (!vaddr) return (0); 1158 1159 vaddr += poffs; 1160 1161#ifndef PCI_QUIET 1162 /* 1163 ** display values. 1164 */ 1165 1166 if (bootverbose) 1167 printf ("\treg%d: virtual=0x%lx physical=0x%lx size=0x%lx\n", 1168 (unsigned) reg, (u_long)vaddr, (u_long)paddr, (u_long)psize); 1169#endif 1170 /* 1171 ** set the configuration register and 1172 ** return the address to the driver 1173 ** Make sure to enable each upstream bridge 1174 ** so memory and DMA can go all the way. 1175 */ 1176 1177 for (;;) { 1178 data = pci_conf_read (tag, PCI_COMMAND_STATUS_REG) & 0xffff; 1179 data |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE; 1180 (void) pci_conf_write(tag, PCI_COMMAND_STATUS_REG, data); 1181 if ((link = link->pcicb_up) == NULL) 1182 break; 1183 tag = link->pcicb_bridge; 1184 } 1185 1186 *va = vaddr; 1187 *pa = paddr; 1188 1189 return (1); 1190} 1191 1192/*----------------------------------------------------------------------- 1193** 1194** Pci meta interrupt handler 1195** 1196** This handler assumes level triggered interrupts. 1197** It's possible to build a kernel which handles shared 1198** edge triggered interrupts by the options "PCI_EDGE_INT". 1199** But there is a performance penalty. 1200** 1201** (Of course you can delete the #ifdef PCI_EDGE_INT bracketed 1202** code at all :-) :-) :-) 1203** 1204**----------------------------------------------------------------------- 1205*/ 1206 1207static struct pci_int_desc* 1208 pci_int_desc [PCI_MAX_IRQ]; 1209 1210#ifndef NO_SHARED_IRQ 1211 1212static inline unsigned 1213splq (unsigned mask) 1214{ 1215 unsigned temp=cpl; 1216 cpl |= mask; 1217 return temp; 1218} 1219 1220static void 1221pci_int (int irq) 1222{ 1223 struct pci_int_desc * p; 1224 int s; 1225 1226 if (irq<0 || irq >= PCI_MAX_IRQ) { 1227 printf ("pci_int: irq %d out of range, ignored\n", irq); 1228 return; 1229 }; 1230 for (p = pci_int_desc[irq]; p!=NULL; p=p->pcid_next) { 1231 s = splq (*p->pcid_maskptr); 1232 (*p->pcid_handler) (p->pcid_argument); 1233 p-> pcid_tally++; 1234 splx (s); 1235#if 0 1236 if (p->pcid_tally<20) 1237 printf ("PCI_INT: irq=%d h=%p cpl o=%x n=%x val=%d\n", 1238 irq, p->pcid_handler, s, cpl, c); 1239#endif 1240 }; 1241} 1242#endif 1243 1244/*----------------------------------------------------------------------- 1245** 1246** Auxiliary function for interrupt (un)mapping. 1247** 1248**----------------------------------------------------------------------- 1249*/ 1250 1251static u_int 1252getirq (pcici_t tag) 1253{ 1254 u_int irq; 1255 1256 irq = PCI_INTERRUPT_LINE_EXTRACT( 1257 pci_conf_read (tag, PCI_INTERRUPT_REG)); 1258 1259 if (irq <= 0) { 1260 printf ("\tint line register not set by bios\n"); 1261 return (0); 1262 } 1263 1264 if (irq >= pcibus->pb_maxirq || irq >= PCI_MAX_IRQ) { 1265 printf ("\tirq %d invalid.\n", irq); 1266 return (0); 1267 } 1268 1269 return (irq); 1270} 1271 1272static struct pci_int_desc ** 1273getintdescbytag (u_int irq, pcici_t tag) 1274{ 1275 struct pci_int_desc *p, **pp; 1276 1277 pp=&pci_int_desc[irq]; 1278 while (((p=*pp)) && !sametag(p->pcid_tag,tag)) 1279 pp=&p->pcid_next; 1280 1281 if (!p) return (NULL); 1282 1283 return (pp); 1284} 1285 1286static struct pci_int_desc * 1287getintdescbymptr (u_int irq, unsigned * mptr) 1288{ 1289 struct pci_int_desc *p; 1290 1291 for (p=pci_int_desc[irq];p;p=p->pcid_next) 1292 if (p->pcid_maskptr == mptr) break; 1293 return (p); 1294} 1295 1296/*----------------------------------------------------------------------- 1297** 1298** Map pci interrupt. 1299** 1300**----------------------------------------------------------------------- 1301*/ 1302 1303static unsigned pci_mask0 = 0; 1304 1305int pci_map_int (pcici_t tag, pci_inthand_t *func, void *arg, unsigned *maskptr) 1306{ 1307 u_int irq; 1308 int result, oldspl; 1309 unsigned mask; 1310 struct pci_int_desc *tail, *mdp=NULL, *new=NULL; 1311 1312 /* 1313 ** Get irq line from configuration space, 1314 ** and check for consistency. 1315 */ 1316 1317 irq = getirq (tag); 1318 if ((irq == 0) || (irq >= PCI_MAX_IRQ)) { 1319 printf ("\tillegal irq %d.\n", irq); 1320 return (0); 1321 }; 1322 mask= 1ul << irq; 1323 1324 /* 1325 ** disable this interrupt. 1326 */ 1327 1328 oldspl = splq (mask); 1329 1330 /* 1331 ** If handler for this tag already installed, 1332 ** remove it first. 1333 */ 1334 1335 if (getintdescbytag (irq, tag) != NULL) 1336 pci_unmap_int (tag); 1337 1338 /* 1339 ** If this irq not yet included in the mask, include it. 1340 */ 1341 1342 mdp = getintdescbymptr (irq, maskptr); 1343 if (!mdp) { 1344 result = pcibus->pb_imaskinc (irq, maskptr); 1345 if (result) 1346 goto conflict; 1347 }; 1348 1349 /* 1350 ** Allocate descriptor and initialize it. 1351 */ 1352 1353 tail = pci_int_desc[irq]; 1354 1355 new = malloc (sizeof (*new), M_DEVBUF, M_WAITOK); 1356 bzero (new, sizeof (*new)); 1357 1358 new->pcid_next = tail; 1359 new->pcid_tag = tag; 1360 new->pcid_handler = func; 1361 new->pcid_argument = arg; 1362 new->pcid_maskptr = maskptr; 1363 new->pcid_tally = 0; 1364 new->pcid_mask = mask; 1365 1366 /* 1367 ** If first handler: install it. 1368 ** If second handler: install shared-int-handler. 1369 */ 1370 1371 if (!tail) { 1372 /* 1373 ** first handler for this irq. 1374 */ 1375 1376 result = pcibus->pb_iattach 1377 /* 1378 * XXX if we get here, then `func' must be pci_int 1379 * so the bogus casts are almost OK since they just 1380 * undo the bogus casts that were needed to pass 1381 * pci_int and its arg to pci_map_int(). 1382 */ 1383 (irq, (inthand2_t *) func, (int) arg, maskptr); 1384 if (result) goto conflict; 1385 1386#ifdef NO_SHARED_IRQ 1387 } else goto conflict; 1388#else 1389 } else if (!tail->pcid_next) { 1390 /* 1391 ** Second handler for this irq. 1392 */ 1393 1394 if (bootverbose) 1395 printf ("\tusing shared irq %d.\n", irq); 1396 1397 /* 1398 ** replace old handler by shared-int-handler. 1399 */ 1400 1401 result = pcibus->pb_idetach (irq, 1402 (inthand2_t *) tail->pcid_handler); 1403 if (result) 1404 printf ("\tCANNOT DETACH INT HANDLER.\n"); 1405 1406 result = pcibus->pb_iattach (irq, pci_int, irq, &pci_mask0); 1407 if (result) { 1408 printf ("\tCANNOT ATTACH SHARED INT HANDLER.\n"); 1409 goto fail; 1410 }; 1411 } 1412#endif 1413 /* 1414 ** Link new descriptor, reenable ints and done. 1415 */ 1416 1417 pci_int_desc[irq] = new; 1418 splx (oldspl); 1419 return (1); 1420 1421 /* 1422 ** Handle some problems. 1423 */ 1424 1425conflict: 1426 printf ("\tirq %d already in use.\n", irq); 1427fail: 1428 /* 1429 ** If descriptor allocated, free it. 1430 ** If included in mask, remove it. 1431 */ 1432 1433 if (new) free(new, M_DEVBUF); 1434 if (!mdp) (void) pcibus->pb_imaskexc (irq, maskptr); 1435 splx (oldspl); 1436 return (0); 1437} 1438 1439/*----------------------------------------------------------------------- 1440** 1441** Unmap pci interrupt. 1442** 1443**----------------------------------------------------------------------- 1444*/ 1445 1446int pci_unmap_int (pcici_t tag) 1447{ 1448 int result, oldspl; 1449 struct pci_int_desc *this, **hook, *tail; 1450 unsigned irq; 1451 1452 /* 1453 ** Get irq line from configuration space, 1454 ** and check for consistency. 1455 */ 1456 1457 irq = getirq (tag); 1458 if (irq >= PCI_MAX_IRQ) { 1459 printf ("\tillegal irq %d.\n", irq); 1460 return (0); 1461 }; 1462 1463 /* 1464 ** Search and unlink interrupt descriptor. 1465 */ 1466 1467 hook = getintdescbytag (irq, tag); 1468 if (hook == NULL) { 1469 printf ("\tno irq %d handler for pci %x\n", 1470 irq, tag.tag); 1471 return (0); 1472 }; 1473 1474 this = *hook; 1475 *hook= this->pcid_next; 1476 1477 /* 1478 ** Message 1479 */ 1480 1481 printf ("\tirq %d handler %p(%p) unmapped for pci %x after %d ints.\n", 1482 irq, this->pcid_handler, this->pcid_argument, 1483 this->pcid_tag.tag, this->pcid_tally); 1484 1485 /* 1486 ** If this irq no longer included in the mask, remove it. 1487 */ 1488 1489 if (!getintdescbymptr (irq, this->pcid_maskptr)) 1490 (void) pcibus->pb_imaskexc (irq, this->pcid_maskptr); 1491 1492 tail = pci_int_desc[irq]; 1493 1494 if (tail == NULL) { 1495 1496 /* 1497 ** Remove the old handler. 1498 */ 1499 1500 result = pcibus->pb_idetach (irq, 1501 (inthand2_t *) this->pcid_handler); 1502 if (result) 1503 printf ("\tirq %d: cannot remove handler.\n", irq); 1504 1505 } else if (tail->pcid_next == NULL) { 1506 1507 /* 1508 ** Remove the shared int handler. 1509 ** Install the last remaining handler. 1510 */ 1511 1512 oldspl = splq (1ul << irq); 1513 1514 result = pcibus->pb_idetach (irq, pci_int); 1515 if (result) 1516 printf ("\tirq %d: cannot remove handler.\n", irq); 1517 1518 result = pcibus->pb_iattach (irq, 1519 (inthand2_t *) tail->pcid_handler, 1520 (int) tail->pcid_argument, 1521 tail->pcid_maskptr); 1522 1523 if (result) 1524 printf ("\tirq %d: cannot install handler.\n", irq); 1525 1526 splx (oldspl); 1527 }; 1528 1529 free (this, M_DEVBUF); 1530 return (1); 1531} 1532 1533/*----------------------------------------------------------- 1534** 1535** Display of unknown devices. 1536** 1537**----------------------------------------------------------- 1538*/ 1539struct vt { 1540 u_short ident; 1541 char* name; 1542}; 1543 1544static struct vt VendorTable[] = { 1545 {0x0e11, "Compaq"}, 1546 {0x1000, "NCR/Symbios"}, 1547 {0x1002, "ATI Technologies Inc."}, 1548 {0x1004, "VLSI"}, 1549 {0x100B, "National Semiconductor"}, 1550 {0x100E, "Weitek"}, 1551 {0x1011, "Digital Equipment Corporation"}, 1552 {0x1013, "Cirrus Logic"}, 1553 {0x101A, "NCR"}, 1554 {0x1022, "AMD"}, 1555 {0x102B, "Matrox"}, 1556 {0x102C, "Chips & Technologies"}, 1557 {0x1039, "Silicon Integrated Systems"}, 1558 {0x1042, "SMC"}, 1559 {0x1044, "DPT"}, 1560 {0x1045, "OPTI"}, 1561 {0x104B, "Bus Logic"}, 1562 {0x1060, "UMC"}, 1563 {0x1080, "Contaq"}, 1564 {0x1095, "CMD"}, 1565 {0x10b9, "ACER Labs"}, 1566 {0x1106, "VIA Technologies"}, 1567 {0x5333, "S3 Inc."}, 1568 {0x8086, "Intel Corporation"}, 1569 {0x9004, "Adaptec"}, 1570 {0,0} 1571}; 1572 1573typedef struct { 1574 const int subclass; 1575 const char *name; 1576} subclass_name; 1577 1578/* 0x00 prehistoric subclasses */ 1579static const subclass_name old_subclasses[] = 1580{ 1581 { 0x00, "misc" }, 1582 { 0x01, "vga" }, 1583 { 0x00, NULL } 1584}; 1585 1586/* 0x01 mass storage subclasses */ 1587static const subclass_name storage_subclasses[] = 1588{ 1589 { 0x00, "scsi" }, 1590 { 0x01, "ide" }, 1591 { 0x02, "floppy"}, 1592 { 0x03, "ipi" }, 1593 { 0x80, "misc" }, 1594 { 0x00, NULL } 1595}; 1596 1597/* 0x02 network subclasses */ 1598static const subclass_name network_subclasses[] = 1599{ 1600 { 0x00, "ethernet" }, 1601 { 0x01, "tokenring" }, 1602 { 0x02, "fddi" }, 1603 { 0x80, "misc" }, 1604 { 0x00, NULL } 1605}; 1606 1607/* 0x03 display subclasses */ 1608static const subclass_name display_subclasses[] = 1609{ 1610 { 0x00, "vga" }, 1611 { 0x01, "xga" }, 1612 { 0x80, "misc" }, 1613 { 0x00, NULL } 1614}; 1615 1616/* 0x04 multimedia subclasses */ 1617static const subclass_name multimedia_subclasses[] = 1618{ 1619 { 0x00, "video" }, 1620 { 0x01, "audio" }, 1621 { 0x80, "misc" }, 1622 { 0x00, NULL } 1623}; 1624 1625/* 0x05 memory subclasses */ 1626static const subclass_name memory_subclasses[] = 1627{ 1628 { 0x00, "ram" }, 1629 { 0x01, "flash" }, 1630 { 0x80, "misc" }, 1631 { 0x00, NULL } 1632}; 1633 1634/* 0x06 bridge subclasses */ 1635static const subclass_name bridge_subclasses[] = 1636{ 1637 { 0x00, "host" }, 1638 { 0x01, "isa" }, 1639 { 0x02, "eisa" }, 1640 { 0x03, "mc" }, 1641 { 0x04, "pci" }, 1642 { 0x05, "pcmcia"}, 1643 { 0x80, "misc" }, 1644 { 0x00, NULL } 1645}; 1646 1647static const subclass_name *const subclasses[] = { 1648 old_subclasses, 1649 storage_subclasses, 1650 network_subclasses, 1651 display_subclasses, 1652 multimedia_subclasses, 1653 memory_subclasses, 1654 bridge_subclasses, 1655}; 1656 1657static const char *const majclasses[] = { 1658 "old", 1659 "storage", 1660 "network", 1661 "display", 1662 "multimedia", 1663 "memory", 1664 "bridge" 1665}; 1666 1667 1668void not_supported (pcici_t tag, u_long type) 1669{ 1670 u_long reg; 1671 u_long data; 1672 u_char class; 1673 u_char subclass; 1674 struct vt * vp; 1675 int pciint; 1676 int irq; 1677 1678 /* 1679 ** lookup the names. 1680 */ 1681 1682 for (vp=VendorTable; vp->ident; vp++) 1683 if (vp->ident == (type & 0xffff)) 1684 break; 1685 1686 /* 1687 ** and display them. 1688 */ 1689 1690 if (vp->ident) printf (vp->name); 1691 else printf ("vendor=0x%04lx", type & 0xffff); 1692 1693 printf (", device=0x%04lx", type >> 16); 1694 1695 data = pci_conf_read(tag, PCI_CLASS_REG); 1696 class = (data >> 24) & 0xff; 1697 subclass = (data >> 16) & 0xff; 1698 1699 if (class < sizeof(majclasses) / sizeof(majclasses[0])) { 1700 printf(", class=%s", majclasses[class]); 1701 } else { 1702 printf(", class=0x%02x", class); 1703 } 1704 1705 if (class < sizeof(subclasses) / sizeof(subclasses[0])) { 1706 const subclass_name *p = subclasses[class]; 1707 while (p->name && (p->subclass != subclass)) 1708 p++; 1709 if (p->name) { 1710 printf(" (%s)", p->name); 1711 } else { 1712 printf(" (unknown subclass 0x%02lx)", subclass); 1713 } 1714 } else { 1715 printf(", subclass=0x%02x", subclass); 1716 } 1717 1718 data = pci_conf_read (tag, PCI_INTERRUPT_REG); 1719 pciint = PCI_INTERRUPT_PIN_EXTRACT(data); 1720 1721 if (pciint) { 1722 1723 printf (" int %c irq ", 0x60+pciint); 1724 1725 irq = PCI_INTERRUPT_LINE_EXTRACT(data); 1726 1727 /* 1728 ** If it's zero, the isa irq number is unknown, 1729 ** and we cannot bind the pci interrupt. 1730 */ 1731 1732 if (irq && (irq != 0xff)) 1733 printf ("%d", irq); 1734 else 1735 printf ("??"); 1736 }; 1737 1738 if (class != (PCI_CLASS_BRIDGE >> 24)) 1739 printf (" [no driver assigned]"); 1740 printf ("\n"); 1741 1742 if (bootverbose) { 1743 if (class == (PCI_CLASS_BRIDGE >> 24)) { 1744 printf ("configuration space registers:"); 1745 for (reg = 0; reg < 0x100; reg+=4) { 1746 if ((reg & 0x0f) == 0) printf ("\n%02x:\t", reg); 1747 printf ("%08x ", pci_conf_read (tag, reg)); 1748 } 1749 printf ("\n"); 1750 } else { 1751 for (reg=PCI_MAP_REG_START; reg<PCI_MAP_REG_END; reg+=4) { 1752 data = pci_conf_read (tag, reg); 1753 if ((data&~7)==0) continue; 1754 switch (data&7) { 1755 1756 case 1: 1757 case 5: 1758 printf ("\tmap(%x): io(%04lx)\n", 1759 reg, data & ~3); 1760 break; 1761 case 0: 1762 printf ("\tmap(%x): mem32(%08lx)\n", 1763 reg, data & ~7); 1764 break; 1765 case 2: 1766 printf ("\tmap(%x): mem20(%05lx)\n", 1767 reg, data & ~7); 1768 break; 1769 case 4: 1770 printf ("\tmap(%x): mem64(%08x%08lx)\n", 1771 reg, pci_conf_read (tag, reg +4), data & ~7); 1772 reg += 4; 1773 break; 1774 } 1775 } 1776 } 1777 } 1778} 1779 1780/* 1781 * This is the user interface to the PCI configuration space. 1782 */ 1783 1784 1785static void 1786pci_remember(int bus, int dev, int func, struct pci_device *dvp) 1787{ 1788 struct pci_conf *p; 1789 pcici_t tag; 1790 1791 if (++pci_dev_list_count > pci_dev_list_size) { 1792 struct pci_conf *new; 1793 1794 pci_dev_list_size += 8; 1795 MALLOC(new, struct pci_conf *, pci_dev_list_size * sizeof *new, 1796 M_DEVL, M_NOWAIT); 1797 if (!new) { 1798 pci_dev_list_size -= 8; 1799 pci_dev_list_count--; 1800 return; 1801 } 1802 1803 if (pci_dev_list) { 1804 bcopy(pci_dev_list, new, ((pci_dev_list_size - 8) * 1805 sizeof *new)); 1806 FREE(pci_dev_list, M_DEVL); 1807 } 1808 pci_dev_list = new; 1809 } 1810 1811 p = &pci_dev_list[pci_dev_list_count - 1]; 1812 p->pc_sel.pc_bus = bus; 1813 p->pc_sel.pc_dev = dev; 1814 p->pc_sel.pc_func = func; 1815 p->pc_hdr = (pci_conf_read (tag, PCI_HEADER_MISC) >> 16) & 0xff; 1816 tag = pcibus->pb_tag (bus, dev, func); 1817 p->pc_devid = pci_conf_read(tag, PCI_ID_REG); 1818 p->pc_dvp = dvp; 1819 p->pc_cb = pcicb; 1820 if ((p->pc_hdr & 0x7f) == 1) { 1821 p->pc_subid = pci_conf_read(tag, PCI_SUBID_REG1); 1822 } else { 1823 p->pc_subid = pci_conf_read(tag, PCI_SUBID_REG0); 1824 } 1825 p->pc_class = pci_conf_read(tag, PCI_CLASS_REG); 1826} 1827 1828static int 1829pci_open(dev_t dev, int oflags, int devtype, struct proc *p) 1830{ 1831 if ((oflags & FWRITE) && securelevel > 0) { 1832 return EPERM; 1833 } 1834 1835 return 0; 1836} 1837 1838static int 1839pci_close(dev_t dev, int flag, int devtype, struct proc *p) 1840{ 1841 return 0; 1842} 1843 1844static int 1845pci_ioctl(dev_t dev, int cmd, caddr_t data, int flag, struct proc *p) 1846{ 1847 struct pci_conf_io *cio; 1848 struct pci_io *io; 1849 size_t iolen; 1850 int error; 1851 pcici_t tag; 1852 1853 if (cmd != PCIOCGETCONF && !(flag & FWRITE)) 1854 return EPERM; 1855 1856 switch(cmd) { 1857 case PCIOCGETCONF: 1858 cio = (struct pci_conf_io *)data; 1859 iolen = min(cio->pci_len, 1860 pci_dev_list_count * sizeof(struct pci_conf)); 1861 cio->pci_len = pci_dev_list_count * sizeof(struct pci_conf); 1862 1863 error = copyout(pci_dev_list, cio->pci_buf, iolen); 1864 break; 1865 1866 case PCIOCREAD: 1867 io = (struct pci_io *)data; 1868 switch(io->pi_width) { 1869 case 4: 1870 tag = pcibus->pb_tag (io->pi_sel.pc_bus, 1871 io->pi_sel.pc_dev, 1872 io->pi_sel.pc_func); 1873 io->pi_data = pci_conf_read(tag, io->pi_reg); 1874 error = 0; 1875 break; 1876 case 2: 1877 case 1: 1878 default: 1879 error = ENODEV; 1880 break; 1881 } 1882 break; 1883 1884 case PCIOCWRITE: 1885 io = (struct pci_io *)data; 1886 switch(io->pi_width) { 1887 case 4: 1888 tag = pcibus->pb_tag (io->pi_sel.pc_bus, 1889 io->pi_sel.pc_dev, 1890 io->pi_sel.pc_func); 1891 pci_conf_write(tag, io->pi_reg, io->pi_data); 1892 error = 0; 1893 break; 1894 case 2: 1895 case 1: 1896 default: 1897 error = ENODEV; 1898 break; 1899 } 1900 break; 1901 1902 case PCIOCATTACHED: 1903 io = (struct pci_io *)data; 1904 switch(io->pi_width) { 1905 case 4: 1906 { 1907 int i = pci_dev_list_count; 1908 struct pci_conf *p = pci_dev_list; 1909 error = ENODEV; 1910 while (i--) { 1911 if (io->pi_sel.pc_bus == p->pc_sel.pc_bus && 1912 io->pi_sel.pc_dev == p->pc_sel.pc_dev && 1913 io->pi_sel.pc_func == p->pc_sel.pc_func) { 1914 io->pi_data = (u_int32_t)p->pc_dvp; 1915 error = 0; 1916 break; 1917 } 1918 p++; 1919 } 1920 } 1921 break; 1922 case 2: 1923 case 1: 1924 default: 1925 error = ENODEV; 1926 break; 1927 } 1928 break; 1929 1930 default: 1931 error = ENOTTY; 1932 break; 1933 } 1934 1935 return (error); 1936} 1937 1938#define PCI_CDEV 78 1939 1940static struct cdevsw pcicdev = { 1941 pci_open, pci_close, noread, nowrite, pci_ioctl, nostop, noreset, 1942 nodevtotty, noselect, nommap, nostrategy, "pci", 0, PCI_CDEV 1943}; 1944 1945#ifdef DEVFS 1946static void *pci_devfs_token; 1947#endif 1948 1949static void 1950pci_cdevinit(void *dummy) 1951{ 1952 dev_t dev; 1953 1954 dev = makedev(PCI_CDEV, 0); 1955 cdevsw_add(&dev, &pcicdev, NULL); 1956#ifdef DEVFS 1957 pci_devfs_token = devfs_add_devswf(&pcicdev, 0, DV_CHR, 1958 UID_ROOT, GID_WHEEL, 0644, "pci"); 1959#endif 1960} 1961 1962SYSINIT(pcidev, SI_SUB_DRIVERS, SI_ORDER_MIDDLE+PCI_CDEV, pci_cdevinit, NULL); 1963 1964#endif /* NPCI */ 1965