Searched refs:reg_name (Results 1 - 25 of 290) sorted by last modified time

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/linux-master/kernel/bpf/
H A Dverifier.c368 const char *reg_name)
372 verbose(env, "%s the register %s has", ctx, reg_name);
5205 const char *reg_name = ""; local
5223 reg_name = btf_type_name(reg->btf, reg->btf_id);
5265 reg_type_str(env, reg->type), reg_name);
12091 static int check_return_code(struct bpf_verifier_env *env, int regno, const char *reg_name);
15373 static int check_return_code(struct bpf_verifier_env *env, int regno, const char *reg_name) argument
15525 verbose_invalid_scalar(env, reg, range, exit_ctx, reg_name);
365 verbose_invalid_scalar(struct bpf_verifier_env *env, struct bpf_reg_state *reg, struct bpf_retval_range range, const char *ctx, const char *reg_name) argument
/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn20/
H A Ddcn20_resource.c129 #define SR(reg_name)\
130 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
131 mm ## reg_name
133 #define SRI(reg_name, block, id)\
134 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
135 mm ## block ## id ## _ ## reg_name
137 #define SRI2_DWB(reg_name, block, id)\
138 .reg_name
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/linux-master/drivers/gpu/drm/amd/display/dc/dcn31/
H A Ddcn31_hpo_dp_link_encoder.c38 #define FN(reg_name, field_name) \
/linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/
H A Ddcn32_clk_mgr.c85 #define FN(reg_name, field_name) \
95 #define SR(reg_name)\
96 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
97 reg ## reg_name
99 #define CLK_SR_DCN32(reg_name)\
100 .reg_name = mm ## reg_name
115 #define CLK_SR_DCN321(reg_name, block, inst)\
116 .reg_name
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/linux-master/drivers/gpu/drm/amd/display/dc/dcn35/
H A Ddcn35_dio_link_encoder.c40 #define FN(reg_name, field_name) \
/linux-master/drivers/gpu/drm/amd/display/dc/dcn32/
H A Ddcn32_dio_link_encoder.c53 #define FN(reg_name, field_name) \
59 #define AUX_REG_READ(reg_name) \
60 dm_read_reg(CTX, AUX_REG(reg_name))
62 #define AUX_REG_WRITE(reg_name, val) \
63 dm_write_reg(CTX, AUX_REG(reg_name), val)
H A Ddcn32_mpc.c41 #define FN(reg_name, field_name) \
/linux-master/drivers/gpu/drm/amd/display/dc/optc/dcn32/
H A Ddcn32_optc.c42 #define FN(reg_name, field_name) \
/linux-master/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_clock_source.c53 #define FN(reg_name, field_name) \
/linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/
H A Ddcn35_clk_mgr.c84 #define REG(reg_name) \
85 (ctx->clk_reg_offsets[reg ## reg_name ## _BASE_IDX] + reg ## reg_name)
/linux-master/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_device.c6462 uint32_t inst, uint32_t reg_addr, char reg_name[],
6480 inst, reg_name, (uint32_t)expected_value,
6461 amdgpu_device_wait_on_rreg(struct amdgpu_device *adev, uint32_t inst, uint32_t reg_addr, char reg_name[], uint32_t expected_value, uint32_t mask) argument
H A Damdgpu.h1203 uint32_t inst, uint32_t reg_addr, char reg_name[],
/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn351/
H A Ddcn351_resource.c111 #define SR(reg_name)\
112 REG_STRUCT.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
113 reg ## reg_name
115 #define SR_ARR(reg_name, id) \
116 REG_STRUCT[id].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
118 #define SR_ARR_INIT(reg_name, id, value) \
119 REG_STRUCT[id].reg_name
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/linux-master/drivers/gpu/drm/amd/display/dc/hwss/dcn35/
H A Ddcn35_hwseq.c73 #define FN(reg_name, field_name) \
/linux-master/drivers/gpu/drm/amd/display/dc/hwss/dcn32/
H A Ddcn32_hwseq.c67 #define FN(reg_name, field_name) \
/linux-master/drivers/gpu/drm/amd/display/dc/hwss/dcn314/
H A Ddcn314_hwseq.c69 #define FN(reg_name, field_name) \
/linux-master/drivers/gpu/drm/amd/display/dc/hwss/dce110/
H A Ddce110_hwseq.c94 #define FN(reg_name, field_name) \
/linux-master/drivers/gpu/drm/amd/display/dc/dcn30/
H A Ddcn30_mpc.c40 #define FN(reg_name, field_name) \
H A Ddcn30_mpc.h38 #define SRII_MPC_RMU(reg_name, block, id)\
39 .RMU##_##reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
40 mm ## block ## id ## _ ## reg_name
/linux-master/tools/objtool/arch/x86/
H A Dorc.c121 static const char *reg_name(unsigned int reg) function
174 printf("%s%+d", reg_name(reg), offset);
/linux-master/tools/objtool/arch/loongarch/
H A Dorc.c120 static const char *reg_name(unsigned int reg) function
153 printf("%s + %3d", reg_name(reg), offset);
/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn321/
H A Ddcn321_resource.c117 #define SR(reg_name)\
118 REG_STRUCT.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
119 reg ## reg_name
120 #define SR_ARR(reg_name, id)\
121 REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
122 reg ## reg_name
123 #define SR_ARR_INIT(reg_name, id, value)\
124 REG_STRUCT[id].reg_name
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn32/
H A Ddcn32_resource.c116 #define SR(reg_name)\
117 REG_STRUCT.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
118 reg ## reg_name
119 #define SR_ARR(reg_name, id) \
120 REG_STRUCT[id].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
122 #define SR_ARR_INIT(reg_name, id, value) \
123 REG_STRUCT[id].reg_name
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/linux-master/drivers/gpu/drm/amd/display/dc/hwss/dcn30/
H A Ddcn30_hwseq.c69 #define FN(reg_name, field_name) \
/linux-master/drivers/gpu/drm/amd/display/dc/hwss/dcn20/
H A Ddcn20_hwseq.c71 #define FN(reg_name, field_name) \

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