/linux-master/kernel/bpf/ |
H A D | verifier.c | 368 const char *reg_name) 372 verbose(env, "%s the register %s has", ctx, reg_name); 5205 const char *reg_name = ""; local 5223 reg_name = btf_type_name(reg->btf, reg->btf_id); 5265 reg_type_str(env, reg->type), reg_name); 12091 static int check_return_code(struct bpf_verifier_env *env, int regno, const char *reg_name); 15373 static int check_return_code(struct bpf_verifier_env *env, int regno, const char *reg_name) argument 15525 verbose_invalid_scalar(env, reg, range, exit_ctx, reg_name); 365 verbose_invalid_scalar(struct bpf_verifier_env *env, struct bpf_reg_state *reg, struct bpf_retval_range range, const char *ctx, const char *reg_name) argument
|
/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn20/ |
H A D | dcn20_resource.c | 129 #define SR(reg_name)\ 130 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \ 131 mm ## reg_name 133 #define SRI(reg_name, block, id)\ 134 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 135 mm ## block ## id ## _ ## reg_name 137 #define SRI2_DWB(reg_name, block, id)\ 138 .reg_name [all...] |
/linux-master/drivers/gpu/drm/amd/display/dc/dcn31/ |
H A D | dcn31_hpo_dp_link_encoder.c | 38 #define FN(reg_name, field_name) \
|
/linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/ |
H A D | dcn32_clk_mgr.c | 85 #define FN(reg_name, field_name) \ 95 #define SR(reg_name)\ 96 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \ 97 reg ## reg_name 99 #define CLK_SR_DCN32(reg_name)\ 100 .reg_name = mm ## reg_name 115 #define CLK_SR_DCN321(reg_name, block, inst)\ 116 .reg_name [all...] |
/linux-master/drivers/gpu/drm/amd/display/dc/dcn35/ |
H A D | dcn35_dio_link_encoder.c | 40 #define FN(reg_name, field_name) \
|
/linux-master/drivers/gpu/drm/amd/display/dc/dcn32/ |
H A D | dcn32_dio_link_encoder.c | 53 #define FN(reg_name, field_name) \ 59 #define AUX_REG_READ(reg_name) \ 60 dm_read_reg(CTX, AUX_REG(reg_name)) 62 #define AUX_REG_WRITE(reg_name, val) \ 63 dm_write_reg(CTX, AUX_REG(reg_name), val)
|
H A D | dcn32_mpc.c | 41 #define FN(reg_name, field_name) \
|
/linux-master/drivers/gpu/drm/amd/display/dc/optc/dcn32/ |
H A D | dcn32_optc.c | 42 #define FN(reg_name, field_name) \
|
/linux-master/drivers/gpu/drm/amd/display/dc/dce/ |
H A D | dce_clock_source.c | 53 #define FN(reg_name, field_name) \
|
/linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/ |
H A D | dcn35_clk_mgr.c | 84 #define REG(reg_name) \ 85 (ctx->clk_reg_offsets[reg ## reg_name ## _BASE_IDX] + reg ## reg_name)
|
/linux-master/drivers/gpu/drm/amd/amdgpu/ |
H A D | amdgpu_device.c | 6462 uint32_t inst, uint32_t reg_addr, char reg_name[], 6480 inst, reg_name, (uint32_t)expected_value, 6461 amdgpu_device_wait_on_rreg(struct amdgpu_device *adev, uint32_t inst, uint32_t reg_addr, char reg_name[], uint32_t expected_value, uint32_t mask) argument
|
H A D | amdgpu.h | 1203 uint32_t inst, uint32_t reg_addr, char reg_name[],
|
/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn351/ |
H A D | dcn351_resource.c | 111 #define SR(reg_name)\ 112 REG_STRUCT.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \ 113 reg ## reg_name 115 #define SR_ARR(reg_name, id) \ 116 REG_STRUCT[id].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name 118 #define SR_ARR_INIT(reg_name, id, value) \ 119 REG_STRUCT[id].reg_name [all...] |
/linux-master/drivers/gpu/drm/amd/display/dc/hwss/dcn35/ |
H A D | dcn35_hwseq.c | 73 #define FN(reg_name, field_name) \
|
/linux-master/drivers/gpu/drm/amd/display/dc/hwss/dcn32/ |
H A D | dcn32_hwseq.c | 67 #define FN(reg_name, field_name) \
|
/linux-master/drivers/gpu/drm/amd/display/dc/hwss/dcn314/ |
H A D | dcn314_hwseq.c | 69 #define FN(reg_name, field_name) \
|
/linux-master/drivers/gpu/drm/amd/display/dc/hwss/dce110/ |
H A D | dce110_hwseq.c | 94 #define FN(reg_name, field_name) \
|
/linux-master/drivers/gpu/drm/amd/display/dc/dcn30/ |
H A D | dcn30_mpc.c | 40 #define FN(reg_name, field_name) \
|
H A D | dcn30_mpc.h | 38 #define SRII_MPC_RMU(reg_name, block, id)\ 39 .RMU##_##reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 40 mm ## block ## id ## _ ## reg_name
|
/linux-master/tools/objtool/arch/x86/ |
H A D | orc.c | 121 static const char *reg_name(unsigned int reg) function 174 printf("%s%+d", reg_name(reg), offset);
|
/linux-master/tools/objtool/arch/loongarch/ |
H A D | orc.c | 120 static const char *reg_name(unsigned int reg) function 153 printf("%s + %3d", reg_name(reg), offset);
|
/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn321/ |
H A D | dcn321_resource.c | 117 #define SR(reg_name)\ 118 REG_STRUCT.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \ 119 reg ## reg_name 120 #define SR_ARR(reg_name, id)\ 121 REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \ 122 reg ## reg_name 123 #define SR_ARR_INIT(reg_name, id, value)\ 124 REG_STRUCT[id].reg_name [all...] |
/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn32/ |
H A D | dcn32_resource.c | 116 #define SR(reg_name)\ 117 REG_STRUCT.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \ 118 reg ## reg_name 119 #define SR_ARR(reg_name, id) \ 120 REG_STRUCT[id].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name 122 #define SR_ARR_INIT(reg_name, id, value) \ 123 REG_STRUCT[id].reg_name [all...] |
/linux-master/drivers/gpu/drm/amd/display/dc/hwss/dcn30/ |
H A D | dcn30_hwseq.c | 69 #define FN(reg_name, field_name) \
|
/linux-master/drivers/gpu/drm/amd/display/dc/hwss/dcn20/ |
H A D | dcn20_hwseq.c | 71 #define FN(reg_name, field_name) \
|