1/* 2 * Copyright 2022 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26#include "dcn32_optc.h" 27 28#include "dcn30/dcn30_optc.h" 29#include "dcn31/dcn31_optc.h" 30#include "reg_helper.h" 31#include "dc.h" 32#include "dcn_calc_math.h" 33#include "dc_dmub_srv.h" 34 35#define REG(reg)\ 36 optc1->tg_regs->reg 37 38#define CTX \ 39 optc1->base.ctx 40 41#undef FN 42#define FN(reg_name, field_name) \ 43 optc1->tg_shift->field_name, optc1->tg_mask->field_name 44 45static void optc32_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt, 46 struct dc_crtc_timing *timing) 47{ 48 struct optc *optc1 = DCN10TG_FROM_TG(optc); 49 uint32_t memory_mask = 0; 50 int h_active = timing->h_addressable + timing->h_border_left + timing->h_border_right; 51 int mpcc_hactive = h_active / opp_cnt; 52 /* Each memory instance is 2048x(32x2) bits to support half line of 4096 */ 53 int odm_mem_count = (h_active + 2047) / 2048; 54 55 /* 56 * display <= 4k : 2 memories + 2 pipes 57 * 4k < display <= 8k : 4 memories + 2 pipes 58 * 8k < display <= 12k : 6 memories + 4 pipes 59 */ 60 if (opp_cnt == 4) { 61 if (odm_mem_count <= 2) 62 memory_mask = 0x3; 63 else if (odm_mem_count <= 4) 64 memory_mask = 0xf; 65 else 66 memory_mask = 0x3f; 67 } else { 68 if (odm_mem_count <= 2) 69 memory_mask = 0x1 << (opp_id[0] * 2) | 0x1 << (opp_id[1] * 2); 70 else if (odm_mem_count <= 4) 71 memory_mask = 0x3 << (opp_id[0] * 2) | 0x3 << (opp_id[1] * 2); 72 else 73 memory_mask = 0x77; 74 } 75 76 REG_SET(OPTC_MEMORY_CONFIG, 0, 77 OPTC_MEM_SEL, memory_mask); 78 79 if (opp_cnt == 2) { 80 REG_SET_3(OPTC_DATA_SOURCE_SELECT, 0, 81 OPTC_NUM_OF_INPUT_SEGMENT, 1, 82 OPTC_SEG0_SRC_SEL, opp_id[0], 83 OPTC_SEG1_SRC_SEL, opp_id[1]); 84 } else if (opp_cnt == 4) { 85 REG_SET_5(OPTC_DATA_SOURCE_SELECT, 0, 86 OPTC_NUM_OF_INPUT_SEGMENT, 3, 87 OPTC_SEG0_SRC_SEL, opp_id[0], 88 OPTC_SEG1_SRC_SEL, opp_id[1], 89 OPTC_SEG2_SRC_SEL, opp_id[2], 90 OPTC_SEG3_SRC_SEL, opp_id[3]); 91 } 92 93 REG_UPDATE(OPTC_WIDTH_CONTROL, 94 OPTC_SEGMENT_WIDTH, mpcc_hactive); 95 96 REG_UPDATE(OTG_H_TIMING_CNTL, 97 OTG_H_TIMING_DIV_MODE, opp_cnt - 1); 98 optc1->opp_count = opp_cnt; 99} 100 101void optc32_get_odm_combine_segments(struct timing_generator *tg, int *odm_combine_segments) 102{ 103 struct optc *optc1 = DCN10TG_FROM_TG(tg); 104 int segments; 105 106 REG_GET(OPTC_DATA_SOURCE_SELECT, OPTC_NUM_OF_INPUT_SEGMENT, &segments); 107 108 switch (segments) { 109 case 0: 110 *odm_combine_segments = 1; 111 break; 112 case 1: 113 *odm_combine_segments = 2; 114 break; 115 case 3: 116 *odm_combine_segments = 4; 117 break; 118 /* 2 is reserved */ 119 case 2: 120 default: 121 *odm_combine_segments = -1; 122 } 123} 124 125void optc32_wait_odm_doublebuffer_pending_clear(struct timing_generator *tg) 126{ 127 struct optc *optc1 = DCN10TG_FROM_TG(tg); 128 129 REG_WAIT(OTG_DOUBLE_BUFFER_CONTROL, OTG_H_TIMING_DIV_MODE_DB_UPDATE_PENDING, 0, 2, 50000); 130} 131 132void optc32_set_h_timing_div_manual_mode(struct timing_generator *optc, bool manual_mode) 133{ 134 struct optc *optc1 = DCN10TG_FROM_TG(optc); 135 136 REG_UPDATE(OTG_H_TIMING_CNTL, 137 OTG_H_TIMING_DIV_MODE_MANUAL, manual_mode ? 1 : 0); 138} 139/** 140 * optc32_enable_crtc() - Enable CRTC - call ASIC Control Object to enable Timing generator. 141 * 142 * @optc: timing_generator instance. 143 * 144 * Return: If CRTC is enabled, return true. 145 */ 146static bool optc32_enable_crtc(struct timing_generator *optc) 147{ 148 struct optc *optc1 = DCN10TG_FROM_TG(optc); 149 150 /* opp instance for OTG, 1 to 1 mapping and odm will adjust */ 151 REG_UPDATE(OPTC_DATA_SOURCE_SELECT, 152 OPTC_SEG0_SRC_SEL, optc->inst); 153 154 /* VTG enable first is for HW workaround */ 155 REG_UPDATE(CONTROL, 156 VTG0_ENABLE, 1); 157 158 REG_SEQ_START(); 159 160 /* Enable CRTC */ 161 REG_UPDATE_2(OTG_CONTROL, 162 OTG_DISABLE_POINT_CNTL, 2, 163 OTG_MASTER_EN, 1); 164 165 REG_SEQ_SUBMIT(); 166 REG_SEQ_WAIT_DONE(); 167 168 return true; 169} 170 171/* disable_crtc */ 172static bool optc32_disable_crtc(struct timing_generator *optc) 173{ 174 struct optc *optc1 = DCN10TG_FROM_TG(optc); 175 176 REG_UPDATE_5(OPTC_DATA_SOURCE_SELECT, 177 OPTC_SEG0_SRC_SEL, 0xf, 178 OPTC_SEG1_SRC_SEL, 0xf, 179 OPTC_SEG2_SRC_SEL, 0xf, 180 OPTC_SEG3_SRC_SEL, 0xf, 181 OPTC_NUM_OF_INPUT_SEGMENT, 0); 182 183 REG_UPDATE(OPTC_MEMORY_CONFIG, 184 OPTC_MEM_SEL, 0); 185 186 /* disable otg request until end of the first line 187 * in the vertical blank region 188 */ 189 REG_UPDATE(OTG_CONTROL, 190 OTG_MASTER_EN, 0); 191 192 REG_UPDATE(CONTROL, 193 VTG0_ENABLE, 0); 194 195 /* CRTC disabled, so disable clock. */ 196 REG_WAIT(OTG_CLOCK_CONTROL, 197 OTG_BUSY, 0, 198 1, 150000); 199 200 return true; 201} 202 203static void optc32_phantom_crtc_post_enable(struct timing_generator *optc) 204{ 205 struct optc *optc1 = DCN10TG_FROM_TG(optc); 206 207 /* Disable immediately. */ 208 REG_UPDATE_2(OTG_CONTROL, OTG_DISABLE_POINT_CNTL, 0, OTG_MASTER_EN, 0); 209 210 /* CRTC disabled, so disable clock. */ 211 REG_WAIT(OTG_CLOCK_CONTROL, OTG_BUSY, 0, 1, 100000); 212} 213 214static void optc32_disable_phantom_otg(struct timing_generator *optc) 215{ 216 struct optc *optc1 = DCN10TG_FROM_TG(optc); 217 218 REG_UPDATE_5(OPTC_DATA_SOURCE_SELECT, 219 OPTC_SEG0_SRC_SEL, 0xf, 220 OPTC_SEG1_SRC_SEL, 0xf, 221 OPTC_SEG2_SRC_SEL, 0xf, 222 OPTC_SEG3_SRC_SEL, 0xf, 223 OPTC_NUM_OF_INPUT_SEGMENT, 0); 224 225 REG_UPDATE(OTG_CONTROL, OTG_MASTER_EN, 0); 226} 227 228void optc32_set_odm_bypass(struct timing_generator *optc, 229 const struct dc_crtc_timing *dc_crtc_timing) 230{ 231 struct optc *optc1 = DCN10TG_FROM_TG(optc); 232 enum h_timing_div_mode h_div = H_TIMING_NO_DIV; 233 234 REG_SET_5(OPTC_DATA_SOURCE_SELECT, 0, 235 OPTC_NUM_OF_INPUT_SEGMENT, 0, 236 OPTC_SEG0_SRC_SEL, optc->inst, 237 OPTC_SEG1_SRC_SEL, 0xf, 238 OPTC_SEG2_SRC_SEL, 0xf, 239 OPTC_SEG3_SRC_SEL, 0xf 240 ); 241 242 h_div = optc1_is_two_pixels_per_containter(dc_crtc_timing); 243 REG_UPDATE(OTG_H_TIMING_CNTL, 244 OTG_H_TIMING_DIV_MODE, h_div); 245 246 REG_SET(OPTC_MEMORY_CONFIG, 0, 247 OPTC_MEM_SEL, 0); 248 optc1->opp_count = 1; 249} 250 251static void optc32_setup_manual_trigger(struct timing_generator *optc) 252{ 253 struct optc *optc1 = DCN10TG_FROM_TG(optc); 254 struct dc *dc = optc->ctx->dc; 255 256 if (dc->caps.dmub_caps.mclk_sw && !dc->debug.disable_fams) 257 dc_dmub_srv_set_drr_manual_trigger_cmd(dc, optc->inst); 258 else { 259 /* 260 * MIN_MASK_EN is gone and MASK is now always enabled. 261 * 262 * To get it to it work with manual trigger we need to make sure 263 * we program the correct bit. 264 */ 265 REG_UPDATE_4(OTG_V_TOTAL_CONTROL, 266 OTG_V_TOTAL_MIN_SEL, 1, 267 OTG_V_TOTAL_MAX_SEL, 1, 268 OTG_FORCE_LOCK_ON_EVENT, 0, 269 OTG_SET_V_TOTAL_MIN_MASK, (1 << 1)); /* TRIGA */ 270 } 271} 272 273static void optc32_set_drr( 274 struct timing_generator *optc, 275 const struct drr_params *params) 276{ 277 struct optc *optc1 = DCN10TG_FROM_TG(optc); 278 279 if (params != NULL && 280 params->vertical_total_max > 0 && 281 params->vertical_total_min > 0) { 282 283 if (params->vertical_total_mid != 0) { 284 285 REG_SET(OTG_V_TOTAL_MID, 0, 286 OTG_V_TOTAL_MID, params->vertical_total_mid - 1); 287 288 REG_UPDATE_2(OTG_V_TOTAL_CONTROL, 289 OTG_VTOTAL_MID_REPLACING_MAX_EN, 1, 290 OTG_VTOTAL_MID_FRAME_NUM, 291 (uint8_t)params->vertical_total_mid_frame_num); 292 293 } 294 295 optc->funcs->set_vtotal_min_max(optc, params->vertical_total_min - 1, params->vertical_total_max - 1); 296 } 297 298 optc32_setup_manual_trigger(optc); 299} 300 301static struct timing_generator_funcs dcn32_tg_funcs = { 302 .validate_timing = optc1_validate_timing, 303 .program_timing = optc1_program_timing, 304 .setup_vertical_interrupt0 = optc1_setup_vertical_interrupt0, 305 .setup_vertical_interrupt1 = optc1_setup_vertical_interrupt1, 306 .setup_vertical_interrupt2 = optc1_setup_vertical_interrupt2, 307 .program_global_sync = optc1_program_global_sync, 308 .enable_crtc = optc32_enable_crtc, 309 .disable_crtc = optc32_disable_crtc, 310 .phantom_crtc_post_enable = optc32_phantom_crtc_post_enable, 311 .disable_phantom_crtc = optc32_disable_phantom_otg, 312 /* used by enable_timing_synchronization. Not need for FPGA */ 313 .is_counter_moving = optc1_is_counter_moving, 314 .get_position = optc1_get_position, 315 .get_frame_count = optc1_get_vblank_counter, 316 .get_scanoutpos = optc1_get_crtc_scanoutpos, 317 .get_otg_active_size = optc1_get_otg_active_size, 318 .set_early_control = optc1_set_early_control, 319 /* used by enable_timing_synchronization. Not need for FPGA */ 320 .wait_for_state = optc1_wait_for_state, 321 .set_blank_color = optc3_program_blank_color, 322 .did_triggered_reset_occur = optc1_did_triggered_reset_occur, 323 .triplebuffer_lock = optc3_triplebuffer_lock, 324 .triplebuffer_unlock = optc2_triplebuffer_unlock, 325 .enable_reset_trigger = optc1_enable_reset_trigger, 326 .enable_crtc_reset = optc1_enable_crtc_reset, 327 .disable_reset_trigger = optc1_disable_reset_trigger, 328 .lock = optc3_lock, 329 .unlock = optc1_unlock, 330 .lock_doublebuffer_enable = optc3_lock_doublebuffer_enable, 331 .lock_doublebuffer_disable = optc3_lock_doublebuffer_disable, 332 .enable_optc_clock = optc1_enable_optc_clock, 333 .set_drr = optc32_set_drr, 334 .get_last_used_drr_vtotal = optc2_get_last_used_drr_vtotal, 335 .set_vtotal_min_max = optc3_set_vtotal_min_max, 336 .set_static_screen_control = optc1_set_static_screen_control, 337 .program_stereo = optc1_program_stereo, 338 .is_stereo_left_eye = optc1_is_stereo_left_eye, 339 .tg_init = optc3_tg_init, 340 .is_tg_enabled = optc1_is_tg_enabled, 341 .is_optc_underflow_occurred = optc1_is_optc_underflow_occurred, 342 .clear_optc_underflow = optc1_clear_optc_underflow, 343 .setup_global_swap_lock = NULL, 344 .get_crc = optc1_get_crc, 345 .configure_crc = optc1_configure_crc, 346 .set_dsc_config = optc3_set_dsc_config, 347 .get_dsc_status = optc2_get_dsc_status, 348 .set_dwb_source = NULL, 349 .set_odm_bypass = optc32_set_odm_bypass, 350 .set_odm_combine = optc32_set_odm_combine, 351 .get_odm_combine_segments = optc32_get_odm_combine_segments, 352 .wait_odm_doublebuffer_pending_clear = optc32_wait_odm_doublebuffer_pending_clear, 353 .set_h_timing_div_manual_mode = optc32_set_h_timing_div_manual_mode, 354 .get_optc_source = optc2_get_optc_source, 355 .set_out_mux = optc3_set_out_mux, 356 .set_drr_trigger_window = optc3_set_drr_trigger_window, 357 .set_vtotal_change_limit = optc3_set_vtotal_change_limit, 358 .set_gsl = optc2_set_gsl, 359 .set_gsl_source_select = optc2_set_gsl_source_select, 360 .set_vtg_params = optc1_set_vtg_params, 361 .program_manual_trigger = optc2_program_manual_trigger, 362 .setup_manual_trigger = optc2_setup_manual_trigger, 363 .get_hw_timing = optc1_get_hw_timing, 364}; 365 366void dcn32_timing_generator_init(struct optc *optc1) 367{ 368 optc1->base.funcs = &dcn32_tg_funcs; 369 370 optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1; 371 optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1; 372 373 optc1->min_h_blank = 32; 374 optc1->min_v_blank = 3; 375 optc1->min_v_blank_interlace = 5; 376 optc1->min_h_sync_width = 4; 377 optc1->min_v_sync_width = 1; 378} 379 380