#
a3a4c0b1 |
|
21-Mar-2024 |
shaoyunl <shaoyun.liu@amd.com> |
drm/amdgpu : Add mes_log_enable to control mes log feature The MES log might slow down the performance for extra step of log the data, disable it by default and introduce a parameter can enable it when necessary Signed-off-by: shaoyunl <shaoyun.liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
959143da |
|
27-Feb-2024 |
Alex Deucher <alexander.deucher@amd.com> |
Revert "drm/amd: Remove freesync video mode amdgpu parameter" This reverts commit e94e787e37b99645e7c02d20d0a1ba0f8a18a82a. This conflicts with how compositors want to handle VRR. Now that compositors actually handle VRR, we probably don't need freesync video. Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/2985 Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
81528254 |
|
29-Oct-2023 |
Likun Gao <Likun.Gao@amd.com> |
drm/amdgpu: add psp_timeout to limit PSP related operation Add a new parameter psp_timeout to limit psp related operation to unify the timeout limition for psp. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
226db360 |
|
07-Feb-2024 |
Mario Limonciello <mario.limonciello@amd.com> |
drm/amd: Stop evicting resources on APUs in suspend commit 5095d5418193 ("drm/amd: Evict resources during PM ops prepare() callback") intentionally moved the eviction of resources to earlier in the suspend process, but this introduced a subtle change that it occurs before adev->in_s0ix or adev->in_s3 are set. This meant that APUs actually started to evict resources at suspend time as well. Explicitly set s0ix or s3 in the prepare() stage, and unset them if the prepare() stage failed. v2: squash in warning fix from Stephen Rothwell Reported-by: Jürg Billeter <j@bitron.ch> Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/3132#note_2271038 Fixes: 5095d5418193 ("drm/amd: Evict resources during PM ops prepare() callback") Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
040fdcde |
|
09-Feb-2024 |
Hamza Mahfooz <hamza.mahfooz@amd.com> |
drm/amdgpu: respect the abmlevel module parameter value if it is set Currently, if the abmlevel module parameter is set, it is possible for user space to override the ABM level at some point after boot. However, that is undesirable because it means that we aren't respecting the user's wishes with regard to the level that they want to use. So, prevent user space from changing the ABM level if the module parameter is set to a non-auto value. Tested-by: Mario Limonciello <mario.limonciello@amd.com> Reviewed-by: Mario Limonciello <mario.limonciello@amd.com> Signed-off-by: Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
fc184dbe |
|
08-Feb-2024 |
Hamza Mahfooz <hamza.mahfooz@amd.com> |
drm/amdgpu: make damage clips support configurable We have observed that there are quite a number of PSR-SU panels on the market that are unable to keep up with what user space throws at them, resulting in hangs and random black screens. So, make damage clips support configurable and disable it by default for PSR-SU displays. Cc: stable@vger.kernel.org Reviewed-by: Mario Limonciello <mario.limonciello@amd.com> Signed-off-by: Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
0326de4c |
|
16-Jan-2024 |
Prike Liang <Prike.Liang@amd.com> |
drm/amdgpu: skip to program GFXDEC registers for suspend abort In the suspend abort cases, the gfx power rail doesn't turn off so some GFXDEC registers/CSB can't reset to default value and at this moment reinitialize GFXDEC/CSB will result in an unexpected error. So let skip those program sequence for the suspend abort case. Signed-off-by: Prike Liang <Prike.Liang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
762343f7 |
|
10-Jan-2024 |
chenxuebing <chenxb_99091@126.com> |
drm/amdgpu: Clean up errors in amdgpu.h Fix the following errors reported by checkpatch: ERROR: open brace '{' following struct go on the same line Signed-off-by: chenxuebing <chenxb_99091@126.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
cce4febb |
|
02-Jan-2024 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu: Add ras helper to query boot errors v2 Add ras helper function to query boot time gpu errors. v2: use aqua_vanjaram smn addressing pattern Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Yang Wang <kevinyang.wang@amd.com> Reviewed-by: Le Ma <le.ma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
f5e4cc84 |
|
12-Nov-2023 |
Yang Wang <kevinyang.wang@amd.com> |
drm/amdgpu: implement RAS ACA driver framework v1: implement new RAS ACA driver code framework. v2: - rename aca_bank_set to aca_banks. - rename aca_source_xxx to aca_handle_xxx. v3: Optimize some function implementation details. (from Hawking's suggestion) Signed-off-by: Yang Wang <kevinyang.wang@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
3a9626c8 |
|
07-Feb-2024 |
Mario Limonciello <mario.limonciello@amd.com> |
drm/amd: Stop evicting resources on APUs in suspend commit 5095d5418193 ("drm/amd: Evict resources during PM ops prepare() callback") intentionally moved the eviction of resources to earlier in the suspend process, but this introduced a subtle change that it occurs before adev->in_s0ix or adev->in_s3 are set. This meant that APUs actually started to evict resources at suspend time as well. Explicitly set s0ix or s3 in the prepare() stage, and unset them if the prepare() stage failed. v2: squash in warning fix from Stephen Rothwell Reported-by: Jürg Billeter <j@bitron.ch> Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/3132#note_2271038 Fixes: 5095d5418193 ("drm/amd: Evict resources during PM ops prepare() callback") Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
d16df040 |
|
08-Feb-2024 |
Hamza Mahfooz <hamza.mahfooz@amd.com> |
drm/amdgpu: make damage clips support configurable We have observed that there are quite a number of PSR-SU panels on the market that are unable to keep up with what user space throws at them, resulting in hangs and random black screens. So, make damage clips support configurable and disable it by default for PSR-SU displays. Cc: stable@vger.kernel.org Reviewed-by: Mario Limonciello <mario.limonciello@amd.com> Signed-off-by: Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
93bafa32 |
|
16-Jan-2024 |
Prike Liang <Prike.Liang@amd.com> |
drm/amdgpu: skip to program GFXDEC registers for suspend abort In the suspend abort cases, the gfx power rail doesn't turn off so some GFXDEC registers/CSB can't reset to default value and at this moment reinitialize GFXDEC/CSB will result in an unexpected error. So let skip those program sequence for the suspend abort case. Signed-off-by: Prike Liang <Prike.Liang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
d20e1aec |
|
09-Jan-2024 |
Le Ma <le.ma@amd.com> |
drm/amdgpu: add debug flag to place fw bo on vram for frontdoor loading Use debug_mask=0x8 param to help isolating data path issues on new systems in early phase. v2: rename the flag for explicitness (lijo) Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
6c5683bd |
|
08-Jan-2024 |
Le Ma <le.ma@amd.com> |
Revert "drm/amdgpu: add param to specify fw bo location for front-door loading" This reverts commit c572abffe9f50c8ba33060865449313b3f588c35. Will use debug module param instead of independent module param. Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
c572abff |
|
03-Jan-2024 |
Le Ma <le.ma@amd.com> |
drm/amdgpu: add param to specify fw bo location for front-door loading This param can help isolating data path issues on new systems in early phase. Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
91963397 |
|
01-Dec-2023 |
Friedrich Vock <friedrich.vock@gmx.de> |
drm/amdgpu: Enable tunneling on high-priority compute queues This improves latency if the GPU is already busy with other work. This is useful for VR compositors that submit highly latency-sensitive compositing work on high-priority compute queues while the GPU is busy rendering the next frame. Userspace merge request: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26462 v2: bump driver version (Alex) Reviewed-by: Marek Olšák <marek.olsak@amd.com> Signed-off-by: Friedrich Vock <friedrich.vock@gmx.de> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
b8b39de6 |
|
11-Dec-2023 |
Evan Quan <quanliangl@hotmail.com> |
drm/amd/pm: setup the framework to support Wifi RFI mitigation feature With WBRF feature supported, as a driver responding to the frequencies, amdgpu driver is able to do shadow pstate switching to mitigate possible interference(between its (G-)DDR memory clocks and local radio module frequency bands used by Wifi 6/6e/7). -- v1->v2: - update the prompt for feature support(Lijo) v8->v9: - update parameter document for smu_wbrf_event_handler(Simon) v9->v10: v10->v11: - correct the logics for wbrf range sorting(Lijo) v13: - Fix the format issue (IIpo Jarvinen) Signed-off-by: Evan Quan <quanliangl@hotmail.com> Reviewed-by: Mario Limonciello <mario.limonciello@amd.com> Signed-off-by: Ma Jun <Jun.Ma2@amd.com> Signed-off-by: Ma Jun <Jun.Ma2@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
9a5095e7 |
|
12-Sep-2023 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: add amdgpu_reg_state.h This header defines the reg state structures exposed via sysfs for umr debugging. v2: add content type Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
|
#
613ecd65 |
|
09-Nov-2023 |
André Almeida <andrealmeid@igalia.com> |
drm/amd: Document device reset methods Document what each amdgpu driver reset method does. Signed-off-by: André Almeida <andrealmeid@igalia.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
c8031019 |
|
10-Oct-2023 |
Arunpravin Paneer Selvam <Arunpravin.PaneerSelvam@amd.com> |
drm/amdgpu: Implement a new 64bit sequence memory driver Developed a new driver which allocates a 64bit memory on each request in sequence order. At the moment, user queue fence memory is the main consumer of this seq64 driver. v2: Worked on review comments from Christian for the following modifications - Move driver name from "semaphore" to "seq64" - Remove unnecessary PT/PD mapping - Move enable_mes check into init/fini functions. v3: Worked on review comments from Christian - drop enable_mes check - use DECLARE_BITMAP for bit array - added kerneldoc for seq64 v4: Worked on review comments from Christian - Rename amdgpu_seq64_get name with amdgpu_seq64_alloc v5: Worked on review comments from Christian - Fix seq64 lockdep warning - move fpriv->seq64_va check into amdgpu_seq64_unmap() - make the function amdgpu_seq64_unmap() return as void. - reserve the buffers as not interruptible. v6: port to drm_exec (Alex) v7: disable for now (Arun) Signed-off-by: Arunpravin Paneer Selvam <Arunpravin.PaneerSelvam@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
6ba5b613 |
|
09-Nov-2023 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: add a module parameter to control the AGP aperture Add a module parameter to control the AGP aperture. The AGP aperture is an aperture in the GPU's internal address space which provides direct non-paged access to the platform address space. This access is non-snooped so only uncached memory can be accessed. Add a knob so that we can toggle this for debugging. Fixes: 67318cb84341 ("drm/amdgpu/gmc11: set gart placement GC11") Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Mario Limonciello <mario.limonciello@amd.com> Tested-by: Mario Limonciello <mario.limonciello@amd.com> # PHX & Navi33 Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
85150626 |
|
03-Oct-2023 |
Victor Lu <victorchengchi.lu@amd.com> |
drm/amdgpu: Use correct KIQ MEC engine for gfx9.4.3 (v5) amdgpu_kiq_wreg/rreg is hardcoded to use MEC engine 0. Add an xcc_id parameter to amdgpu_kiq_wreg/rreg, define W/RREG32_XCC and amdgpu_device_xcc_wreg/rreg to use the new xcc_id parameter. Using amdgpu_sriov_runtime to determine whether to access via kiq or RLC is sufficient for now. v5: add condition in amdgpu_device_xcc_w/rreg, remove trace func call v4: avoid using amdgpu_sriov_w/rreg v3: use W/RREG32_XCC to handle non-kiq case v2: define amdgpu_device_xcc_wreg/rreg instead of changing parameters of amdgpu_device_wreg/rreg Signed-off-by: Victor Lu <victorchengchi.lu@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
2bfb0ca3 |
|
30-Oct-2023 |
Yang Wang <kevinyang.wang@amd.com> |
drm/amdgpu: remove unused macro HW_REV remove unused macro HW_REV Signed-off-by: Yang Wang <kevinyang.wang@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
2757a848 |
|
23-Oct-2023 |
Mario Limonciello <mario.limonciello@amd.com> |
drm/amd: Explicitly disable ASPM when dynamic switching disabled Currently there are separate but related checks: * amdgpu_device_should_use_aspm() * amdgpu_device_aspm_support_quirk() * amdgpu_device_pcie_dynamic_switching_supported() Simplify into checking whether DPM was enabled or not in the auto case. This works because amdgpu_device_pcie_dynamic_switching_supported() populates that value. Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
8eece69a |
|
12-Oct-2023 |
Lijo Lazar <lijo.lazar@amd.com> |
drm/amdgpu: Add API to get full IP version Fetch the full version of IP including variant and subrevision. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Le Ma <le.ma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
69619868 |
|
15-Sep-2023 |
André Almeida <andrealmeid@igalia.com> |
drm/amdgpu: Move coredump code to amdgpu_reset file Giving that we use codedump just for device resets, move it's functions and structs to a more semantic file, the amdgpu_reset.{c, h}. Signed-off-by: André Almeida <andrealmeid@igalia.com> Signed-off-by: Shashank Sharma <shashank.sharma@amd.com> Reviewed-by: Shashank Sharma <shashank.sharma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
2d6a2a28 |
|
15-Sep-2023 |
André Almeida <andrealmeid@igalia.com> |
drm/amdgpu: Encapsulate all device reset info To better organize struct amdgpu_device, keep all reset information related fields together in a separated struct. Signed-off-by: André Almeida <andrealmeid@igalia.com> Signed-off-by: Shashank Sharma <shashank.sharma@amd.com> Reviewed-by: Shashank Sharma <shashank.sharma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
5095d5418 |
|
06-Oct-2023 |
Mario Limonciello <mario.limonciello@amd.com> |
drm/amd: Evict resources during PM ops prepare() callback Linux PM core has a prepare() callback run before suspend. If the system is under high memory pressure, the resources may need to be evicted into swap instead. If the storage backing for swap is offlined during the suspend() step then such a call may fail. So move this step into prepare() to move evict majority of resources and update all non-pmops callers to call the same callback. Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2362 Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
8a2b5139 |
|
04-Oct-2023 |
Lijo Lazar <lijo.lazar@amd.com> |
drm/amdgpu: Refactor FRU product information Keep FRU related information together in a separate structure. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
2b6b29f3 |
|
30-Sep-2023 |
Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> |
drm/amdgpu: Fix complex macros error Fixes the below: ERROR: Macros with complex values should be enclosed in parentheses WARNING: macros should not use a trailing semicolon +#define amdgpu_inc_vram_lost(adev) atomic_inc(&((adev)->vram_lost_counter)); Cc: Christian König <christian.koenig@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: "Pan, Xinhui" <Xinhui.Pan@amd.com> Signed-off-by: Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
b8e6aec1 |
|
29-Sep-2023 |
Mario Limonciello <mario.limonciello@amd.com> |
drm/amd: Drop all hand-built MIN and MAX macros in the amdgpu base driver Several files declare MIN() or MAX() macros that ignore the types of the values being compared. Drop these macros and switch to min() min_t(), and max() from `linux/minmax.h`. Suggested-by: Hamza Mahfooz <Hamza.Mahfooz@amd.com> Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
ff96ddc3 |
|
11-Sep-2023 |
Lijo Lazar <lijo.lazar@amd.com> |
drm/amdgpu: Add more fields to IP version Include subrevision and variant fileds also to IP version. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
a7691785 |
|
15-Sep-2023 |
André Almeida <andrealmeid@igalia.com> |
drm/amdgpu: Rework coredump to use memory dynamically Instead of storing coredump information inside amdgpu_device struct, move if to a proper separated struct and allocate it dynamically. This will make it easier to further expand the logged information. Signed-off-by: André Almeida <andrealmeid@igalia.com> Reviewed-by: Shashank Sharma <shashank.sharma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
5dc270d3 |
|
05-Sep-2023 |
Mario Limonciello <mario.limonciello@amd.com> |
drm/amd: Add a module parameter for seamless boot The module parameter can be used to test more easily enabling seamless boot support on additional ASICs. Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
bb0f8429 |
|
05-Sep-2023 |
Mario Limonciello <mario.limonciello@amd.com> |
drm/amd: Move seamless boot check out of display This will allow base driver to dictate whether seamless should be enabled. No intended functional changes. Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
4e8303cf |
|
11-Sep-2023 |
Lijo Lazar <lijo.lazar@amd.com> |
drm/amdgpu: Use function for IP version check Use an inline function for version check. Gives more flexibility to handle any format changes. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
ffde7210 |
|
11-Sep-2023 |
André Almeida <andrealmeid@igalia.com> |
drm/amdgpu: Create an option to disable soft recovery Create a module option to disable soft recoveries on amdgpu, making every recovery go through the device reset path. This option makes easier to force device resets for testing and debugging purposes. Signed-off-by: André Almeida <andrealmeid@igalia.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
887db1e4 |
|
11-Sep-2023 |
André Almeida <andrealmeid@igalia.com> |
drm/amdgpu: Merge debug module parameters Merge all developer debug options available as separated module parameters in one, making it obvious that are for developers. Drop the obsolete module options in favor of the new ones. Signed-off-by: André Almeida <andrealmeid@igalia.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
601c63ad |
|
08-Sep-2023 |
Hamza Mahfooz <hamza.mahfooz@amd.com> |
Revert "drm/amd: Disable S/G for APUs when 64GB or more host memory" This reverts commit 70e64c4d522b732e31c6475a3be2349de337d321. Since, we now have an actual fix for this issue, we can get rid of this workaround as it can cause pin failures if enough VRAM isn't carved out by the BIOS. Cc: stable@vger.kernel.org # 6.1+ Acked-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
a76b2870 |
|
16-May-2023 |
Candice Li <candice.li@amd.com> |
drm/amdgpu: Add RREG64_PCIE_EXT/WREG64_PCIE_EXT functions Add 64bits register access support on register whose address is greater than 32bits. Signed-off-by: Candice Li <candice.li@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
eebb06d1 |
|
03-Jun-2023 |
Lang Yu <Lang.Yu@amd.com> |
drm/amdgpu: add amdgpu_umsch_mm module parameter Enable Multi Media User Mode Scheduler (0 = disabled (default), 1 = enabled). Signed-off-by: Lang Yu <Lang.Yu@amd.com> Acked-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Veerabadhran Gopalakrishnan <Veerabadhran.Gopalakrishnan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
3488c79b |
|
10-May-2023 |
Lang Yu <Lang.Yu@amd.com> |
drm/amdgpu: add initial support for UMSCH Add basic data structure, dummy ring functions and ip functions for UMSCH. Implement sw_init(ring_init and init_microcodede) and hw_init(load_microcode), UMSCH can boot up now. Implement hw_init(ring_start) and hw_fini(ring_stop), UMSCH is ready for command submission now. Implement set_hw_resources and add/remove_queue, UMSCH is ready for scheduling now. Aggregated doorbell is used to notify UMSCH FW that there is unmapped queue with corresponding priority level (e.g., AGDB[0] for Real time band, etc.) is updating its job. v2: squash together initial patches to avoid breaking the build (Alex) Signed-off-by: Lang Yu <Lang.Yu@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Veerabadhran Gopalakrishnan <Veerabadhran.Gopalakrishnan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
9d4346bd |
|
22-May-2022 |
Lang Yu <Lang.Yu@amd.com> |
drm/amdgpu: add VPE 6.1.0 support Add skeleton driver code. (Ray) Add initial support for Video Processing Engine. (Lang) Signed-off-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Lang Yu <Lang.Yu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
5b28f1c7 |
|
24-Apr-2022 |
Huang Rui <ray.huang@amd.com> |
drm/amdgpu: add VPE HW IP BLOCK definition Add HW IP BLOCK for Video Processing Engine. Signed-off-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
169ed4ec |
|
08-Sep-2023 |
Hamza Mahfooz <hamza.mahfooz@amd.com> |
Revert "drm/amd: Disable S/G for APUs when 64GB or more host memory" This reverts commit 70e64c4d522b732e31c6475a3be2349de337d321. Since, we now have an actual fix for this issue, we can get rid of this workaround as it can cause pin failures if enough VRAM isn't carved out by the BIOS. Cc: stable@vger.kernel.org # 6.1+ Acked-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
e94e787e |
|
22-Mar-2023 |
Aurabindo Pillai <aurabindo.pillai@amd.com> |
drm/amd: Remove freesync video mode amdgpu parameter [Why&How] Freesync Video mode was enabled by default. Hence no need for the module parameter, so remove it completely Acked-by: Stylon Wang <stylon.wang@amd.com> Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Reviewed-by: Stylon Wang <stylon.wang@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
70e64c4d |
|
27-Jul-2023 |
Mario Limonciello <mario.limonciello@amd.com> |
drm/amd: Disable S/G for APUs when 64GB or more host memory Users report a white flickering screen on multiple systems that is tied to having 64GB or more memory. When S/G is enabled pages will get pinned to both VRAM carve out and system RAM leading to this. Until it can be fixed properly, disable S/G when 64GB of memory or more is detected. This will force pages to be pinned into VRAM. This should fix white screen flickers but if VRAM pressure is encountered may lead to black screens. It's a trade-off for now. Fixes: 81d0bcf99009 ("drm/amdgpu: make display pinning more flexible (v2)") Cc: Hamza Mahfooz <Hamza.Mahfooz@amd.com> Cc: Roman Li <roman.li@amd.com> Cc: <stable@vger.kernel.org> # 6.1.y: bf0207e172703 ("drm/amdgpu: add S/G display parameter") Cc: <stable@vger.kernel.org> # 6.4.y Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2735 Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2354 Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
f9acfafc |
|
24-Jul-2023 |
Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> |
drm/amdgpu: Move externs to amdgpu.h file from amdgpu_drv.c Fixes the following: WARNING: externs should be avoided in .c files +extern const struct attribute_group amdgpu_vram_mgr_attr_group; WARNING: externs should be avoided in .c files +extern const struct attribute_group amdgpu_gtt_mgr_attr_group; WARNING: externs should be avoided in .c files +extern const struct attribute_group amdgpu_flash_attr_group; And other style fixes: WARNING: Block comments should align the * on each line WARNING: void function return statements are not generally useful WARNING: braces {} are not necessary for single statement blocks Cc: Christian König <christian.koenig@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Reviewed-by: Guchun Chen <guchun.chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
8ed49dd1 |
|
16-Jun-2023 |
Victor Lu <victorchengchi.lu@amd.com> |
drm/amdgpu: Add RLCG interface driver implementation for gfx v9.4.3 (v3) Add RLCG interface support for gfx v9.4.3 and multiple XCCs. Do not enable it yet. v2: Fix amdgpu_rlcg_reg_access_ctrl init, add support for multiple XCCs in amdgpu_mm_wreg_mmio_rlc v3: Use GET_INST() when indexing amdgpu_rlcg_reg_access_ctrl Signed-off-by: Victor Lu <victorchengchi.lu@amd.com> Reviewed-by: Zhigang Luo <zhigang.luo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
5d1eb4c4 |
|
07-Jul-2023 |
Mario Limonciello <mario.limonciello@amd.com> |
drm/amd: Move helper for dynamic speed switch check out of smu13 This helper is used for checking if the connected host supports the feature, it can be moved into generic code to be used by other smu implementations as well. Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
ca6c1e21 |
|
16-Apr-2022 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: use the new drm_exec object for CS v3 Use the new component here as well and remove the old handling. v2: drop dupplicate handling v3: fix memory leak pointed out by Tatsuyuki Signed-off-by: Christian König <christian.koenig@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230711133122.3710-7-christian.koenig@amd.com
|
#
521289d2 |
|
26-Jun-2023 |
Mario Limonciello <mario.limonciello@amd.com> |
drm/amd: Use attribute groups for PSP flashing attributes Individually creating attributes can be racy, instead make attributes using attribute groups and control their visibility with an is_visible callback to only show when using appropriate products. v2: squash in fix for PSP 13.0.10 Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
08fffa74 |
|
27-Jul-2023 |
Mario Limonciello <mario.limonciello@amd.com> |
drm/amd: Disable S/G for APUs when 64GB or more host memory Users report a white flickering screen on multiple systems that is tied to having 64GB or more memory. When S/G is enabled pages will get pinned to both VRAM carve out and system RAM leading to this. Until it can be fixed properly, disable S/G when 64GB of memory or more is detected. This will force pages to be pinned into VRAM. This should fix white screen flickers but if VRAM pressure is encountered may lead to black screens. It's a trade-off for now. Fixes: 81d0bcf99009 ("drm/amdgpu: make display pinning more flexible (v2)") Cc: Hamza Mahfooz <Hamza.Mahfooz@amd.com> Cc: Roman Li <roman.li@amd.com> Cc: <stable@vger.kernel.org> # 6.1.y: bf0207e172703 ("drm/amdgpu: add S/G display parameter") Cc: <stable@vger.kernel.org> # 6.4.y Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2735 Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2354 Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
18862307 |
|
07-Jul-2023 |
Mario Limonciello <mario.limonciello@amd.com> |
drm/amd: Move helper for dynamic speed switch check out of smu13 This helper is used for checking if the connected host supports the feature, it can be moved into generic code to be used by other smu implementations as well. Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org # 6.1.x
|
#
b75efe88 |
|
04-May-2023 |
Evan Quan <evan.quan@amd.com> |
drm/amd/pm: avoid unintentional shutdown due to temperature momentary fluctuation An intentional delay is added on soft ctf triggered. Then there will be a double check for the GPU temperature before taking further action. This can avoid unintended shutdown due to temperature momentary fluctuation. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
b579ea63 |
|
15-Jun-2023 |
Lijo Lazar <lijo.lazar@amd.com> |
drm/amdgpu: Modify for_each_inst macro Modify it such that it doesn't change the instance mask parameter. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Acked-by: Victor Skvortsov <victor.skvortsov@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
80e709ee |
|
07-Jun-2023 |
Chong Li <chongli2@amd.com> |
drm/amdgpu: add option params to enforce process isolation between graphics and compute enforce process isolation between graphics and compute via using the same reserved vmid. v2: remove params "struct amdgpu_vm *vm" from amdgpu_vmid_alloc_reserved and amdgpu_vmid_free_reserved. Signed-off-by: Chong Li <chongli2@amd.com> Reviewed-by: Christian Koenig <Christian.Koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
01f64820 |
|
30-Mar-2022 |
Jonathan Kim <jonathan.kim@amd.com> |
drm/amdgpu: add gfx9.4.1 hw debug mode enable and disable calls On GFX9.4.1, the implicit wait count instruction on s_barrier is disabled by default in the driver during normal operation for performance requirements. There is a hardware bug in GFX9.4.1 where if the implicit wait count instruction after an s_barrier instruction is disabled, any wave that hits an exception may step over the s_barrier when returning from the trap handler with the barrier logic having no ability to be aware of this, thereby causing other waves to wait at the barrier indefinitely resulting in a shader hang. This bug has been corrected for GFX9.4.2 and onward. Since the debugger subscribes to hardware exceptions, in order to avoid this bug, the debugger must enable implicit wait count on s_barrier for a debug session and disable it on detach. In order to change this setting in the in the device global SQ_CONFIG register, the GFX pipeline must be idle. GFX9.4.1 as a compute device will either dispatch work through the compute ring buffers used for image post processing or through the hardware scheduler by the KFD. Have the KGD suspend and drain the compute ring buffer, then suspend the hardware scheduler and block any future KFD process job requests before changing the implicit wait count setting. Once set, resume all work. Signed-off-by: Jonathan Kim <jonathan.kim@amd.com> Reviewed-by: Felix Kuehling <felix.kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
b336c681 |
|
19-May-2023 |
Likun Gao <Likun.Gao@amd.com> |
drm/amdgpu: fix vga_set_state NULL pointer issue Fix NULL pointer issue for vga_set_state function as not all the ASIC need this operation. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
af2ba368 |
|
27-Feb-2023 |
Tao Zhou <tao.zhou1@amd.com> |
drm/amdgpu: convert logical instance mask to physical one Convert instance mask for the convenience of RAS TA. Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Stanley.Yang <Stanley.Yang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
be3800f5 |
|
28-Feb-2023 |
James Zhu <James.Zhu@amd.com> |
drm/amdgpu: find partition ID when open device Find partition ID when open device from render device minor. Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-and-tested-by: Philip Yang<Philip.Yang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
2c1c7ba4 |
|
15-Aug-2022 |
James Zhu <James.Zhu@amd.com> |
drm/amdgpu: support partition drm devices Support partition drm devices on GC_HWIP IP_VERSION(9, 4, 3). This is a temporary solution and will be superceded. Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-and-tested-by: Philip Yang<Philip.Yang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
76eb9c95 |
|
27-Feb-2023 |
David Francis <David.Francis@amd.com> |
drm/amdgpu/bu: add mtype_local as a module parameter Selects the MTYPE to be used for local memory, (0 = MTYPE_CC (default), 1 = MTYPE_NC, 2 = MTYPE_RW) v2: squash in build fix (Alex) Reviewed-by: Graham Sider <Graham.Sider@amd.com> Signed-off-by: David Francis <David.Francis@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
895797d9 |
|
06-Feb-2023 |
Graham Sider <Graham.Sider@amd.com> |
drm/amdgpu/bu: Add use_mtype_cc_wa module param By default, set use_mtype_cc_wa to 1 to set PTE coherence flag MTYPE_CC instead of MTYPE_RW by default. This is required for the time being to mitigate a bug causing XCCs to hit stale data due to TCC marking fully dirty lines as exclusive. Signed-off-by: Graham Sider <Graham.Sider@amd.com> Reviewed-by: Joseph Greathouse <Joseph.Greathouse@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
570de94b |
|
13-Feb-2023 |
Lijo Lazar <lijo.lazar@amd.com> |
drm/amdgpu: Add auto mode for compute partition When auto mode is specified, driver will choose the right compute partition mode. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Le Ma <le.ma@amd.com> Reviewed-by: Philip Yang <philip.yang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
fa0497c3 |
|
14-Feb-2023 |
Lijo Lazar <lijo.lazar@amd.com> |
drm/amdgpu: Add API to get numa information of XCC Add interface to get numa information of ACPI XCC object. The interface uses logical id to identify an XCC. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Le Ma <le.ma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
6e018822 |
|
27-Jan-2023 |
Lijo Lazar <lijo.lazar@amd.com> |
drm/amdgpu: Add API to get tmr info from acpi In certain configs, TMR information is available from ACPI. Add API to fetch the information. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
4d5275ab |
|
27-Jan-2023 |
Lijo Lazar <lijo.lazar@amd.com> |
drm/amdgpu: Add parsing of acpi xcc objects Add parsing of ACPI xcc objects and fill in relevant info from them by invoking the DSM methods. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-and-tested-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
9e4216cf |
|
05-May-2023 |
Mukul Joshi <mukul.joshi@amd.com> |
drm/amdgpu: Increase Max GPU instance to 64 Increase Max GPU instances to 64 to handle multi-socket system with GFX 9.4.3 asic. Signed-off-by: Mukul Joshi <mukul.joshi@amd.com> Acked-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
7a1efad0 |
|
29-Nov-2022 |
Lijo Lazar <lijo.lazar@amd.com> |
drm/amdgpu: Use mask for active clusters Use a mask of available active clusters instead of using only the number of active clusters. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
75d16923 |
|
15-Sep-2022 |
Lijo Lazar <lijo.lazar@amd.com> |
drm/amdgpu: Add initial version of XCP routines Within a device, an accelerator core partition can be constituted with different IP instances. These partitions are spatial in nature. Number of partitions which can exist at the same time depends on the 'partition mode'. Add a manager entity which is responsible for switching between different partition modes and maintaining partitions. It is also responsible for suspend/resume of different partitions. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
dd1a02e2 |
|
13-Sep-2022 |
Lijo Lazar <lijo.lazar@amd.com> |
drm/amdgpu: Add xcc specific functions for gfxhub GFXHUB 1.2 supports multiple XCC instances. Add XCC specific functions to handle XCC instances separately. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
2fa480d3 |
|
27-Sep-2022 |
Le Ma <le.ma@amd.com> |
drm/amdgpu: add helpers to access registers on different AIDs SMN address which is larger than 32bit has different indications through bit[34:32] on different AIDs. v2: put smn addressing of different AIDs into asic specific place v3: change to ext_id/ext_offset naming Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
7e0eebdc |
|
14-Sep-2022 |
Le Ma <le.ma@amd.com> |
drm/amdgpu: extend max instances Number of instances is extended. Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
5d30cbb4 |
|
29-Jun-2022 |
Lijo Lazar <lijo.lazar@amd.com> |
drm/amdgpu: Add map of logical to physical inst Add a map for logical to physical instances of an IP. For ex: on some device configurations, the first logical XCC may not be the first physical XCC. Software may continue to access in logical IP instance order. The map provides a convenient way to get to the actual physical instance. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Le Ma <Le.Ma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
0c552ed3 |
|
02-Apr-2022 |
Le Ma <le.ma@amd.com> |
drm/amdgpu: add indirect r/w interface for smn address greater than 32bits On multiple AIDs platform, bit[34:32] in SMD address is leveraged to access nonAID0 register smn address and new PCI_INDEX_HI register is introduced to access the higher bits. v2: rebase on latest register accessors (Alex) Signed-off-by: Le Ma <le.ma@amd.com> Acked-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
386ea27c |
|
22-Feb-2022 |
Le Ma <le.ma@amd.com> |
drm/amdgpu: adjust some basic elements for multiple AID case add some elements below: - num_aid - aid_id for each sdma instance - num_inst_per_aid for sdma and extend macro size below: - SDMA_MAX_INSTANCES to 16 - AMDGPU_MAX_RINGS to 96 - AMDGPU_MAX_HWIP_RINGS to 32 v2: move aid_id from amdgpu_ring to amdgpu_sdma_instance. (Lijo) Signed-off-by: Le Ma <le.ma@amd.com> Acked-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
81283fee |
|
19-Jan-2022 |
James Zhu <James.Zhu@amd.com> |
drm/amdgpu/: add more macro to support offset variant Add more macro to support offset variant and simplify macro SOC15_WAIT_ON_RREG. Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
0fa49d10 |
|
16-Dec-2021 |
Shiwu Zhang <shiwu.zhang@amd.com> |
drm/amdgpu: override partition mode through module parameter Add a module parameter to override the partition mode. Signed-off-by: Shiwu Zhang <shiwu.zhang@amd.com> Reviewed-by: Le Ma <Le.Ma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
d9426c3d |
|
20-Dec-2021 |
Le Ma <le.ma@amd.com> |
drm/amdgpu: add bitmask to iterate vmhubs As the layout of VMHUB definition has been changed to cover multiple XCD/AID case, the original num_vmhubs is not appropriate to do vmhub iteration any more. Drop num_vmhubs and introduce vmhubs_mask instead. v2: switch to the new VMHUB layout v3: use DECLARE_BITMAP to define vmhubs_mask Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
f1f6f48a |
|
25-Apr-2023 |
Mukul Joshi <mukul.joshi@amd.com> |
drm/amdgpu: Set GTT size equal to TTM mem limit Use the helper function in TTM to get TTM mem limit and set GTT size to be equal to TTL mem limit. Signed-off-by: Mukul Joshi <mukul.joshi@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
541372bb |
|
16-Nov-2021 |
Le Ma <le.ma@amd.com> |
drm/amdgpu: add some basic elements for multiple XCD case Add some basic definitions and structure member. Inscrease MAX_WB slots to 1024 to support the increasing number of rings for multiple partitions. v2: unify naming style Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
418431bc |
|
05-Apr-2023 |
Lijo Lazar <lijo.lazar@amd.com> |
drm/amdgpu: Fix warnings Fix below warning due to incompatible types in conditional operator ../pm/swsmu/smu13/smu_v13_0_6_ppt.c:315:17: sparse: sparse: incompatible types in conditional expression (different base types): Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reported-by: kernel test robot <lkp@intel.com> Reviewed-by: Luben Tuikov <luben.tuikov@amd.com> Reviewed-by: Guchun Chen <guchun.chen@amd.com> Link: https://lore.kernel.org/oe-kbuild-all/202303082135.NjdX1Bij-lkp@intel.com/ Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
11f25c84 |
|
05-Apr-2023 |
Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> |
drm/amd/amdgpu: Drop the hang limit parameter The driver doesn't resubmit jobs on hangs any more, hence drop the hang limit parameter - amdgpu_job_hang_limit, wherever it is used. Suggested-by: Christian König <christian.koenig@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Mario Limonciello <mario.limonciello@amd.com> Cc: Kent Russell <kent.russell@amd.com> Signed-off-by: Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Reviewed-by: Mario Limonciello <mario.limonciello@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
3ad5dcfe |
|
15-Mar-2023 |
Kai-Heng Feng <kai.heng.feng@canonical.com> |
drm/amdgpu/nv: Apply ASPM quirk on Intel ADL + AMD Navi S2idle resume freeze can be observed on Intel ADL + AMD WX5500. This is caused by commit 0064b0ce85bb ("drm/amd/pm: enable ASPM by default"). The root cause is still not clear for now. So extend and apply the ASPM quirk from commit e02fe3bc7aba ("drm/amdgpu: vi: disable ASPM on Intel Alder Lake based systems"), to workaround the issue on Navi cards too. Fixes: 0064b0ce85bb ("drm/amd/pm: enable ASPM by default") Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2458 Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Kai-Heng Feng <kai.heng.feng@canonical.com> Reviewed-by: Mario Limonciello <mario.limonciello@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
d24eae4d |
|
15-Mar-2023 |
Tim Huang <tim.huang@amd.com> |
drm/amdgpu: reposition the gpu reset checking for reuse Move the amdgpu_acpi_should_gpu_reset out of CONFIG_SUSPEND to share it with hibernate case. Signed-off-by: Tim Huang <tim.huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
dabc114e |
|
06-Mar-2023 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu: Move to common helper to query soc rev_id Replace soc15, nv, soc21 get_rev_id callback with common helper so we don't need to duplicate code when introduce new asics. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Likun Gao <Likun.Gao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
65ba96e9 |
|
06-Mar-2023 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu: Move to common indirect reg access helper Replace soc15, nv, soc21 specific callbacks with common one. so we don't need to duplicate code when introduce new asics. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Likun Gao <Likun.Gao@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
53e9d836 |
|
12-Mar-2023 |
Guchun Chen <guchun.chen@amd.com> |
drm/amdgpu: drop pm_sysfs_en flag from amdgpu_device structure pm_sysfs_en is overlapped with pm.sysfs_initialized, so drop it for simplifying code(no functional change). Signed-off-by: Guchun Chen <guchun.chen@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
58265640 |
|
07-Mar-2023 |
Bjorn Helgaas <bhelgaas@google.com> |
drm/amdgpu: Drop redundant pci_enable_pcie_error_reporting() pci_enable_pcie_error_reporting() enables the device to send ERR_* Messages. Since f26e58bf6f54 ("PCI/AER: Enable error reporting when AER is native"), the PCI core does this for all devices during enumeration, so the driver doesn't need to do it itself. Remove the redundant pci_enable_pcie_error_reporting() call from the driver. Note that this only controls ERR_* Messages from the device. An ERR_* Message may cause the Root Port to generate an interrupt, depending on the AER Root Error Command register managed by the AER service driver. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
c103a23f |
|
24-Feb-2023 |
Maarten Lankhorst <maarten.lankhorst@linux.intel.com> |
drm/amd: Convert amdgpu to use suballocation helper. Now that we have a generic suballocation helper, Use it in amdgpu. For lines that get moved or changed, also fix up pre-existing style issues. Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Co-developed-by: Thomas Hellström <thomas.hellstrom@linux.intel.com> Signed-off-by: Thomas Hellström <thomas.hellstrom@linux.intel.com> Reviewed-by: Christian König <christian.koenig@amd.com> Acked-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Acked-by: Christian König <christian.koenig@amd.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230224095152.30134-3-thomas.hellstrom@linux.intel.com
|
#
2b072442 |
|
15-Mar-2023 |
Kai-Heng Feng <kai.heng.feng@canonical.com> |
drm/amdgpu/nv: Apply ASPM quirk on Intel ADL + AMD Navi S2idle resume freeze can be observed on Intel ADL + AMD WX5500. This is caused by commit 0064b0ce85bb ("drm/amd/pm: enable ASPM by default"). The root cause is still not clear for now. So extend and apply the ASPM quirk from commit e02fe3bc7aba ("drm/amdgpu: vi: disable ASPM on Intel Alder Lake based systems"), to workaround the issue on Navi cards too. Fixes: 0064b0ce85bb ("drm/amd/pm: enable ASPM by default") Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2458 Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Kai-Heng Feng <kai.heng.feng@canonical.com> Reviewed-by: Mario Limonciello <mario.limonciello@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
|
#
aaee0ce4 |
|
15-Mar-2023 |
Tim Huang <tim.huang@amd.com> |
drm/amdgpu: reposition the gpu reset checking for reuse Move the amdgpu_acpi_should_gpu_reset out of CONFIG_SUSPEND to share it with hibernate case. Signed-off-by: Tim Huang <tim.huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org # 6.1.x
|
#
bf0207e1 |
|
09-Feb-2023 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: add S/G display parameter Some users have reported flickerng with S/G display. We've tried extensively to reproduce and debug the issue on a wide variety of platform configurations (DRAM bandwidth, etc.) and a variety of monitors, but so far have not been able to. We disabled S/G display on a number of platforms to address this but that leads to failure to pin framebuffers errors and blank displays when there is memory pressure or no displays at all on systems with limited carveout (e.g., Chromebooks). Add a option to disable this as a debugging option as a way for users to disable this, depending on their use case, and for us to help debug this further. v2: fix typo Reviewed-by: Harry Wentland <harry.wentland@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
90f56611 |
|
23-Dec-2022 |
xurui <xurui@kylinos.cn> |
drm/amdgpu: Retry DDC probing on DVI on failure if we got an HPD interrupt HPD signals on DVI ports can be fired off before the pins required for DDC probing actually make contact, due to the pins for HPD making contact first. This results in a HPD signal being asserted but DDC probing failing, resulting in hotplugging occasionally failing. Rescheduling the hotplug work for a second when we run into an HPD signal with a failing DDC probe usually gives enough time for the rest of the connector's pins to make contact, and fixes this issue. Signed-off-by: xurui <xurui@kylinos.cn> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
4243c84a |
|
21-Dec-2022 |
Michel Dänzer <mdaenzer@redhat.com> |
Revert "drm/amd/display: Enable Freesync Video Mode by default" This reverts commit de05abe6b9d0fe08f65d744f7f75a4cba4df27ad. The bug referenced below was bisected to this commit. There has been no activity toward fixing it in 3 months, so let's revert for now. Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/2162 Signed-off-by: Michel Dänzer <mdaenzer@redhat.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
0b04ea39 |
|
01-Feb-2022 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: allow zero as vram limit This allows testing the driver without any VRAM. Signed-off-by: Christian König <christian.koenig@amd.com> Acked-by: Luben Tuikov <luben.tuikov@amd.com> Acked-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
7ccfd79f |
|
21-Jan-2022 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: rename vram_scratch into mem_scratch Rename vram_scratch into mem_scratch and allow allocating it into GTT as well. The only problem with that is that we won't have a default page for the system aperture any more. Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Luben Tuikov <luben.tuikov@amd.com> Acked-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
58ab2c08 |
|
14-Jan-2022 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: use VRAM|GTT for a bunch of kernel allocations Technically all of those can use GTT as well, no need to force things into VRAM. Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Luben Tuikov <luben.tuikov@amd.com> Acked-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
a3185f91 |
|
09-May-2022 |
Christian König <christian.koenig@amd.com> |
drm/ttm: merge ttm_bo_api.h and ttm_bo_driver.h v2 Merge and cleanup the two headers into a single description of the object API. Also move all the documentation to the implementation and drop unnecessary includes from the header. No functional change. v2: minimal checkpatch.pl cleanup Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Arunpravin Paneer Selvam <Arunpravin.PaneerSelvam@amd.com> Link: https://patchwork.freedesktop.org/patch/msgid/20221125102137.1801-4-christian.koenig@amd.com
|
#
4693e852 |
|
09-Feb-2023 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: add S/G display parameter Some users have reported flickerng with S/G display. We've tried extensively to reproduce and debug the issue on a wide variety of platform configurations (DRAM bandwidth, etc.) and a variety of monitors, but so far have not been able to. We disabled S/G display on a number of platforms to address this but that leads to failure to pin framebuffers errors and blank displays when there is memory pressure or no displays at all on systems with limited carveout (e.g., Chromebooks). Add a option to disable this as a debugging option as a way for users to disable this, depending on their use case, and for us to help debug this further. v2: fix typo Reviewed-by: Harry Wentland <harry.wentland@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
6fe6ece3 |
|
21-Dec-2022 |
Michel Dänzer <mdaenzer@redhat.com> |
Revert "drm/amd/display: Enable Freesync Video Mode by default" This reverts commit de05abe6b9d0fe08f65d744f7f75a4cba4df27ad. The bug referenced below was bisected to this commit. There has been no activity toward fixing it in 3 months, so let's revert for now. Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/2162 Signed-off-by: Michel Dänzer <mdaenzer@redhat.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
|
#
d9483ecd |
|
08-Nov-2022 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: rename the files for HMM handling Clean that up a bit, no functional change. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
220c8cc8 |
|
10-Nov-2022 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: there is no vbios fb on devices with no display hw (v2) If we enable virtual display functionality on parts with no display hardware we can end up trying to check for and reserve the vbios FB area on devices where it doesn't exist. Check if display hardware is actually present on the hardware before trying to reserve the memory. v2: move the check into common code Acked-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
d09ef243 |
|
19-Jul-2022 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: clarify DC checks There are several places where we don't want to check if a particular asic could support DC, but rather, if DC is enabled. Set a flag if DC is enabled and check for that rather than if a device supports DC or not. Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
25263da3 |
|
18-Jul-2022 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: rework SR-IOV virtual display handling virtual display is enabled unconditionally in SR-IOV, but without specifying the virtual_display module, the number of crtcs defaults to 0. Set a single display by default for SR-IOV if the virtual_display parameter is not set. Only enable virtual display by default on SR-IOV on asics which actually have display hardware. Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
9a1662f5 |
|
29-Sep-2022 |
Graham Sider <Graham.Sider@amd.com> |
drm/amdgpu: extend halt_if_hws_hang to MES Hang on MES timeout if halt_if_hws_hang is set to 1. Signed-off-by: Graham Sider <Graham.Sider@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
6aa58939 |
|
12-Oct-2022 |
Victor Zhao <Victor.Zhao@amd.com> |
Revert "drm/amdgpu: add debugfs amdgpu_reset_level" This reverts commit 5bd8d53f6fa53eab5433698d1362dae2aa53c1cc. This commit breaks the reset logic for aldebaran, revert it for now. Will move the mask inside the reset handler. Fixes: 5bd8d53f6fa53e ("drm/amdgpu: add debugfs amdgpu_reset_level") Signed-off-by: Victor Zhao <Victor.Zhao@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
7a94c860 |
|
17-May-2022 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu: extend HWIP_MAX_INSTANCE to 28 more ip instances are available Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
f8794f31 |
|
10-Nov-2022 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: there is no vbios fb on devices with no display hw (v2) If we enable virtual display functionality on parts with no display hardware we can end up trying to check for and reserve the vbios FB area on devices where it doesn't exist. Check if display hardware is actually present on the hardware before trying to reserve the memory. v2: move the check into common code Acked-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
afbaa155 |
|
12-Oct-2022 |
Victor Zhao <Victor.Zhao@amd.com> |
Revert "drm/amdgpu: add debugfs amdgpu_reset_level" This reverts commit 5bd8d53f6fa53eab5433698d1362dae2aa53c1cc. This commit breaks the reset logic for aldebaran, revert it for now. Will move the mask inside the reset handler. Fixes: 5bd8d53f6fa53e ("drm/amdgpu: add debugfs amdgpu_reset_level") Signed-off-by: Victor Zhao <Victor.Zhao@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
68ce8b24 |
|
02-Mar-2022 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: add gang submit backend v2 Allows submitting jobs as gang which needs to run on multiple engines at the same time. Basic idea is that we have a global gang submit fence representing when the gang leader is finally pushed to run on the hardware last. Jobs submitted as gang are never re-submitted in case of a GPU reset since this won't work and will just deadlock the hardware immediately again. v2: fix logic inversion, improve documentation, fix rcu Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
194eb174 |
|
23-Jun-2022 |
Victor Zhao <Victor.Zhao@amd.com> |
drm/amdgpu: reduce reset time In multi container use case, reset time is important, so skip ring tests and cp halt wait during ip suspending for reset as they are going to fail and cost more time on reset v2: add a hang flag to indicate the reset comes from a job timeout, skip ring test and cp halt wait in this case v3: move hang flag to adev Signed-off-by: Victor Zhao <Victor.Zhao@amd.com> Acked-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
5bd8d53f |
|
13-Jun-2022 |
Victor Zhao <Victor.Zhao@amd.com> |
drm/amdgpu: add debugfs amdgpu_reset_level Introduce amdgpu_reset_level debugfs in order to help debug and test specific type of reset. Also helps blocking unwanted type of resets. By default, mode2 reset will not be enabled v2: make this debugfs in adev and use debugfs_create_u32 Signed-off-by: Victor Zhao <Victor.Zhao@amd.com> Acked-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
373008bf |
|
10-Aug-2022 |
Dusica Milinkovic <Dusica.Milinkovic@amd.com> |
drm/amdgpu: Increase tlb flush timeout for sriov [Why] During multi-vf executing benchmark (Luxmark) observed kiq error timeout. It happenes because all of VFs do the tlb invalidation at the same time. Although each VF has the invalidate register set, from hardware side the invalidate requests are queue to execute. [How] In case of 12 VF increase timeout on 12*100ms Signed-off-by: Dusica Milinkovic <Dusica.Milinkovic@amd.com> Acked-by: Shaoyun Liu <shaoyun.liu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
1f83db6b |
|
20-Jul-2022 |
Roy Sun <Roy.Sun@amd.com> |
drm/amdgpu: Fix the incomplete product number The comments say that the product number is a 16-digit HEX string so the buffer needs to be at least 17 characters to hold the NUL terminator. Expand the buffer size to 20 to avoid the alignment issues. The comment:Product number should only be 16 characters. Any more,and something could be wrong. Cap it at 16 to be safe Signed-off-by: Roy Sun <Roy.Sun@amd.com> Reviewed-by: André Almeida <andrealmeid@igalia.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
792a0cdd |
|
06-Jul-2022 |
Leo Li <sunpeng.li@amd.com> |
drm/amd/display: Add visualconfirm module parameter [Why] Being able to configure visual confirm at boot or in cmdline is helpful when debugging. [How] Add a module parameter to configure DC visual confirm, which works the same way as the equivalent debugfs entry. Signed-off-by: Leo Li <sunpeng.li@amd.com> Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
9c913f38 |
|
14-Jul-2022 |
Guchun Chen <guchun.chen@amd.com> |
drm/amdgpu: drop runpm from amdgpu_device structure It's redundant, as now switching to rpm_mode to indicate runtime power management mode. Suggested-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Guchun Chen <guchun.chen@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
f1549c09 |
|
07-Jul-2022 |
Likun Gao <Likun.Gao@amd.com> |
drm/amdgpu: support reset flag set for gpu reset Move reset_context out of gpu recover function to make it configurable for different reset purpose. For the reset way of call gpu_recovery sysfs, force to use full reset method. Otherwise, try soft reset by default if the related ASIC supportted, if soft reset failed, will use full reset. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
cf727044 |
|
17-May-2022 |
Andrey Grodzovsky <andrey.grodzovsky@amd.com> |
drm/amdgpu: Rename amdgpu_device_gpu_recover_imp back to amdgpu_device_gpu_recover We removed the wrapper that was queueing the recover function into reset domain queue who was using this name. Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
2f83658f |
|
17-May-2022 |
Andrey Grodzovsky <andrey.grodzovsky@amd.com> |
drm/amdgpu: Add work_struct for GPU reset from debugfs We need to have a work_struct to cancel this reset if another already in progress. Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
62f8f5c3 |
|
28-Apr-2022 |
Evan Quan <evan.quan@amd.com> |
drm/amdgpu: enable ASPM support for PCIE 7.4.0/7.6.0 Enable ASPM support for PCIE 7.4.0 and 7.6.0. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
08a2fd23 |
|
25-May-2022 |
Ramesh Errabolu <Ramesh.Errabolu@amd.com> |
drm/amdgpu: Add peer-to-peer support among PCIe connected AMD GPUs Add support for peer-to-peer communication among AMD GPUs over PCIe bus. Support REQUIRES enablement of config HSA_AMD_P2P. Signed-off-by: Ramesh Errabolu <Ramesh.Errabolu@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
3d8785f6 |
|
02-Jun-2022 |
Somalapuram Amaranath <Amaranath.Somalapuram@amd.com> |
drm/amdgpu: adding device coredump support Added device coredump information: - Kernel version - Module - Time - VRAM status - Guilty process name and PID - GPU register dumps v1 -> v2: Variable name change v1 -> v2: NULL check v1 -> v2: Code alignment v1 -> v2: Adding dummy amdgpu_devcoredump_free v1 -> v2: memset reset_task_info to zero v2 -> v3: add CONFIG_DEV_COREDUMP for variables v2 -> v3: remove NULL check on amdgpu_devcoredump_read Signed-off-by: Somalapuram Amaranath <Amaranath.Somalapuram@amd.com> Reviewed-by: Shashank Sharma <Shashank.sharma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
651d7ee6 |
|
01-Jun-2022 |
Somalapuram Amaranath <Amaranath.Somalapuram@amd.com> |
drm/amdgpu: save the reset dump register value for devcoredump Allocate memory for register value and use the same values for devcoredump. v1 -> v2: Change krealloc_array() to kmalloc_array() v2 -> v3: Fix alignment Signed-off-by: Somalapuram Amaranath <Amaranath.Somalapuram@amd.com> Reviewed-by: Shashank Sharma <Shashank.sharma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
faf26f2b |
|
26-May-2022 |
pengfuyuan <pengfuyuan@kylinos.cn> |
drm/amd: Fix spelling typo in comments Fix spelling typo in comments. Reported-by: k2ci <kernel-bot@kylinos.cn> Signed-off-by: pengfuyuan <pengfuyuan@kylinos.cn> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
0223e516 |
|
16-May-2022 |
Mario Limonciello <mario.limonciello@amd.com> |
drm/amd: Don't reset dGPUs if the system is going to s2idle An A+A configuration on ASUS ROG Strix G513QY proves that the ASIC reset for handling aborted suspend can't work with s2idle. This functionality was introduced in commit daf8de0874ab5b ("drm/amdgpu: always reset the asic in suspend (v2)"). A few other commits have gone on top of the ASIC reset, but this still doesn't work on the A+A configuration in s2idle. Avoid doing the reset on dGPUs specifically when using s2idle. Fixes: daf8de0874ab5b ("drm/amdgpu: always reset the asic in suspend (v2)") Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2008 Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
1b491330 |
|
05-May-2022 |
Likun Gao <Likun.Gao@amd.com> |
drm/amdgpu: add lsdma block Add Light SDMA (LSDMA) block and related function. LSDMA is a small instance of SDMA mainly for kernel driver use. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
8424f2cc |
|
21-Feb-2022 |
Likun Gao <Likun.Gao@amd.com> |
drm/amdgpu/psp: Add vbflash sysfs interface support Add sysfs interface to copy VBIOS. v2: squash in fix for proper vmalloc API (Alex) Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
5a90c24a |
|
04-May-2022 |
Alex Deucher <alexander.deucher@amd.com> |
Revert "drm/amdgpu: disable runpm if we are the primary adapter" This reverts commit b95dc06af3e683d6b7ddbbae178b2b2a21ee8b2b. This workaround is no longer necessary. We have a better workaround in commit f95af4a9236695 ("drm/amdgpu: don't runtime suspend if there are displays attached (v3)"). Reviewed-by: Javier Martinez Canillas <javierm@redhat.com> Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
928fe236 |
|
14-Apr-2021 |
Jack Xiao <Jack.Xiao@amd.com> |
drm/amdgpu: add mes_kiq module parameter v2 mes_kiq parameter is used to enable mes kiq pipe. This module parameter is unneccessary or enabled by default in final version. v2: reword commit message. Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
2bc956ef |
|
26-Mar-2020 |
Jack Xiao <Jack.Xiao@amd.com> |
drm/amdgpu: add the per-context meta data v3 The per-context meta data is a per-context data structure associated with a mes-managed hardware ring, which includes MCBP CSA, ring buffer and etc. v2: fix typo v3: a. use structure instead of typedef b. move amdgpu_mes_ctx_get_offs_* to amdgpu_ring.h c. use __aligned to make alignement Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
5405a526 |
|
30-Jun-2020 |
Jack Xiao <Jack.Xiao@amd.com> |
drm/amdgpu: define MQD abstract layer for hw ip Define MQD abstract layer for hw ip, for the passing mqd configuration not only from ring but more sources, like user queue. Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
7f318f4e |
|
04-May-2022 |
Likun Gao <Likun.Gao@amd.com> |
drm/amdgpu: add tracking for the enablement of SCPM Add parmeter to shows whether SCPM feature is enabled or not, and whether is valid. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
563fcfbf |
|
04-Apr-2022 |
Likun Gao <Likun.Gao@amd.com> |
drm/amdgpu: add hdp version 6 functions Unify hdp related function into hdp structure for hdp version 6. V2: Remove hdp invalidate function as hdp v6 doesn't have read cache. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
1d5eee7d |
|
10-Dec-2021 |
Likun Gao <Likun.Gao@amd.com> |
drm/amdgpu: add function to decode ip version Add function to decode IP version. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
3202c7e7 |
|
07-Nov-2019 |
Likun Gao <Likun.Gao@amd.com> |
drm/amdgpu: increase HWIP MAX INSTANCE Extend HWIP MAX INSTANCE to 11. Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
25faeddc |
|
25-Mar-2022 |
Evan Quan <evan.quan@amd.com> |
drm/amdgpu: expand cg_flags from u32 to u64 With this, we can support more CG flags. Signed-off-by: Evan Quan <evan.quan@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
7123d39d |
|
16-May-2022 |
Mario Limonciello <mario.limonciello@amd.com> |
drm/amd: Don't reset dGPUs if the system is going to s2idle An A+A configuration on ASUS ROG Strix G513QY proves that the ASIC reset for handling aborted suspend can't work with s2idle. This functionality was introduced in commit daf8de0874ab5b ("drm/amdgpu: always reset the asic in suspend (v2)"). A few other commits have gone on top of the ASIC reset, but this still doesn't work on the A+A configuration in s2idle. Avoid doing the reset on dGPUs specifically when using s2idle. Fixes: daf8de0874ab5b ("drm/amdgpu: always reset the asic in suspend (v2)") Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2008 Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
|
#
a190f8dc |
|
21-Feb-2022 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: header cleanup No function change, just move a bunch of definitions from amdgpu.h into separate header files. Signed-off-by: Christian König <christian.koenig@amd.com> Acked-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
11eb648d |
|
02-Mar-2022 |
Ruijing Dong <ruijing.dong@amd.com> |
drm/amdgpu/vcn: Add vcn firmware log vcn fwlog is for debugging purpose only, by default, it is disabled. Signed-off-by: Ruijing Dong <ruijing.dong@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
158a05a0 |
|
23-Feb-2022 |
Alex Sierra <alex.sierra@amd.com> |
drm/amdgpu: Add use_xgmi_p2p module parameter This parameter controls xGMI p2p communication, which is enabled by default. However, it can be disabled by setting it to 0. In case xGMI p2p is disabled in a dGPU, PCIe p2p interface will be used instead. This parameter is ignored in GPUs that do not support xGMI p2p configuration. Signed-off-by: Alex Sierra <alex.sierra@amd.com> Acked-by: Luben Tuikov <luben.tuikov@amd.com> Acked-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
5ce5a584 |
|
23-Feb-2022 |
Somalapuram Amaranath <Amaranath.Somalapuram@amd.com> |
drm/amdgpu: add debugfs for reset registers list List of register populated for dump collection during the GPU reset. Signed-off-by: Somalapuram Amaranath <Amaranath.Somalapuram@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
b784f42c |
|
18-Feb-2022 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: drop testing module parameter This test is not particularly useful now that GTT and GART are decoupled in the driver. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
0b1a6348 |
|
18-Feb-2022 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: drop benchmark module parameter Now that we expose the benchmarks via debugfs, there is no longer a need for the module parameter. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
f113cc32 |
|
18-Feb-2022 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: add a benchmark mutex To avoid multiple runs in parallel to avoid mixing results. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
e460f244 |
|
18-Feb-2022 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: plumb error handling though amdgpu_benchmark() So we can tell when this function fails. v2: squash in error handling fix (Alex) Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
0ab5d711 |
|
16-Feb-2022 |
Mario Limonciello <mario.limonciello@amd.com> |
drm/amd: Refactor `amdgpu_aspm` to be evaluated per device Evaluating `pcie_aspm_enabled` as part of driver probe has the implication that if one PCIe bridge with an AMD GPU connected doesn't support ASPM then none of them do. This is an invalid assumption as the PCIe core will configure ASPM for individual PCIe bridges. Create a new helper function that can be called by individual dGPUs to react to the `amdgpu_aspm` module parameter without having negative results for other dGPUs on the PCIe bus. Suggested-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
a6c40b17 |
|
03-Feb-2022 |
Luben Tuikov <luben.tuikov@amd.com> |
drm/amdgpu: Show IP discovery in sysfs Add IP discovery data in sysfs. The format is: /sys/class/drm/cardX/device/ip_discovery/die/D/B/I/<attrs> where, X is the card ID, an integer, D is the die ID, an integer, B is the IP HW ID, an integer, aka block type, I is the IP HW ID instance, an integer. <attrs> are the attributes of the block instance. At the moment these include HW ID, instance number, major, minor, revision, number of base addresses, and the base addresses themselves. A symbolic link of the acronym HW ID is also created, under D/, if you prefer to browse by something humanly accessible. Cc: Alex Deucher <Alexander.Deucher@amd.com> Cc: Tom StDenis <tom.stdenis@amd.com> Signed-off-by: Luben Tuikov <luben.tuikov@amd.com> Reviewed-by: Alex Deucher <Alexander.Deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
89a7a870 |
|
19-Jan-2022 |
Andrey Grodzovsky <andrey.grodzovsky@amd.com> |
drm/amdgpu: Move in_gpu_reset into reset_domain We should have a single instance per entrire reset domain. Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Suggested-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Link: https://www.spinics.net/lists/amd-gfx/msg74116.html
|
#
d0fb18b5 |
|
19-Jan-2022 |
Andrey Grodzovsky <andrey.grodzovsky@amd.com> |
drm/amdgpu: Move reset sem into reset_domain We want single instance of reset sem across all reset clients because in case of XGMI we should stop access cross device MMIO because any of them could be in a reset in the moment. Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Link: https://www.spinics.net/lists/amd-gfx/msg74117.html
|
#
cfbb6b00 |
|
21-Jan-2022 |
Andrey Grodzovsky <andrey.grodzovsky@amd.com> |
drm/amdgpu: Rework reset domain to be refcounted. The reset domain contains register access semaphor now and so needs to be present as long as each device in a hive needs it and so it cannot be binded to XGMI hive life cycle. Adress this by making reset domain refcounted and pointed by each member of the hive and the hive itself. v4: Fix crash on boot witrh XGMI hive by adding type to reset_domain. XGMI will only create a new reset_domain if prevoius was of single device type meaning it's first boot. Otherwsie it will take a refocunt to exsiting reset_domain from the amdgou device. Add a wrapper around reset_domain->refcount get/put and a wrapper around send to reset wq (Lijo) Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Link: https://www.spinics.net/lists/amd-gfx/msg74121.html
|
#
54f329cc |
|
17-Dec-2021 |
Andrey Grodzovsky <andrey.grodzovsky@amd.com> |
drm/amdgpu: Serialize non TDR gpu recovery with TDRs Use reset domain wq also for non TDR gpu recovery trigers such as sysfs and RAS. We must serialize all possible GPU recoveries to gurantee no concurrency there. For TDR call the original recovery function directly since it's already executed from within the wq. For others just use a wrapper to qeueue work and wait on it to finish. v2: Rename to amdgpu_recover_work_struct Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Link: https://www.spinics.net/lists/amd-gfx/msg74113.html
|
#
a4c63caf |
|
30-Nov-2021 |
Andrey Grodzovsky <andrey.grodzovsky@amd.com> |
drm/amdgpu: Introduce reset domain Defined a reset_domain struct such that all the entities that go through reset together will be serialized one against another. Do it for both single device and XGMI hive cases. Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Suggested-by: Daniel Vetter <daniel.vetter@ffwll.ch> Suggested-by: Christian König <ckoenig.leichtzumerken@gmail.com> Reviewed-by: Christian König <christian.koenig@amd.com> Link: https://www.spinics.net/lists/amd-gfx/msg74111.html
|
#
18b66ace |
|
25-Jan-2022 |
Mario Limonciello <mario.limonciello@amd.com> |
drm/amd: add support to check whether the system is set to s3 This will be used to help make decisions on what to do in misconfigured systems. v2: squash in semicolon fix from Stephen Rothwell Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
f588a1bb |
|
11-Jan-2022 |
Mario Limonciello <mario.limonciello@amd.com> |
drm/amd: Warn users about potential s0ix problems On some OEM setups users can configure the BIOS for S3 or S2idle. When configured to S3 users can still choose 's2idle' in the kernel by using `/sys/power/mem_sleep`. Before commit 6dc8265f9803 ("drm/amdgpu: always reset the asic in suspend (v2)"), the GPU would crash. Now when configured this way, the system should resume but will use more power. As such, adjust the `amdpu_acpi_is_s0ix function` to warn users about potential power consumption issues during their first attempt at suspending. Reported-by: Bjoren Dasse <bjoern.daase@gmail.com> Link: https://gitlab.freedesktop.org/drm/amd/-/issues/1824 Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
04022982 |
|
10-Jan-2022 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu: switch to common helper to read bios from rom create a common helper function for soc15 and onwards to read bios image from rom Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
86700a40 |
|
18-Jan-2022 |
Xiaojian Du <Xiaojian.Du@amd.com> |
drm/amdgpu: modify a pair of functions for the pcie port wreg/rreg This patch will modify a pair of functions for pcie port wreg/rreg. AMD GPU have had an independent NBIO block from SOC15 arch. If the dirver wants to read/write the address space of the pcie devices, it has to go through the NBIO block. This patch will move the pcie port wreg/rreg functions to "amdgpu_device.c", so that to reuse the functions on the future GPU ASICs. Signed-off-by: Xiaojian Du <Xiaojian.Du@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
400ef298 |
|
12-Jan-2022 |
Jonathan Kim <jonathan.kim@amd.com> |
drm/amdgpu: cleanup ttm debug sdma vram access function Some suggested cleanups to declutter ttm when doing debug VRAM access over SDMA. Signed-off-by: Jonathan Kim <jonathan.kim@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
7cab2124 |
|
03-Jan-2022 |
yipechai <YiPeng.Chai@amd.com> |
drm/amdgpu: Modify the compilation failed problem when other ras blocks' .h include amdgpu_ras.h Modify the compilation failed problem when other ras blocks' .h include amdgpu_ras.h. v2: squash in forward declaration warning fix (Alex) Signed-off-by: yipechai <YiPeng.Chai@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: John Clements <john.clements@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
6492e1b0 |
|
03-Jan-2022 |
yipechai <YiPeng.Chai@amd.com> |
drm/amdgpu: Unify ras block interface for each ras block 1. Define unified ops interface for each block. 2. Add ras_block_match function pointer in ops interface, each ras block can customize specail match function to identify itself. 3. Add amdgpu_ras_block_match_default new function. If a ras block doesn't define .ras_block_match, default execute amdgpu_ras_block_match_default to identify this ras block. 4. Define unified basic ras block data for each ras block. 5. Create dedicated amdgpu device ras block link list to manage all of the ras blocks. 6. Add amdgpu_ras_register_ras_block new function interface for each ras block to register itself to ras controlling block. Signed-off-by: yipechai <YiPeng.Chai@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: John Clements <john.clements@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
ebfc2533 |
|
21-Nov-2021 |
Evan Quan <evan.quan@amd.com> |
drm/amd/pm: do not expose the smu_context structure used internally in power This can cover the power implementation details. And as what did for powerplay framework, we hook the smu_context to adev->powerplay.pp_handle. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
d698a2c4 |
|
15-Nov-2021 |
Evan Quan <evan.quan@amd.com> |
drm/amd/pm: move pp_force_state_enabled member to amdgpu_pm structure As it lables an internal pm state and amdgpu_pm structure is the more proper place than amdgpu_device structure for it. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
de05abe6 |
|
06-Jan-2022 |
Solomon Chiu <solomon.chiu@amd.com> |
drm/amd/display: Enable Freesync Video Mode by default [Why&How] Freesync Video Mode is a experimental feature previously, and need to be enabled by kernel parameter. We enable it by default with removing module paramterter in amdgpu_dm. v2: squash the patches together Signed-off-by: Solomon Chiu <solomon.chiu@amd.com> Reviewed-by: Aurabindo Jayamohanan Pillai <Aurabindo.Pillai@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
f52a2b8b |
|
25-Jan-2022 |
Mario Limonciello <mario.limonciello@amd.com> |
drm/amd: add support to check whether the system is set to s3 This will be used to help make decisions on what to do in misconfigured systems. v2: squash in semicolon fix from Stephen Rothwell Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
a6ed2035 |
|
11-Jan-2022 |
Mario Limonciello <mario.limonciello@amd.com> |
drm/amd: Warn users about potential s0ix problems On some OEM setups users can configure the BIOS for S3 or S2idle. When configured to S3 users can still choose 's2idle' in the kernel by using `/sys/power/mem_sleep`. Before commit 6dc8265f9803 ("drm/amdgpu: always reset the asic in suspend (v2)"), the GPU would crash. Now when configured this way, the system should resume but will use more power. As such, adjust the `amdpu_acpi_is_s0ix function` to warn users about potential power consumption issues during their first attempt at suspending. Reported-by: Bjoren Dasse <bjoern.daase@gmail.com> Link: https://gitlab.freedesktop.org/drm/amd/-/issues/1824 Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
6c92fe5fa |
|
13-Dec-2021 |
Kent Russell <kent.russell@amd.com> |
drm/amdgpu: Increase potential product_name to 64 characters Having seen at least 1 42-character product_name, bump the number up to 64, and put that definition into amdgpu.h to make future adjustments simpler. Signed-off-by: Kent Russell <kent.russell@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
4a74c38c |
|
06-Dec-2021 |
Philip Yang <Philip.Yang@amd.com> |
drm/amdgpu: Detect if amdgpu in IOMMU direct map mode If host and amdgpu IOMMU is not enabled or IOMMU is pass through mode, set adev->ram_is_direct_mapped flag which will be used to optimize memory usage for multi GPU mappings. Signed-off-by: Philip Yang <Philip.Yang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
34f3a4a9 |
|
09-Dec-2021 |
Lang Yu <lang.yu@amd.com> |
drm/amdgpu: introduce a kind of halt state for amdgpu device It is useful to maintain error context when debugging SW/FW issues. Introduce amdgpu_device_halt() for this purpose. It will bring hardware to a kind of halt state, so that no one can touch it any more. Compare to a simple hang, the system will keep stable at least for SSH access. Then it should be trivial to inspect the hardware state and see what's going on. v2: - Set adev->no_hw_access earlier to avoid potential crashes.(Christian) Suggested-by: Christian Koenig <christian.koenig@amd.com> Suggested-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Signed-off-by: Lang Yu <lang.yu@amd.com> Reviewed-by: Christian Koenig <christian.koenig@amd.co> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
e105b64a |
|
07-Dec-2021 |
Isabella Basso <isabbasso@riseup.net> |
drm/amdgpu: fix location of prototype for amdgpu_kms_compat_ioctl This fixes the warning below by changing the prototype to a location that's actually included by the .c files that call amdgpu_kms_compat_ioctl: warning: no previous prototype for ‘amdgpu_kms_compat_ioctl’ [-Wmissing-prototypes] 37 | long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) | ^~~~~~~~~~~~~~~~~~~~~~~ Signed-off-by: Isabella Basso <isabbasso@riseup.net> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
fe9c5c9a |
|
25-Nov-2021 |
Lijo Lazar <lijo.lazar@amd.com> |
drm/amdgpu: Use MAX_HWIP instead of HW_ID_MAX HW_ID_MAX considers HWID of all IPs, far more than what amdgpu uses. amdgpu tracks only the IPs defined by amd_hw_ip_block_type whose max is MAX_HWIP. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Guchun Chen <guchun.chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
fa78e367 |
|
22-Sep-2021 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: stop getting excl fence separately Just grab all fences for the display flip in one go. Signed-off-by: Christian König <christian.koenig@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Link: https://patchwork.freedesktop.org/patch/msgid/20211028132630.2330-2-christian.koenig@amd.com
|
#
b95dc06a |
|
22-Dec-2021 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: disable runpm if we are the primary adapter If we are the primary adapter (i.e., the one used by the firwmare framebuffer), disable runtime pm. This fixes a regression caused by commit 55285e21f045 which results in the displays waking up shortly after they go to sleep due to the device coming out of runtime suspend and sending a hotplug uevent. v2: squash in reworked fix from Evan Fixes: 55285e21f045 ("fbdev/efifb: Release PCI device's runtime PM ref during FB destroy") Bug: https://bugzilla.kernel.org/show_bug.cgi?id=215203 Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1840 Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
68daadf3 |
|
19-Oct-2021 |
Kent Russell <kent.russell@amd.com> |
drm/amdgpu: Add kernel parameter support for ignoring bad page threshold When a GPU hits the bad_page_threshold, it will not be initialized by the amdgpu driver. This means that the table cannot be cleared, nor can information gathering be performed (getting serial number, BDF, etc). If the bad_page_threshold kernel parameter is set to -2, continue to initialize the GPU, while printing a warning to dmesg that this action has been done v2: squash in Luben's fix to restore RAS info reporting Cc: Luben Tuikov <luben.tuikov@amd.com> Cc: Mukul Joshi <Mukul.Joshi@amd.com> Signed-off-by: Kent Russell <kent.russell@amd.com> Acked-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Luben Tuikov <luben.tuikov@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
e17e27f9 |
|
30-Sep-2021 |
Guchun Chen <guchun.chen@amd.com> |
drm/amdgpu: handle the case of pci_channel_io_frozen only in amdgpu_pci_resume In current code, when a PCI error state pci_channel_io_normal is detectd, it will report PCI_ERS_RESULT_CAN_RECOVER status to PCI driver, and PCI driver will continue the execution of PCI resume callback report_resume by pci_walk_bridge, and the callback will go into amdgpu_pci_resume finally, where write lock is releasd unconditionally without acquiring such lock first. In this case, a deadlock will happen when other threads start to acquire the read lock. To fix this, add a member in amdgpu_device strucutre to cache pci_channel_state, and only continue the execution in amdgpu_pci_resume when it's pci_channel_io_frozen. Fixes: c9a6b82f45e2 ("drm/amdgpu: Implement DPC recovery") Suggested-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Signed-off-by: Guchun Chen <guchun.chen@amd.com> Reviewed-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
c8365dbd |
|
30-Sep-2021 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: revert "Add autodump debugfs node for gpu reset v8" This reverts commit 728e7e0cd61899208e924472b9e641dbeb0775c4. Further discussion reveals that this feature is severely broken and needs to be reverted ASAP. GPU reset can never be delayed by userspace even for debugging or otherwise we can run into in kernel deadlocks. Signed-off-by: Christian König <christian.koenig@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Acked-by: Nirmoy Das <nirmoy.das@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
1d789535 |
|
04-Oct-2021 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: convert IP version array to include instances Allow us to query instances versions more cleanly. Instancing support is not consistent unfortunately. SDMA is a good example. Sienna cichlid has 4 total SDMA instances, each enumerated separately (HWIDs 42, 43, 68, 69). Arcturus has 8 total SDMA instances, but they are enumerated as multiple instances of the same HWIDs (4x HWID 42, 4x HWID 43). UMC is another example. On most chips there are multiple instances with the same HWID. This allows us to support both forms. v2: rebase v3: clarify instancing support Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
5eceb201 |
|
08-Aug-2021 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: add VCN1 hardware IP So we can store the VCN IP revision for each instance of VCN. Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
5f931489 |
|
29-Jul-2021 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: add DCI HWIP So we can track grab the appropriate DCE info out of the IP discovery table. This is a separare IP from DCN. Acked-by: Harry Wentland <harry.wentland@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
1534db55 |
|
26-Jul-2021 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: add XGMI HWIP So we can track grab the appropriate XGMI info out of the IP discovery table. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
5f52e9a7 |
|
20-Jul-2021 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: store HW IP versions in the driver structure So we can check the IP versions directly rather than using asic type. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
81d1bf01 |
|
20-Jul-2021 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: add debugfs access to the IP discovery table Useful for debugging and new asic validation. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
cd54323e |
|
02-Sep-2021 |
Ernst Sjöstrand <ernstp@gmail.com> |
drm/amd/amdgpu: Increase HWIP_MAX_INSTANCE to 10 Seems like newer cards can have even more instances now. Found by UBSAN: array-index-out-of-bounds in drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c:318:29 index 8 is out of range for type 'uint32_t *[8]' Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1697 Cc: stable@vger.kernel.org Signed-off-by: Ernst Sjöstrand <ernstp@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
248b0616 |
|
30-Sep-2021 |
Guchun Chen <guchun.chen@amd.com> |
drm/amdgpu: handle the case of pci_channel_io_frozen only in amdgpu_pci_resume In current code, when a PCI error state pci_channel_io_normal is detectd, it will report PCI_ERS_RESULT_CAN_RECOVER status to PCI driver, and PCI driver will continue the execution of PCI resume callback report_resume by pci_walk_bridge, and the callback will go into amdgpu_pci_resume finally, where write lock is releasd unconditionally without acquiring such lock first. In this case, a deadlock will happen when other threads start to acquire the read lock. To fix this, add a member in amdgpu_device strucutre to cache pci_channel_state, and only continue the execution in amdgpu_pci_resume when it's pci_channel_io_frozen. Fixes: c9a6b82f45e2 ("drm/amdgpu: Implement DPC recovery") Suggested-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Signed-off-by: Guchun Chen <guchun.chen@amd.com> Reviewed-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
67a44e65 |
|
02-Sep-2021 |
Ernst Sjöstrand <ernstp@gmail.com> |
drm/amd/amdgpu: Increase HWIP_MAX_INSTANCE to 10 Seems like newer cards can have even more instances now. Found by UBSAN: array-index-out-of-bounds in drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c:318:29 index 8 is out of range for type 'uint32_t *[8]' Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1697 Cc: stable@vger.kernel.org Signed-off-by: Ernst Sjöstrand <ernstp@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
3907c492 |
|
23-Aug-2021 |
John Clements <john.clements@amd.com> |
drm/amdgpu: Add driver infrastructure for MCA RAS Add MCA specific IP blocks targetting RAS features Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: John Clements <john.clements@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
0d8318e1 |
|
09-Feb-2021 |
Evan Quan <evan.quan@amd.com> |
drm/amd/pm: drop the unnecessary intermediate percent-based transition Currently, the readout of fan speed pwm is transited into percent-based and then pwm-based. However, the transition into percent-based is totally unnecessary and make the final output less accurate. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
84ec374b |
|
07-Jun-2021 |
Ryan Taylor <Ryan.Taylor@amd.com> |
drm/amdgpu: create amdgpu_vkms (v4) Modify the VKMS driver into an api that dce_virtual can use to create virtual displays that obey drm's atomic modesetting api. v2: Made local functions static. v3: Switched vkms_output kzalloc for kcalloc. Cleanup patches by moving display mode fixes to this patch. v4: Update atomic_check and atomic_update to comply with new kms api. Signed-off-by: Ryan Taylor <Ryan.Taylor@amd.com> Reported-by: kernel test robot <lkp@intel.com> Suggested-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
d0260f62 |
|
26-Jul-2021 |
Pratik Vishwakarma <Pratik.Vishwakarma@amd.com> |
drm/amdgpu: Rename amdgpu_acpi_is_s0ix_supported Rename amdgpu_acpi_is_s0ix_supported to better explain functionality by renaming to amdgpu_acpi_is_s0ix_active Signed-off-by: Pratik Vishwakarma <Pratik.Vishwakarma@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
048af66b |
|
16-Jul-2021 |
Kevin Wang <kevin1.wang@amd.com> |
drm/amdgpu: split amdgpu_device_access_vram() into two small parts split amdgpu_device_access_vram() 1. amdgpu_device_mm_access(): using MM_INDEX/MM_DATA to access vram 2. amdgpu_device_aper_access(): using vram aperature to access vram (option) Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
9075096b |
|
13-Jul-2021 |
Veerabadhran Gopalakrishnan <veerabadhran.gopalakrishnan@amd.com> |
amdgpu/nv.c - Optimize code for video codec support structure Optimized the code for codec info structure initialization Signed-off-by: Veerabadhran Gopalakrishnan <veerabadhran.gopalakrishnan@amd.com> Reviewed-by: James Zhu <James.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
6505d6fc |
|
13-Jul-2021 |
Veerabadhran Gopalakrishnan <veerabadhran.gopalakrishnan@amd.com> |
amdgpu/nv.c - Optimize code for video codec support structure Optimized the code for codec info structure initialization Signed-off-by: Veerabadhran Gopalakrishnan <veerabadhran.gopalakrishnan@amd.com> Reviewed-by: James Zhu <James.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
810085dd |
|
02-Jun-2021 |
Eric Huang <jinhuieric.huang@amd.com> |
drm/amdgpu: Don't flush/invalidate HDP for APUs and A+A Integrate two generic functions to determine if HDP flush is needed for all Asics. Signed-off-by: Eric Huang <jinhuieric.huang@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
30d95a37 |
|
29-May-2021 |
Sathishkumar S <sathishkumar.sundararaju@amd.com> |
drm/amdgpu: attr to control SS2.0 bias level (v2) add sysfs attr to read/write smartshift bias level. document smartshift_bias sysfs attr. V2: add attr to amdgpu_device_attrs and use attr_update (Lijo) Signed-off-by: Sathishkumar S <sathishkumar.sundararaju@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
3fa8f89d |
|
26-May-2021 |
Sathishkumar S <sathishkumar.sundararaju@amd.com> |
drm/amdgpu: enable smart shift on dGPU (v5) enable smart shift on dGPU if it is part of HG system and the platform supports ATCS method to handle power shift. V2: avoid psc updates in baco enter and exit (Lijo) fix alignment (Shashank) V3: rebased on unified ATCS handling. (Alex) V4: check for return value and warn on failed update (Shashank) return 0 if device does not support smart shift. (Lizo) V5: rebased on ATPX/ATCS structures global (Alex) Signed-off-by: Sathishkumar S <sathishkumar.sundararaju@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Shashank Sharma <shashank.sharma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
16eb48c6 |
|
10-May-2021 |
Sathishkumar S <sathishkumar.sundararaju@amd.com> |
drm/amdgpu: support atcs method powershift (v4) add support to handle ATCS method for power shift control. used to communicate dGPU device state to SBIOS. V2: use defined acpi func for checking psc support (Lijo) fix alignment (Shashank) V3: rebased on unified ATCS handling (Alex) V4: rebased on ATPX/ATCS structures global (Alex) Signed-off-by: Sathishkumar S <sathishkumar.sundararaju@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
f9b7f370 |
|
25-May-2021 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu/acpi: make ATPX/ATCS structures global (v2) They are global ACPI methods, so maybe the structures global in the driver. This simplified a number of things in the handling of these methods. v2: reset the handle if verify interface fails (Lijo) v3: fix compilation when ACPI is not defined. Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
7afefb81 |
|
21-May-2021 |
Andrey Grodzovsky <andrey.grodzovsky@amd.com> |
drm/amdgpu: Rename flag which prevents HW access Make it's name not feature but function descriptive. Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210521204122.762288-1-andrey.grodzovsky@amd.com
|
#
77bf762f |
|
19-May-2021 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu/acpi: unify ATCS handling (v3) Treat it like ATIF and check both the dGPU and APU for the method. This is required because ATCS may be hung off of the APU in ACPI on A+A systems. v2: add back accidently removed ACPI handle check. v3: Fix incorrect atif check (Colin) Fix uninitialized variable (Colin) Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
a5504e9a |
|
14-May-2021 |
Peng Ju Zhou <PengJu.Zhou@amd.com> |
drm/amdgpu: Indirect register access for Navi12 sriov This patch series are used for GC/MMHUB(part)/IH_RB_CNTL indirect access in the SRIOV environment. There are 4 bits, controlled by host, to control if GC/MMHUB(part)/IH_RB_CNTL indirect access enabled. (one bit is master bit controls other 3 bits) For GC registers, changing all the register access from MMIO to RLC and use RLC as the default access method in the full access time. For partial MMHUB registers, changing their access from MMIO to RLC in the full access time, the remaining registers keep the original access method. For IH_RB_CNTL register, changing it's access from MMIO to PSP. Signed-off-by: Peng Ju Zhou <PengJu.Zhou@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
72c8c97b |
|
12-May-2021 |
Andrey Grodzovsky <andrey.grodzovsky@amd.com> |
drm/amdgpu: Split amdgpu_device_fini into early and late Some of the stuff in amdgpu_device_fini such as HW interrupts disable and pending fences finilization must be done right away on pci_remove while most of the stuff which relates to finilizing and releasing driver data structures can be kept until drm_driver.release hook is called, i.e. when the last device reference is dropped. v4: Change functions prefix early->hw and late->sw Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210512142648.666476-3-andrey.grodzovsky@amd.com
|
#
7bd939d0 |
|
29-Apr-2021 |
Likun GAO <Likun.Gao@amd.com> |
drm/amdgpu: add judgement when add ip blocks (v2) Judgement whether to add an sw ip according to the harvest info. v2: fix indentation (Alex) Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Guchun Chen <guchun.chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
8ab0d6f0 |
|
04-May-2021 |
Luben Tuikov <luben.tuikov@amd.com> |
drm/amdgpu: Rename to ras_*_enabled Rename, ras_hw_supported --> ras_hw_enabled, and ras_features --> ras_enabled, to show that ras_enabled is a subset of ras_hw_enabled, which itself is a subset of the ASIC capability. Cc: Alexander Deucher <Alexander.Deucher@amd.com> Cc: John Clements <john.clements@amd.com> Cc: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Luben Tuikov <luben.tuikov@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: John Clements <John.Clements@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
e509965e |
|
03-May-2021 |
Luben Tuikov <luben.tuikov@amd.com> |
drm/amdgpu: Move up ras_hw_supported Move ras_hw_supported into struct amdgpu_dev. The dependency is: struct amdgpu_ras <== struct amdgpu_dev <== ASIC, read as "struct amdgpu_ras depends on struct amdgpu_dev, which depends on the hardware." This can be loosely understood as, "if RAS is supported, which is property of the ASIC (struct amdgpu_dev), then we can access struct amdgpu_ras." v2: Fix a typo: must binary AND in ternary cond in amdgpu_ras.c Cc: Alexander Deucher <Alexander.Deucher@amd.com> Cc: John Clements <john.clements@amd.com> Cc: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Luben Tuikov <luben.tuikov@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: John Clements <John.Clements@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
87444254 |
|
26-Apr-2021 |
Roy Sun <Roy.Sun@amd.com> |
drm/amdgpu: Add show_fdinfo() interface Tracking devices, process info and fence info using /proc/pid/fdinfo Signed-off-by: David M Nieto <David.Nieto@amd.com> Signed-off-by: Roy Sun <Roy.Sun@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Christian König <christian.koenig@amd.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210426062701.39732-2-Roy.Sun@amd.com
|
#
83a0b863 |
|
29-Apr-2021 |
Likun GAO <Likun.Gao@amd.com> |
drm/amdgpu: add judgement when add ip blocks (v2) Judgement whether to add an sw ip according to the harvest info. v2: fix indentation (Alex) Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Guchun Chen <guchun.chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
f066af88 |
|
31-Mar-2021 |
Jude Shih <shenshih@amd.com> |
drm/amdgpu: add DMUB outbox event IRQ source define/complete/debug flag [Why & How] We use outbox interrupt that allows us to do the AUX via DMUB Therefore, we need to add some irq source related definition in the header files; Signed-off-by: Jude Shih <shenshih@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
5d89bb2d |
|
16-Mar-2021 |
Lijo Lazar <lijo.lazar@amd.com> |
drm/amdgpu: Make set PG/CG state functions public Expose PG/CG set states functions for other clients Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
04442bf7 |
|
16-Mar-2021 |
Lijo Lazar <lijo.lazar@amd.com> |
drm/amdgpu: Add reset control handling to reset workflow This prefers reset control based handling if it's implemented for a particular ASIC. If not, it takes the legacy path. It uses the legacy method of preparing environment (job, scheduler tasks) and restoring environment. v2: remove unused variable (Alex) Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
e071dce3 |
|
16-Mar-2021 |
Lijo Lazar <lijo.lazar@amd.com> |
drm/amdgpu: Add reset control to amdgpu_device v1: Add generic amdgpu_reset_control to handle different types of resets. It may be added at device, hive or ip level. Each reset control has a list of handlers associated with it to handle different types of reset. Reset control is responsible for choosing the right handler given a particular reset context. Handler objects may implement a set of functions on how to handle a particular type of reset. prepare_env = Prepare environment/software context (not used currently). prepare_hwcontext = Prepare hardware context for the reset. perform_reset = Perform the type of reset. restore_hwcontext = Restore the hw context after reset. restore_env = Restore the environment after reset (not used currently). Reset context carries the context of reset, as of now this is based on the parameters used for current set of resets. v2: Fix coding style Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
32c811b0 |
|
22-Mar-2021 |
Wan Jiabing <wanjiabing@vivo.com> |
drivers: gpu: Remove duplicate include of amdgpu_hdp.h amdgpu_hdp.h has been included at line 91, so remove the duplicate include. Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Wan Jiabing <wanjiabing@vivo.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
62498733 |
|
12-Mar-2021 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: rework S3/S4/S0ix state handling Set flags at the top level pmops callbacks to track state. This cleans up the current set of flags and properly handles S4 on S0ix capable systems. Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
b98c6299 |
|
09-Mar-2021 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: disentangle HG systems from vgaswitcheroo There's no need to keep vgaswitcheroo around for HG systems. They don't use muxes and their power control is handled via ACPI. Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
56b53c0b |
|
10-Mar-2021 |
Dennis Li <Dennis.Li@amd.com> |
drm/amdgpu: add codes to capture invalid hardware access when recovery When recovery thread has begun GPU reset, there should be not other threads to access hardware, otherwise system randomly hang. v2 (chk): rewritten from scratch, use trylock and lockdep instead of hand wiring the logic. v3: add in_irq check v4: change to check in_task Signed-off-by: Dennis Li <Dennis.Li@amd.com> Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
a85ba005 |
|
15-Mar-2021 |
Nikola Cornij <nikola.cornij@amd.com> |
drm/amdgpu/display: re-enable freesync video patches Since this is a "revert of a revert", the end effect is that freesync video is back to its original state, the way it was before the first revert. Signed-off-by: Nikola Cornij <nikola.cornij@amd.com> Reviewed-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
e99d2eaa |
|
15-Mar-2021 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: drop legacy IO bar support It was leftover from radeon where it was required for some specific old hardware. It hasn't been required for ages and the driver already falls back to MMIO when legacy IO is not available. Legacy IO also seems to be problematic on on some thunderbolt devices. Drop it. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: Nicholas Johnson <nicholas.johnson-opensource@outlook.com.au>
|
#
e3c1b071 |
|
15-Feb-2021 |
shaoyunl <shaoyun.liu@amd.com> |
drm/amdgpu: Reset the devices in the XGMI hive duirng probe In passthrough configuration, hypervisior will trigger the SBR(Secondary bus reset) to the devices without sync to each other. This could cause device hang since for XGMI configuration, all the devices within the hive need to be reset at a limit time slot. This serial of patches try to solve this issue by co-operate with new SMU which will only do minimum house keeping to response the SBR request but don't do the real reset job and leave it to driver. Driver need to do the whole sw init and minimum HW init to bring up the SMU and trigger the reset(possibly BACO) on all the ASICs at the same time Signed-off-by: shaoyunl <shaoyun.liu@amd.com> Acked-by: Andrey Grodzovsky andrey.grodzovsky@amd.com Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
655ce9cb |
|
04-Mar-2021 |
shaoyunl <shaoyun.liu@amd.com> |
drm/amdgpu: Add reset_list for device list used for reset The gmc.xgmi.head list originally is designed for device list in the XGMI hive. Mix use it for reset purpose will prevent the reset function to adjust XGMI device list which is required in next change Signed-off-by: shaoyunl <shaoyun.liu@amd.com> Reviewed-by: Andrey Grodzovsky andrey.grodzovsky@amd.com Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
c0ea73a4 |
|
06-Mar-2021 |
Aurabindo Pillai <aurabindo.pillai@amd.com> |
Revert freesync video patches temporarily This temporarily reverts freesync video patches since it causes regression with eDP displays. This patch is a squashed revert of the following patches: 6f59f229f8ed ("drm/amd/display: Skip modeset for front porch change") d10cd527f5e5 ("drm/amd/display: Add freesync video modes based on preferred modes") 0eb1af2e8205 ("drm/amd/display: Add module parameter for freesync video mode") Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Reviewed-by: Anson Jacob <anson.jacob@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
88f8575b |
|
05-Mar-2021 |
Dennis Li <Dennis.Li@amd.com> |
drm/amdgpu: enable watchdog feature for SQ of aldebaran SQ's watchdog timer monitors forward progress, a mask of which waves caused the watchdog timeout is recorded into ras status registers and then trigger a system fatal error event. v2: 1. change *query_timeout_status to *query_sq_timeout_status. 2. move query_sq_timeout_status into amdgpu_ras_do_recovery. 3. add module parameters to enable/disable fatal error event and modify the watchdog timer. v3: 1. remove unused parameters of *enable_watchdog_timer Signed-off-by: Dennis Li <Dennis.Li@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
8738a82b |
|
28-Nov-2020 |
Lijo Lazar <lijo.lazar@amd.com> |
drm/amd/amdgpu: Add smu_pptable module parameter Temporarily add smu_pptable module parameter for aldebaran.This is used to force soft PPTable use overriding any VBIOS PPTable. Signed-off-by: Lijo Lazar <Lijo.Lazar@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
5c03e584 |
|
19-Nov-2020 |
Feifei Xu <Feifei.Xu@amd.com> |
drm/amdgpu:add smu mode1/2 support for aldebaran Use MSG_GfxDriverReset for mode reset and retire MSG_Mode1Reset. Centralize soc15_asic_mode1_reset() and nv_asic_mode1_reset()functions. Add mode2_reset_is_support() for smu->ppt_funcs. Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
7c209847 |
|
03-Feb-2021 |
Takashi Iwai <tiwai@suse.de> |
drm/amd/display: Add a backlight module option There seem devices that don't work with the aux channel backlight control. For allowing such users to test with the other backlight control method, provide a new module option, aux_backlight, to specify enabling or disabling the aux backport support explicitly. As default, the aux support is detected by the hardware capability. v2: make the backlight option generic in case we add future backlight types (Alex) BugLink: https://bugzilla.opensuse.org/show_bug.cgi?id=1180749 BugLink: https://gitlab.freedesktop.org/drm/amd/-/issues/1438 Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Takashi Iwai <tiwai@suse.de> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
c79fe9b4 |
|
04-Mar-2021 |
Leo (Hanghong) Ma <hanghong.ma@amd.com> |
drm/amdgpu: add DMUB trace event IRQ source define [Why & How] We use DMCUB outbox0 interrupt to log DMCUB trace buffer events as Linux kernel traces, so need to add some irq source related defination in the header files; Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Leo (Hanghong) Ma <hanghong.ma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
6f786950 |
|
02-Feb-2021 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu/codec: drop the internal codec index And just use the ioctl index. They are the same. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
9269bf18 |
|
07-Jan-2021 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: add asic callback for querying video codec info (v3) This will be used by a new INFO ioctl query to fetch the decode and encode capabilities from the kernel driver rather than hardcoding them in mesa. This gives us more fine grained control of capabilities using information that is only availabl in the kernel (e.g., platform limitations or bandwidth restrictions). v2: reorder the codecs to better align with mesa v3: add max_pixels_per_frame to handle the portrait case Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> (v2) Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
0eb1af2e |
|
10-Dec-2020 |
Aurabindo Pillai <aurabindo.pillai@amd.com> |
drm/amd/display: Add module parameter for freesync video mode [Why] This option shall be opt-in by default since it is a temporary solution until long term solution is agreed upon which may require userspace interface changes. This feature give the user a seamless experience when freesync aware programs (media players for instance) switches to a compatible freesync mode when playing videos. Enabling this feature also have the potential side effect of causing higher power consumption due to running a mode with lower resolution and base clock frequency with the highest base clock supported on the monitor as per its advertised modes. There has been precedent of manufacturing modes in the kernel. In AMDGPU, the existing usage are for common modes and scaling modes. Other driver have a similar approach as well. [How] Adds a module parameter to enable freesync video mode modeset optimization. Enabling this mode allows the driver to skip a full modeset when a freesync compatible mode is requested by the userspace. This parameter will also add some additional modes that are within the connected monitor's VRR range corresponding to common video modes, which media players can use for a seamless experience while making use of freesync. Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Shashank Sharma <shashank.sharma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
b00978de |
|
21-Feb-2021 |
Prike Liang <Prike.Liang@amd.com> |
drm/amdgpu: fix shutdown and poweroff process failed with s0ix In the shutdown and poweroff opt on the s0i3 system we still need un-gate the gfx clock gating and power gating before destory amdgpu device. Fixes: 628c36d7b238e2 ("drm/amdgpu: update amdgpu device suspend/resume sequence for s0i3 support") Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1499 Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Prike Liang <Prike.Liang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
|
#
98d28ac2 |
|
15-Feb-2021 |
Nirmoy Das <nirmoy.das@amd.com> |
drm/amdgpu: do not use drm middle layer for debugfs Use debugfs API directly instead of drm middle layer. This also includes following debugfs file output changes: 1 amdgpu_evict_vram/amdgpu_evict_gtt output will not contain any braces. e.g. (0) --> 0 2 amdgpu_gpu_recover output will print return value of amdgpu_device_gpu_recover() instead of not so important "gpu recover" message. v2: * checkpatch.pl: use '0444' instead of S_IRUGO. * remove S_IFREG from mode. * remove mode variable. Signed-off-by: Nirmoy Das <nirmoy.das@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
88293c03 |
|
10-Feb-2021 |
Nirmoy Das <nirmoy.das@amd.com> |
drm/amdgpu: do not keep debugfs dentry Cleanup unnecessary debugfs dentries and surrounding functions. v3: remove return value check for debugfs_create_file() v2: remove ttm_debugfs_entries array. do not init variables. Signed-off-by: Nirmoy Das <nirmoy.das@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
8af8a109 |
|
01-Oct-2020 |
Christian König <christian.koenig@amd.com> |
drm/ttm: device naming cleanup Rename ttm_bo_device to ttm_device. Rename ttm_bo_driver to ttm_device_funcs. Rename ttm_bo_global to ttm_global. Move global and device related functions to ttm_device.[ch]. No functional change. Signed-off-by: Christian König <christian.koenig@amd.com> Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch> Link: https://patchwork.freedesktop.org/patch/415222/
|
#
8914089a |
|
12-Mar-2021 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: rework S3/S4/S0ix state handling Set flags at the top level pmops callbacks to track state. This cleans up the current set of flags and properly handles S4 on S0ix capable systems. Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
7a46f05e |
|
03-Feb-2021 |
Takashi Iwai <tiwai@suse.de> |
drm/amd/display: Add a backlight module option There seem devices that don't work with the aux channel backlight control. For allowing such users to test with the other backlight control method, provide a new module option, aux_backlight, to specify enabling or disabling the aux backport support explicitly. As default, the aux support is detected by the hardware capability. v2: make the backlight option generic in case we add future backlight types (Alex) BugLink: https://bugzilla.opensuse.org/show_bug.cgi?id=1180749 BugLink: https://gitlab.freedesktop.org/drm/amd/-/issues/1438 Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Takashi Iwai <tiwai@suse.de> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
|
#
b092b196 |
|
21-Feb-2021 |
Prike Liang <Prike.Liang@amd.com> |
drm/amdgpu: fix shutdown and poweroff process failed with s0ix In the shutdown and poweroff opt on the s0i3 system we still need un-gate the gfx clock gating and power gating before destory amdgpu device. Fixes: 628c36d7b238e2 ("drm/amdgpu: update amdgpu device suspend/resume sequence for s0i3 support") Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1499 Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Prike Liang <Prike.Liang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
|
#
006cc1a2 |
|
05-Feb-2021 |
Jiawei Gu <Jiawei.Gu@amd.com> |
drm/amdgpu: extend MAX_KIQ_REG_TRY to 1000 Extend retry times of KIQ to avoid starvation situation caused by long time full access of GPU by other VFs. Signed-off-by: Jiawei Gu <Jiawei.Gu@amd.com> Reviewed-by: Emily.Deng <Emily.Deng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
af484df8 |
|
04-Feb-2021 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: add generic pci reset as an option This allows us to use generic PCI reset mechanisms (FLR, SBR) as a reset mechanism to verify that the generic PCI reset mechanisms are working properly. Acked-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
11f1a553 |
|
28-Jan-2021 |
Wayne Lin <Wayne.Lin@amd.com> |
drm/amdgpu: Add otg vertical IRQ Source [Why & How] In order to get appropriate timing for registers which read/write is vertical line sensitive, add new IRQ source variable. This interrupt is triggered by specific vertical line, Signed-off-by: Wayne Lin <Wayne.Lin@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
455d40c9 |
|
28-Dec-2020 |
Likun Gao <Likun.Gao@amd.com> |
drm/amdgpu: switch hdp callback functions for hdp v4 Switch to use the HDP functions which unified on hdp structure instead of the scattered hdp callback functions. V2: clean up hdp reset ras error count function. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
b291a387 |
|
24-Dec-2020 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu: add amdgpu_hdp structure amdgpu_hdp hold all the callbacks for hdp Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Likun Gao <Likun.Gao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
5cf82904 |
|
17-Nov-2020 |
Christian König <christian.koenig@amd.com> |
drm/ttm/drivers: remove unecessary ttm_module.h include v2 ttm_module.h deals with internals of TTM and should never be include outside of it. v2: also move the file around Signed-off-by: Christian König <christian.koenig@amd.com> Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch> Link: https://patchwork.freedesktop.org/patch/404885/
|
#
b10c1c5b |
|
09-Dec-2020 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: add check for ACPI power resources Check if the device has ACPI power resources so we can enable runtime pm if so. Acked-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
fd496ca8 |
|
08-Dec-2020 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: split BOCO and ATPX handling In preparation for systems that support d3cold on dGPUs independent of PX/HG. No functional change intended. Acked-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
9ca5b8a1 |
|
15-Dec-2020 |
Likun Gao <Likun.Gao@amd.com> |
drm/amdgpu: add judgement for suspend/resume sequence S0ix only makes sense on APUs since they are part of the platform, so only when the ASIC is APU should set amdgpu_acpi_is_s0ix_supported flag to deal with the related situation. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
b1246bd4 |
|
09-Nov-2020 |
Luben Tuikov <luben.tuikov@amd.com> |
drm/amdgpu: Fix missing prototype warning Fix a missing prototype warning for function amdgpu_info_ioctl(), drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c:482:5: warning: no previous prototype for 'amdgpu_info_ioctl' [-Wmissing-prototypes] Signed-off-by: Luben Tuikov <luben.tuikov@amd.com> Reported-by: kernel test robot <lkp@intel.com> Reviewed-by: Souptick Joarder <jrdr.linux@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Link: https://patchwork.freedesktop.org/patch/msgid/20201110051548.685725-1-luben.tuikov@amd.com
|
#
4cd078dc |
|
08-Sep-2020 |
Prike Liang <Prike.Liang@amd.com> |
drm/amdgpu: add s0i3 capacity check for s0i3 routine (v2) add amdgpu_acpi_is_s0ix_supported() to check the platform whether support s0i3. v2: fix empty function parameters warning (void) Signed-off-by: Prike Liang <Prike.Liang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Acked-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
293f2563 |
|
07-Nov-2020 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu: add amdgpu_smuio structure Add amdgpu_smuio structure in amdgpu_device to provide various callback functions to support smuio ip funcitonality Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: John Clements <john.clements@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
02f40f82 |
|
05-Nov-2020 |
Lee Jones <lee.jones@linaro.org> |
gpu: drm: amd: amdgpu: amdgpu: Mark global variables as __maybe_unused These 3 variables are used in *some* sourcefiles which include amdgpu.h, but not *all*. This leads to a flurry of build warnings. Fixes the following W=1 kernel build warning(s): from drivers/gpu/drm/amd/amdgpu/amdgpu.h:67, drivers/gpu/drm/amd/amdgpu/amdgpu.h:198:19: warning: ‘no_system_mem_limit’ defined but not used [-Wunused-const-variable=] drivers/gpu/drm/amd/amdgpu/amdgpu.h:197:19: warning: ‘debug_evictions’ defined but not used [-Wunused-const-variable=] drivers/gpu/drm/amd/amdgpu/amdgpu.h:196:18: warning: ‘sched_policy’ defined but not used [-Wunused-const-variable=] NB: Repeats ~650 times - snipped for brevity. Cc: Alex Deucher <alexander.deucher@amd.com> Cc: "Christian König" <christian.koenig@amd.com> Cc: David Airlie <airlied@linux.ie> Cc: Daniel Vetter <daniel@ffwll.ch> Cc: Sumit Semwal <sumit.semwal@linaro.org> Cc: amd-gfx@lists.freedesktop.org Cc: dri-devel@lists.freedesktop.org Cc: linux-media@vger.kernel.org Cc: linaro-mm-sig@lists.linaro.org Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
73275181 |
|
24-Sep-2020 |
Evan Quan <evan.quan@amd.com> |
drm/amd/pm: correct the checks for polaris kickers By defining new Macros. Signed-off-by: Evan Quan <evan.quan@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
f2b75bc2 |
|
17-Aug-2020 |
Evan Quan <evan.quan@amd.com> |
drm/amd/pm: correct gfx and pcie settings on umd pstate switching(V2) For entering UMD stable Pstate, the operations to enter rlc_safe mode, disable mgcg_perfmon and disable PCIE aspm are needed. And the opposite operations should be performed on UMD stable Pstate exiting. V2: take those ASICs(CI/SI/VI) which may not support this into consideration Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
b4a7db71 |
|
01-Sep-2020 |
Jonathan Kim <jonathan.kim@amd.com> |
drm/amdgpu: add per device user friendly xgmi events for vega20 Non-outbound data metrics are non useful so mark them as legacy. Bucket new perf counters into device and not device ip. Bind events to chip instead of IP. Report available event counters and not number of hw counter banks. Move DF public macros to private since not needed outside of IP version. v5: cleanup by moving per chip configs into structs v4: After more discussion, replace *_LEGACY references with IP references to indicate concept of pmu-typed versus event-config-typed event registration. v3: attr groups const array is global but attr groups are allocated per device which doesn't work and causes problems on memory allocation and de-allocation for pmu unregister. Switch to building const attr groups per pmu instead to simplify solution. v2: add comments on sysfs structure and formatting. Signed-off-by: Jonathan Kim <jonathan.kim@amd.com> Reviewed-by: Harish Kasiviswanathan <harish.kasiviswanathan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
f7ee1874 |
|
18-Sep-2020 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu: support indirect access reg outside of mmio bar (v2) support both direct and indirect accessor in unified helper functions. v2: Retire indirect mmio access via mm_index/data Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Guchun Chen <guchun.chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
1bba3683 |
|
17-Sep-2020 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu: add helper function for indirect reg access (v3) Add helper function in order to remove RREG32/WREG32 in current pcie_rreg/wreg function for soc15 and onwards adapters. PCIE_INDEX/DATA pairs are used to access regsiters outside of mmio bar in the helper functions. The new helper functions help remove the recursion of amdgpu_mm_rreg/wreg from pcie_rreg/wreg and provide the oppotunity to centralize direct and indirect access in a single function. v2: Fixed typo and refine the comments v3: Remove unnecessary volatile local variable Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Guchun Chen <guchun.chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
8ffff9b4 |
|
17-Sep-2020 |
Oak Zeng <Oak.Zeng@amd.com> |
drm/amdgpu: use function pointer for gfxhub functions gfxhub functions are now called from function pointers, instead of from asic-specific functions. Signed-off-by: Oak Zeng <Oak.Zeng@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
c1dd4aa6 |
|
23-Aug-2020 |
Andrey Grodzovsky <andrey.grodzovsky@amd.com> |
drm/amdgpu: Fix consecutive DPC recovery failures. Cache the PCI state on boot and before each case where we might loose it. v2: Add pci_restore_state while caching the PCI state to avoid breaking PCI core logic for stuff like suspend/resume. v3: Extract pci_restore_state from amdgpu_device_cache_pci_state to avoid superflous restores during GPU resets and suspend/resumes. v4: Style fixes. Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
bf36b52e |
|
29-Jul-2020 |
Andrey Grodzovsky <andrey.grodzovsky@amd.com> |
drm/amdgpu: Avoid accessing HW when suspending SW state At this point the ASIC is already post reset by the HW/PSP so the HW not in proper state to be configured for suspension, some blocks might be even gated and so best is to avoid touching it. v2: Rename in_dpc to more meaningful name Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
c9a6b82f |
|
28-Jul-2020 |
Andrey Grodzovsky <andrey.grodzovsky@amd.com> |
drm/amdgpu: Implement DPC recovery Add PCI Downstream Port Containment (DPC) with basic recovery functionality v2: remove pci_save_state to avoid breaking suspend/resume v3: Fix style comments v4: Improve description. Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
5436ab94 |
|
17-Aug-2020 |
Stanley.Yang <Stanley.Yang@amd.com> |
drm/amdkfd: fix set kfd node ras properties value The ctx->features are new RAS implementation which is only available for Vega20 and onwards, it is not available for vega10, vega10 should follow legacy ECC implementation. Changed from V1: wrap function to initialize kfd node properties Changed from V2: remove wrap function and SDMA SRAM ECC check Signed-off-by: Stanley.Yang <Stanley.Yang@amd.com> Reviewed-by: Guchun Chen <guchun.chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
9737a923 |
|
19-Aug-2020 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: add an asic callback for pre asic init This callback can be used by asics that need to do something special prior to calling atom asic init. Acked-by: Nirmoy Das <nirmoy.das@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
8aba21b7 |
|
14-Aug-2020 |
Luben Tuikov <luben.tuikov@amd.com> |
drm/amdgpu: Embed drm_device into amdgpu_device (v3) a) Embed struct drm_device into struct amdgpu_device. b) Modify the inline-f drm_to_adev() accordingly. c) Modify the inline-f adev_to_drm() accordingly. d) Eliminate the use of drm_device.dev_private, in amdgpu. e) Switch from using drm_dev_alloc() to drm_dev_init(). f) Add a DRM driver release function, which frees the container amdgpu_device after all krefs on the contained drm_device have been released. v2: Split out adding adev_to_drm() into its own patch (previous commit), making this patch more succinct and clear. More detailed commit description. v3: squash in fix to call drmm_add_final_kfree() to avoid a warning. Signed-off-by: Luben Tuikov <luben.tuikov@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
4a580877 |
|
23-Aug-2020 |
Luben Tuikov <luben.tuikov@amd.com> |
drm/amdgpu: Get DRM dev from adev by inline-f Add a static inline adev_to_drm() to obtain the DRM device pointer from an amdgpu_device pointer. Signed-off-by: Luben Tuikov <luben.tuikov@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
1348969a |
|
23-Aug-2020 |
Luben Tuikov <luben.tuikov@amd.com> |
drm/amdgpu: drm_device to amdgpu_device by inline-f (v2) Get the amdgpu_device from the DRM device by use of an inline function, drm_to_adev(). The inline function resolves a pointer to struct drm_device to a pointer to struct amdgpu_device. v2: Use a typed visible static inline function instead of an invisible macro. Signed-off-by: Luben Tuikov <luben.tuikov@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
d95e8e97 |
|
18-Aug-2020 |
Dennis Li <Dennis.Li@amd.com> |
drm/amdgpu: refine create and release logic of hive info Change to dynamically create and release hive info object, which help driver support more hives in the future. v2: Change to save hive object pointer in adev, to avoid locking xgmi_mutex every time when calling amdgpu_get_xgmi_hive. v3: 1. Change type of hive object pointer in adev from void* to amdgpu_hive_info*. 2. remove unnecessary variable initialization. Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Dennis Li <Dennis.Li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
6049db43 |
|
19-Aug-2020 |
Dennis Li <Dennis.Li@amd.com> |
drm/amdgpu: change reset lock from mutex to rw_semaphore clients don't need reset-lock for synchronization when no GPU recovery. v2: change to return the return value of down_read_killable. v3: if GPU recovery begin, VF ignore FLR notification. Reviewed-by: Monk Liu <monk.liu@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Dennis Li <Dennis.Li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
53b3f8f4 |
|
19-Aug-2020 |
Dennis Li <Dennis.Li@amd.com> |
drm/amdgpu: refine codes to avoid reentering GPU recovery if other threads have holden the reset lock, recovery will fail to try_lock. Therefore we introduce atomic hive->in_reset and adev->in_gpu_reset, to avoid reentering GPU recovery. v2: drop "? true : false" in the definition of amdgpu_in_reset Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Dennis Li <Dennis.Li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
9a1cddd6 |
|
07-Aug-2020 |
jqdeng <Emily.Deng@amd.com> |
drm/amdgpu: Fix repeatly flr issue Only for no job running test case need to do recover in flr notification. For having job in mirror list, then let guest driver to hit job timeout, and then do recover. Signed-off-by: jqdeng <Emily.Deng@amd.com> Acked-by: Nirmoy Das <nirmoy.das@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
f1403342 |
|
12-Aug-2020 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: revert "fix system hang issue during GPU reset" The whole approach wasn't thought through till the end. We already had a reset lock like this in the past and it caused the same problems like this one. Completely revert the patch for now and add individual trylock protection to the hardware access functions as necessary. This reverts commit df9c8d1aa278c435c30a69b8f2418b4a52fcb929. Signed-off-by: Christian König <christian.koenig@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
b80f050f |
|
27-Jul-2020 |
Philip Yang <Philip.Yang@amd.com> |
drm/amdkfd: option to disable system mem limit If multiple process share system memory through /dev/shm, KFD allocate memory should not fail if it reaches the system memory limit because one copy of physical system memory are shared by multiple process. Add module parameter no_system_mem_limit to provide user option to disable system memory limit check at runtime using sysfs or during driver module init using kernel boot argument. By default the system memory limit is on. Print out debug message to warn user if KFD allocate memory failed because system memory reaches limit. Signed-off-by: Philip Yang <Philip.Yang@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
87ded5ca |
|
29-Jul-2020 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: move vram usage by vbios to mman (v2) It's related to the memory manager so move it there. v2: inline the structure Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
72de33f8 |
|
29-Jul-2020 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: move IP discovery data to mman It's related to the memory manager so move it there. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
fcbc92e2 |
|
28-Jul-2020 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: move stolen vga bo from amdgpu to amdgpu.gmc Since that is where we store the other data related to the stolen vga memory. Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
81b54fb7 |
|
28-Jul-2020 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: use a define for the memory size of the vga emulator Rather than open coding it everywhere. Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
a300de40 |
|
27-Jul-2020 |
Monk Liu <Monk.Liu@amd.com> |
drm/amdgpu: introduce a new parameter to configure how many KCQ we want(v5) what: the MQD's save and restore of KCQ (kernel compute queue) cost lots of clocks during world switch which impacts a lot to multi-VF performance how: introduce a paramter to control the number of KCQ to avoid performance drop if there is no kernel compute queue needed notes: this paramter only affects gfx 8/9/10 v2: refine namings v3: choose queues for each ring to that try best to cross pipes evenly. v4: fix indentation some cleanupsin the gfx_compute_queue_acquire() v5: further fix on indentations more cleanupsin gfx_compute_queue_acquire() TODO: in the future we will let hypervisor driver to set this paramter automatically thus no need for user to configure it through modprobe in virtual machine Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
acc0204c |
|
21-Jul-2020 |
Guchun Chen <guchun.chen@amd.com> |
drm/amdgpu: add bad page count threshold in module parameter(v3) bad_page_threshold could be configured to enable/disable the associated bad page retirement feature in RAS. When it's -1, ras will use typical bad page failure value to handle bad page retirement. When it's 0, disable bad page retirement, and no bad page will be recorded and saved. For other valid value, driver will use this manual value as the threshold value of totoal bad pages. v2: correct documentation of this parameter. v3: remove confused statement in documentation. Signed-off-by: Guchun Chen <guchun.chen@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
df9c8d1a |
|
08-Jul-2020 |
Dennis Li <Dennis.Li@amd.com> |
drm/amdgpu: fix system hang issue during GPU reset when GPU hang, driver has multi-paths to enter amdgpu_device_gpu_recover, the atomic adev->in_gpu_reset and hive->in_reset are used to avoid re-entering GPU recovery. During GPU reset and resume, it is unsafe that other threads access GPU, which maybe cause GPU reset failed. Therefore the new rw_semaphore adev->reset_sem is introduced, which protect GPU from being accessed by external threads during recovery. v2: 1. add rwlock for some ioctls, debugfs and file-close function. 2. change to use dqm->is_resetting and dqm_lock for protection in kfd driver. 3. remove try_lock and change adev->in_gpu_reset as atomic, to avoid re-enter GPU recovery for the same GPU hang. v3: 1. change back to use adev->reset_sem to protect kfd callback functions, because dqm_lock couldn't protect all codes, for example: free_mqd must be called outside of dqm_lock; [ 1230.176199] Hardware name: Supermicro SYS-7049GP-TRT/X11DPG-QT, BIOS 3.1 05/23/2019 [ 1230.177221] Call Trace: [ 1230.178249] dump_stack+0x98/0xd5 [ 1230.179443] amdgpu_virt_kiq_reg_write_reg_wait+0x181/0x190 [amdgpu] [ 1230.180673] gmc_v9_0_flush_gpu_tlb+0xcc/0x310 [amdgpu] [ 1230.181882] amdgpu_gart_unbind+0xa9/0xe0 [amdgpu] [ 1230.183098] amdgpu_ttm_backend_unbind+0x46/0x180 [amdgpu] [ 1230.184239] ? ttm_bo_put+0x171/0x5f0 [ttm] [ 1230.185394] ttm_tt_unbind+0x21/0x40 [ttm] [ 1230.186558] ttm_tt_destroy.part.12+0x12/0x60 [ttm] [ 1230.187707] ttm_tt_destroy+0x13/0x20 [ttm] [ 1230.188832] ttm_bo_cleanup_memtype_use+0x36/0x80 [ttm] [ 1230.189979] ttm_bo_put+0x1be/0x5f0 [ttm] [ 1230.191230] amdgpu_bo_unref+0x1e/0x30 [amdgpu] [ 1230.192522] amdgpu_amdkfd_free_gtt_mem+0xaf/0x140 [amdgpu] [ 1230.193833] free_mqd+0x25/0x40 [amdgpu] [ 1230.195143] destroy_queue_cpsch+0x1a7/0x270 [amdgpu] [ 1230.196475] pqm_destroy_queue+0x105/0x260 [amdgpu] [ 1230.197819] kfd_ioctl_destroy_queue+0x37/0x70 [amdgpu] [ 1230.199154] kfd_ioctl+0x277/0x500 [amdgpu] [ 1230.200458] ? kfd_ioctl_get_clock_counters+0x60/0x60 [amdgpu] [ 1230.201656] ? tomoyo_file_ioctl+0x19/0x20 [ 1230.202831] ksys_ioctl+0x98/0xb0 [ 1230.204004] __x64_sys_ioctl+0x1a/0x20 [ 1230.205174] do_syscall_64+0x5f/0x250 [ 1230.206339] entry_SYSCALL_64_after_hwframe+0x49/0xbe 2. remove try_lock and introduce atomic hive->in_reset, to avoid re-enter GPU recovery. v4: 1. remove an unnecessary whitespace change in kfd_chardev.c 2. remove comment codes in amdgpu_device.c 3. add more detailed comment in commit message 4. define a wrap function amdgpu_in_reset v5: 1. Fix some style issues. Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Suggested-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Suggested-by: Christian König <christian.koenig@amd.com> Suggested-by: Felix Kuehling <Felix.Kuehling@amd.com> Suggested-by: Lijo Lazar <Lijo.Lazar@amd.com> Suggested-by: Luben Tukov <luben.tuikov@amd.com> Signed-off-by: Dennis Li <Dennis.Li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
273da6ff |
|
14-Jul-2020 |
Wenhui Sheng <Wenhui.Sheng@amd.com> |
drm/amdgpu: add module parameter choose reset mode Default value is auto, doesn't change original reset method logic. v2: change to use parameter reset_method v3: add warn msg if specified mode isn't supported Signed-off-by: Likun Gao <Likun.Gao@amd.com> Signed-off-by: Wenhui Sheng <Wenhui.Sheng@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
e78b579d |
|
30-Jun-2020 |
Hawking Zhang <Hawking.Zhang@amd.com> |
Revert "drm/amdgpu: support access regs outside of mmio bar" This reverts commit 2eee0229f65e897134566888e5321bcb3af0df7a. Fallback to a stable base until we have a correct new one Signed-off-by:Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
fb40bceb |
|
23-Jun-2020 |
Alex Jivin <alex.jivin@amd.com> |
drm/amdgpu: SI support for VCE clock control Port functionality from the Radeon driver to support VCE clock control. Signed-off-by: Alex Jivin <alex.jivin@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
b2057956 |
|
11-Jun-2020 |
Felix Kuehling <Felix.Kuehling@amd.com> |
drm/amdkfd: Add eviction debug messages Use WARN to print messages with backtrace when evictions are triggered. This can help determine the root cause of evictions and help spot driver bugs triggering evictions unintentionally, or help with performance tuning by avoiding conditions that cause evictions in a specific workload. The messages are controlled by a new module parameter that can be changed at runtime: echo Y > /sys/module/amdgpu/parameters/debug_evictions echo N > /sys/module/amdgpu/parameters/debug_evictions Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Philip Yang <Philip.Yang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
8df1a28f |
|
10-Jun-2020 |
Dan Carpenter <dan.carpenter@oracle.com> |
drm/amdgpu: Fix a buffer overflow handling the serial number The comments say that the serial number is a 16-digit HEX string so the buffer needs to be at least 17 characters to hold the NUL terminator. The other issue is that "size" returned from sprintf() is the number of characters before the NUL terminator so the memcpy() wasn't copying the terminator. The serial number needs to be NUL terminated so that it doesn't lead to a read overflow in amdgpu_device_get_serial_number(). Also it's just cleaner and faster to sprintf() directly to adev->serial[] instead of using a temporary buffer. Fixes: 81a16241114b ("drm/amdgpu: Add unique_id and serial_number for Arcturus v3") Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com>
|
#
72d208c2 |
|
22-May-2020 |
Likun Gao <Likun.Gao@amd.com> |
drm/amdgpu: remove unnecessary check for mem train a.Check whether mem train support when try to reserve related memory. b.Remove ASIC check and atom firmware table version check as the check of firmware capability is enough to achieve that purpose. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
b265bdbd |
|
22-May-2020 |
Evan Quan <evan.quan@amd.com> |
drm/amdgpu: added a sysfs interface for thermal throttling related V4 User can check and set the enablement of throttling logging and the interval between each logging. V2: simplify the sysfs interface(no string parsing) V3: add proper lock protection on updating throttling_logging_rs.interval V4: documentation cosmetic per Luben's suggestion Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Luben Tuikov <luben.tuikov@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
54f78a76 |
|
15-May-2020 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: add apu flags (v2) Add some APU flags to simplify handling of different APU variants. It's easier to understand the special cases if we use names flags rather than checking device ids and silicon revisions. v2: rebase on latest code Acked-by: Evan Quan <evan.quan@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
8a791dab |
|
01-May-2020 |
Harry Wentland <harry.wentland@amd.com> |
drm/amd/display: Add DC Debug mask to disable features for bringup [Why] At bringup we want to be able to disable various power features. [How] These features are already exposed as dc_debug_options and exercised on other OSes. Create a new dc_debug_mask module parameter and expose relevant bits, in particular * DC_DISABLE_PIPE_SPLIT * DC_DISABLE_STUTTER * DC_DISABLE_DSC * DC_DISABLE_CLOCK_GATING Signed-off-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
728e7e0c |
|
26-Apr-2020 |
Jiange Zhao <Jiange.Zhao@amd.com> |
drm/amdgpu: Add autodump debugfs node for gpu reset v8 When GPU got timeout, it would notify an interested part of an opportunity to dump info before actual GPU reset. A usermode app would open 'autodump' node under debugfs system and poll() for readable/writable. When a GPU reset is due, amdgpu would notify usermode app through wait_queue_head and give it 10 minutes to dump info. After usermode app has done its work, this 'autodump' node is closed. On node closure, amdgpu gets to know the dump is done through the completion that is triggered in release(). There is no write or read callback because necessary info can be obtained through dmesg and umr. Messages back and forth between usermode app and amdgpu are unnecessary. v2: (1) changed 'registered' to 'app_listening' (2) add a mutex in open() to prevent race condition v3 (chk): grab the reset lock to avoid race in autodump_open, rename debugfs file to amdgpu_autodump, provide autodump_read as well, style and code cleanups v4: add 'bool app_listening' to differentiate situations, so that the node can be reopened; also, there is no need to wait for completion when no app is waiting for a dump. v5: change 'bool app_listening' to 'enum amdgpu_autodump_state' add 'app_state_mutex' for race conditions: (1)Only 1 user can open this file node (2)wait_dump() can only take effect after poll() executed. (3)eliminated the race condition between release() and wait_dump() v6: removed 'enum amdgpu_autodump_state' and 'app_state_mutex' removed state checking in amdgpu_debugfs_wait_dump Improve on top of version 3 so that the node can be reopened. v7: move reinit_completion into open() so that only one user can open it. v8: remove complete_all() from amdgpu_debugfs_wait_dump(). Signed-off-by: Jiange Zhao <Jiange.Zhao@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
b2b6290a |
|
07-May-2020 |
Evan Quan <evan.quan@amd.com> |
drm/amdgpu: enable hibernate support on Navi1X BACO is needed to support hibernate on Navi1X. Signed-off-by: Evan Quan <evan.quan@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
|
#
85625e64 |
|
07-May-2020 |
Evan Quan <evan.quan@amd.com> |
drm/amdgpu: enable hibernate support on Navi1X BACO is needed to support hibernate on Navi1X. Signed-off-by: Evan Quan <evan.quan@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
e0c116c1 |
|
31-Mar-2020 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu: re-structue members for ip discovery This is to prepare for initializing discovery tmr size per ASIC type Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Likun Gao <Likun.Gao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
9ecefb19 |
|
01-Apr-2020 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: cleanup IB pool handling a bit Fix the coding style, move and rename the definitions to better match what they are supposed to be doing. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
c6252390 |
|
19-Mar-2020 |
Luben Tuikov <luben.tuikov@amd.com> |
drm/amdgpu: implement TMZ accessor (v3) Implement an accessor of adev->tmz.enabled. Let not code around access it as "if (adev->tmz.enabled)" as the organization may change. Instead... Recruit "bool amdgpu_is_tmz(adev)" to return exactly this Boolean value. That is, this function is now an accessor of an already initialized and set adev and adev->tmz. Add "void amdgpu_gmc_tmz_set(adev)" to check and set adev->gmc.tmz_enabled at initialization time. After which one uses "bool amdgpu_is_tmz(adev)" to query whether adev supports TMZ. Also, remove circular header file include. v2: Remove amdgpu_tmz.[ch] as requested. v3: Move TMZ into GMC. Signed-off-by: Luben Tuikov <luben.tuikov@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
ae60305a |
|
14-Jan-2020 |
Huang Rui <ray.huang@amd.com> |
drm/amdgpu: add amdgpu_tmz data structure This patch to add amdgpu_tmz structure which stores all tmz related fields. Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
d7ccb38d |
|
04-Aug-2019 |
Huang Rui <ray.huang@amd.com> |
drm/amdgpu: add tmz feature parameter (v2) This patch adds tmz parameter to enable/disable the feature in the amdgpu kernel module. Nomally, by default, it should be auto (rely on the hardware capability). But right now, it need to set "off" to avoid breaking other developers' work because it's not totally completed. Will set "auto" till the feature is stable and completely verified. v2: add "auto" option for future use. Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
54208194 |
|
22-Apr-2020 |
Yintian Tao <yttao@amd.com> |
drm/amdgpu: request reg_val_offs each kiq read reg According to the current kiq read register method, there will be race condition when using KIQ to read register if multiple clients want to read at same time just like the expample below: 1. client-A start to read REG-0 throguh KIQ 2. client-A poll the seqno-0 3. client-B start to read REG-1 through KIQ 4. client-B poll the seqno-1 5. the kiq complete these two read operation 6. client-A to read the register at the wb buffer and get REG-1 value Therefore, use amdgpu_device_wb_get() to request reg_val_offs for each kiq read register. v2: fix the error remove v3: fix the print typo v4: remove unused variables Signed-off-by: Yintian Tao <yttao@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
e05185b3 |
|
20-Apr-2020 |
Kevin Wang <kevin1.wang@amd.com> |
drm/amdgpu: clean up unused variable about ring lru clean up unused variable: 1. ring_lru_list 2. ring_lru_list_lock related-commit: drm/amdgpu: remove ring lru handling Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
d84a430d |
|
17-Mar-2020 |
Jonathan Kim <jonathan.kim@amd.com> |
drm/amdgpu: fix race between pstate and remote buffer map Vega20 arbitrates pstate at hive level and not device level. Last peer to remote buffer unmap could drop P-State while another process is still remote buffer mapped. With this fix, P-States still needs to be disabled for now as SMU bug was discovered on synchronous P2P transfers. This should be fixed in the next FW update. Signed-off-by: Jonathan Kim <Jonathan.Kim@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
539489fc |
|
08-Apr-2020 |
Aurabindo Pillai <mail@aurabindo.in> |
drm/amd/amdgpu: add print prefix for dev_* variants Define dev_fmt macro for informative print messages Signed-off-by: Aurabindo Pillai <mail@aurabindo.in> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
d57229b1 |
|
08-Apr-2020 |
Aurabindo Pillai <mail@aurabindo.in> |
drm/amd/amdgpu: add prefix for pr_* prints amdgpu uses lots of pr_* calls for printing error messages. With this prefix, errors shall be more obvious to the end use regarding its origin, and may help debugging. Prefix format: [xxx.xxxxx] amdgpu: ... Signed-off-by: Aurabindo Pillai <mail@aurabindo.in> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
2eee0229 |
|
08-Apr-2020 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu: support access regs outside of mmio bar add indirect access support to registers outside of mmio bar. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
f384ff95 |
|
03-Apr-2020 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu: retire AMDGPU_REGS_KIQ flag all the register access through kiq is redirected to amdgpu_kiq_rreg/amdgpu_kiq_wreg Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
ec59847e |
|
03-Apr-2020 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu: retire RREG32_IDX/WREG32_IDX those are not needed anymore Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
dec0520a |
|
03-Apr-2020 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu: remove inproper workaround for vega10 the workaround is not needed for soc15 ASICs except for vega10. it is even not needed with latest vega10 vbios. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
1c6d567b |
|
01-Apr-2020 |
Nirmoy Das <nirmoy.das@amd.com> |
drm/amdgpu: rework sched_list generation Generate HW IP's sched_list in amdgpu_ring_init() instead of amdgpu_ctx.c. This makes amdgpu_ctx_init_compute_sched(), ring.has_high_prio and amdgpu_ctx_init_sched() unnecessary. This patch also stores sched_list for all HW IPs in one big array in struct amdgpu_device which makes amdgpu_ctx_init_entity() much more leaner. v2: fix a coding style issue do not use drm hw_ip const to populate amdgpu_ring_type enum v3: remove ctx reference and move sched array and num_sched to a struct use num_scheds to detect uninitialized scheduler list v4: use array_index_nospec for user space controlled variables fix possible checkpatch.pl warnings Signed-off-by: Nirmoy Das <nirmoy.das@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
c8e42d57 |
|
25-Mar-2020 |
xinhui pan <xinhui.pan@amd.com> |
drm/amdgpu: implement more ib pools (v2) We have three ib pools, they are normal, VM, direct pools. Any jobs which schedule IBs without dependence on gpu scheduler should use DIRECT pool. Any jobs schedule direct VM update IBs should use VM pool. Any other jobs use NORMAL pool. v2: squash in coding style fix Signed-off-by: xinhui pan <xinhui.pan@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
bd607166 |
|
13-Mar-2020 |
Kent Russell <kent.russell@amd.com> |
drm/amdgpu: Enable reading FRU chip via I2C v3 Allow for reading of information like manufacturer, product number and serial number from the FRU chip. Report the serial number as the new sysfs file serial_number. Note that this only works on server cards, as consumer cards do not feature the FRU chip, which contains this information. v2: Add documentation to amdgpu.rst, add helper functions, rename functions for consistency, fix bad starting offset v3: Remove testing definitions Signed-off-by: Kent Russell <kent.russell@amd.com> Reviewed-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
2e0cc4d4 |
|
10-Mar-2020 |
Monk Liu <Monk.Liu@amd.com> |
drm/amdgpu: revise RLCG access path what changed: 1)provide new implementation interface for the rlcg access path 2)put SQ_CMD/SQ_IND_INDEX to GFX9 RLCG path to let debugfs's reg_op function can access reg that need RLCG path help now even debugfs's reg_op can used to dump wave. tested-by: Monk Liu <monk.liu@amd.com> tested-by: Zhou pengju <pengju.zhou@amd.com> Signed-off-by: Zhou pengju <pengju.zhou@amd.com> Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Emily Deng <Emily.Deng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
4a89ad9b |
|
02-Mar-2020 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu: add reset_ras_error_count function for HDP HDP ras error counters are dirty ones after cold reboot Read operation is needed to reset them to 0 Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Guchun Chen <guchun.chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
e3eff4b5 |
|
23-Jan-2020 |
Thomas Zimmermann <tzimmermann@suse.de> |
drm/amdgpu: Convert to CRTC VBLANK callbacks VBLANK callbacks in struct drm_driver are deprecated in favor of their equivalents in struct drm_crtc_funcs. Convert amdgpu over. v2: * don't wrap existing functions; change signature instead Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200123135943.24140-6-tzimmermann@suse.de
|
#
f0f7ddfc |
|
07-Feb-2020 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: add flag for runtime suspend So we know whether we in are in runtime suspend or system suspend. Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
c68dbcd8 |
|
14-Jan-2020 |
chen gong <curry.gong@amd.com> |
drm/amdgpu: add kiq version interface for RREG32/WREG32 Reading some registers by mmio will result in hang when GPU is in "gfxoff" state.This problem can be solved by GPU in "ring command packages" way. Signed-off-by: chen gong <curry.gong@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
bdf84a80 |
|
14-Jan-2020 |
Joseph Greathouse <Joseph.Greathouse@amd.com> |
drm/amdgpu: Create generic DF struct in adev The only data fabric information the adev struct currently contains is a function pointer table. In the near future, we will be adding some cached DF information into adev. As such, this patch creates a new amdgpu_df struct for adev. Right now, it only containst the old function pointer table, but new stuff will be added soon. Signed-off-by: Joseph Greathouse <Joseph.Greathouse@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
8d40002f |
|
16-Dec-2019 |
Tianci.Yin <tianci.yin@amd.com> |
drm/amdgpu: update the method to get fb_loc of memory training(V4) The method of getting fb_loc changed from parsing VBIOS to taking certain offset from top of VRAM Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Tianci.Yin <tianci.yin@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
041a62bc |
|
06-Dec-2019 |
Andrey Grodzovsky <andrey.grodzovsky@amd.com> |
drm/amdgpu: reverts commit ce316fa55ef0f1751276b846a54fb3b835bd5e64. In preparation for doing XGMI reset synchronization using task barrier. Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by: Le Ma <Le.Ma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
ce316fa5 |
|
26-Nov-2019 |
Le Ma <le.ma@amd.com> |
drm/amdgpu: add concurrent baco reset support for XGMI Currently each XGMI node reset wq does not run in parrallel if bound to same cpu. Make change to bound the xgmi_reset_work item to different cpus. XGMI requires all nodes enter into baco within very close proximity before any node exit baco. So schedule the xgmi_reset_work wq twice for enter/exit baco respectively. To use baco for XGMI, PMFW supported for baco on XGMI needs to be involved. The case that PSP reset and baco reset coexist within an XGMI hive never exist and is not in the consideration. v2: define use_baco flag to simplify the code for xgmi baco sequence Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
7c868b59 |
|
29-Nov-2019 |
Yintian Tao <yttao@amd.com> |
drm/amdgpu: not remove sysfs if not create sysfs When load amdgpu failed before create pm_sysfs and ucode_sysfs, the pm_sysfs and ucode_sysfs should not be removed. Otherwise, there will be warning call trace just like below. [ 24.836386] [drm] VCE initialized successfully. [ 24.841352] amdgpu 0000:00:07.0: amdgpu_device_ip_init failed [ 25.370383] amdgpu 0000:00:07.0: Fatal error during GPU init [ 25.889575] [drm] amdgpu: finishing device. [ 26.069128] amdgpu 0000:00:07.0: [drm:amdgpu_ring_test_helper [amdgpu]] *ERROR* ring kiq_2.1.0 test failed (-110) [ 26.070110] [drm:gfx_v9_0_hw_fini [amdgpu]] *ERROR* KCQ disable failed [ 26.200309] [TTM] Finalizing pool allocator [ 26.200314] [TTM] Finalizing DMA pool allocator [ 26.200349] [TTM] Zone kernel: Used memory at exit: 0 KiB [ 26.200351] [TTM] Zone dma32: Used memory at exit: 0 KiB [ 26.200353] [drm] amdgpu: ttm finalized [ 26.205329] ------------[ cut here ]------------ [ 26.205330] sysfs group 'fw_version' not found for kobject '0000:00:07.0' [ 26.205347] WARNING: CPU: 0 PID: 1228 at fs/sysfs/group.c:256 sysfs_remove_group+0x80/0x90 [ 26.205348] Modules linked in: amdgpu(OE+) gpu_sched(OE) ttm(OE) drm_kms_helper(OE) drm(OE) i2c_algo_bit fb_sys_fops syscopyarea sysfillrect sysimgblt rpcsec_gss_krb5 auth_rpcgss nfsv4 nfs lockd grace fscache binfmt_misc snd_hda_codec_generic ledtrig_audio crct10dif_pclmul snd_hda_intel crc32_pclmul snd_hda_codec ghash_clmulni_intel snd_hda_core snd_hwdep snd_pcm snd_timer input_leds snd joydev soundcore serio_raw pcspkr evbug aesni_intel aes_x86_64 crypto_simd cryptd mac_hid glue_helper sunrpc ip_tables x_tables autofs4 8139too psmouse 8139cp mii i2c_piix4 pata_acpi floppy [ 26.205369] CPU: 0 PID: 1228 Comm: modprobe Tainted: G OE 5.2.0-rc1 #1 [ 26.205370] Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS Ubuntu-1.8.2-1ubuntu1 04/01/2014 [ 26.205372] RIP: 0010:sysfs_remove_group+0x80/0x90 [ 26.205374] Code: e8 35 b9 ff ff 5b 41 5c 41 5d 5d c3 48 89 df e8 f6 b5 ff ff eb c6 49 8b 55 00 49 8b 34 24 48 c7 c7 48 7a 70 98 e8 60 63 d3 ff <0f> 0b eb d7 66 90 66 2e 0f 1f 84 00 00 00 00 00 0f 1f 44 00 00 55 [ 26.205375] RSP: 0018:ffffbee242b0b908 EFLAGS: 00010282 [ 26.205376] RAX: 0000000000000000 RBX: 0000000000000000 RCX: 0000000000000006 [ 26.205377] RDX: 0000000000000007 RSI: 0000000000000092 RDI: ffff97ad6f817380 [ 26.205377] RBP: ffffbee242b0b920 R08: ffffffff98f520c4 R09: 00000000000002b3 [ 26.205378] R10: ffffbee242b0b8f8 R11: 00000000000002b3 R12: ffffffffc0e58240 [ 26.205379] R13: ffff97ad6d1fe0b0 R14: ffff97ad4db954c8 R15: ffff97ad4db7fff0 [ 26.205380] FS: 00007ff3d8a1c4c0(0000) GS:ffff97ad6f800000(0000) knlGS:0000000000000000 [ 26.205381] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 26.205381] CR2: 00007f9b2ef1df04 CR3: 000000042aab8001 CR4: 00000000003606f0 [ 26.205384] DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000 [ 26.205385] DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400 [ 26.205385] Call Trace: [ 26.205461] amdgpu_ucode_sysfs_fini+0x18/0x20 [amdgpu] [ 26.205518] amdgpu_device_fini+0x3b4/0x560 [amdgpu] [ 26.205573] amdgpu_driver_unload_kms+0x4f/0xa0 [amdgpu] [ 26.205623] amdgpu_driver_load_kms+0xcd/0x250 [amdgpu] [ 26.205637] drm_dev_register+0x12b/0x1c0 [drm] [ 26.205695] amdgpu_pci_probe+0x12a/0x1e0 [amdgpu] [ 26.205699] local_pci_probe+0x47/0xa0 [ 26.205701] pci_device_probe+0x106/0x1b0 [ 26.205704] really_probe+0x21a/0x3f0 [ 26.205706] driver_probe_device+0x11c/0x140 [ 26.205707] device_driver_attach+0x58/0x60 [ 26.205709] __driver_attach+0xc3/0x140 Signed-off-by: Yintian Tao <yttao@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Nirmoy Das <nirmoy.das@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
de185019 |
|
20-Nov-2019 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: move pci handling out of pm ops The documentation says the that PCI core handles this for you unless you choose to implement it. Just rely on the PCI core to handle the pci specific bits. Reviewed-by: Zhan Liu <zhan.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
62914a99 |
|
12-Nov-2019 |
Jason Gunthorpe <jgg@ziepe.ca> |
drm/amdgpu: Use mmu_interval_insert instead of hmm_mirror Remove the interval tree in the driver and rely on the tree maintained by the mmu_notifier for delivering mmu_notifier invalidation callbacks. For some reason amdgpu has a very complicated arrangement where it tries to prevent duplicate entries in the interval_tree, this is not necessary, each amdgpu_bo can be its own stand alone entry. interval_tree already allows duplicates and overlaps in the tree. Also, there is no need to remove entries upon a release callback, the mmu_interval API safely allows objects to remain registered beyond the lifetime of the mm. The driver only has to stop touching the pages during release. Link: https://lore.kernel.org/r/20191112202231.3856-12-jgg@ziepe.ca Reviewed-by: Philip Yang <Philip.Yang@amd.com> Tested-by: Philip Yang <Philip.Yang@amd.com> Signed-off-by: Jason Gunthorpe <jgg@mellanox.com>
|
#
6ae6c7d4 |
|
07-Nov-2019 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: start to disentangle boco from runtime pm BACO - Bus Active, Chip Off BOCO - Bus Off, Chip Off We originally only supported runtime pm on PX/HG laptops so most of the runtime pm code looks for this. Add a new flag to check for runtime pm enablement and use this rather than checking for PX/HG. Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
361dbd01 |
|
03-Oct-2019 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: add helpers for baco entry and exit BACO - Bus Active, Chip Off Will be used for runtime pm. Entry will enter the BACO state (chip off). Exit will exit the BACO state (chip on). Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
31af062a |
|
04-Oct-2019 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: rename amdgpu_device_is_px to amdgpu_device_supports_boco (v2) BACO - Bus Active, Chip Off BOCO - Bus Off, Chip Off To better match what we are checking for and to align with amdgpu_device_supports_baco. BOCO is used on PowerXpress/Hybrid Graphics systems and BACO is used on desktop dGPU boards. v2: fix typo in documentation Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
a69cba42 |
|
28-Oct-2019 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: add a amdgpu_device_supports_baco helper BACO - Bus Active, Chip Off To check if a device supports BACO or not. This will be used in determining when to enable runtime pm. Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
69d5436d |
|
04-Oct-2019 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: add asic callback for BACO support BACO - Bus Active, Chip Off Used to check whether the device supports BACO. This will be used to enable runtime pm on devices which support BACO. Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
88a1c40a |
|
08-Nov-2019 |
Leo Liu <leo.liu@amd.com> |
drm/amdgpu: add JPEG HW IP and SW structures It will be used for JPEG IP 1.0, 2.0, 2.5 and later. Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
5c5b2ba0 |
|
31-Oct-2019 |
Evan Quan <evan.quan@amd.com> |
drm/amdgpu: fix possible pstate switch race condition Added lock protection so that the p-state switch will be guarded to be sequential. Also update the hive pstate only all device from the hive are in the same state. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
f440ff44 |
|
27-Oct-2019 |
Wambui Karuga <wambui.karugax@gmail.com> |
drm/amd: correct "_LENTH" mispelling in constant Correct the "_LENTH" mispelling in the AMDGPU_MAX_TIMEOUT_PARAM_LENGTH constant. Signed-off-by: Wambui Karuga <wambui.karugax@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
7e0ff20c |
|
27-Oct-2019 |
Wambui Karuga <wambui.karugax@gmail.com> |
drm/amd: declare amdgpu_exp_hw_support in amdgpu.h Declare `amdgpu_exp_hw_support` as extern in amdgpu.h to address the following sparse warning: drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c:118:5: warning: symbol 'amdgpu_exp_hw_support' was not declared. Should it be static? Signed-off-by: Wambui Karuga <wambui.karugax@gmail.com> Suggested-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
367039bf |
|
30-Sep-2019 |
Tianci.Yin <tianci.yin@amd.com> |
drm/amdgpu/psp: add psp memory training implementation(v3) add memory training implementation code to save resume time. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Luben Tuikov <luben.tuikov@amd.com> Signed-off-by: Tianci.Yin <tianci.yin@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
efe4f000 |
|
29-Sep-2019 |
Tianci.Yin <tianci.yin@amd.com> |
drm/amdgpu/atomfirmware: add memory training related helper functions(v3) parse firmware to get memory training capability and fb location. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Luben Tuikov <luben.tuikov@amd.com> Signed-off-by: Tianci.Yin <tianci.yin@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
e35e2b11 |
|
29-Sep-2019 |
Tianci.Yin <tianci.yin@amd.com> |
drm/amdgpu: add a generic fb accessing helper function(v3) add a generic helper function for accessing framebuffer via MMIO Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Luben Tuikov <luben.tuikov@amd.com> Signed-off-by: Tianci.Yin <tianci.yin@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
31fa2991 |
|
04-Oct-2019 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: remove in_baco_reset hack It was a vega20 specific hack. Check if we are in reset and what reset method we are using. Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
5f6a556f |
|
10-Oct-2019 |
Xiaojie Yuan <xiaojie.yuan@amd.com> |
drm/amdgpu/discovery: reserve discovery data at the top of VRAM IP Discovery data is TMR fenced by the latest PSP BL, so we need to reserve this region. Tested on navi10/12/14 with VBIOS integrated with latest PSP BL. v2: use DISCOVERY_TMR_SIZE macro as bo size use amdgpu_bo_create_kernel_at() to allocate bo Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
71f98027 |
|
04-Oct-2019 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: move amdgpu_device_get_job_timeout_settings It's only used in amdgpu_device.c and the naming also reflects that. Move it there. Reviewed-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
d65bf1f8 |
|
12-Sep-2019 |
Tao Zhou <tao.zhou1@amd.com> |
drm/amdgpu: replace mmhub_funcs with mmhub.funcs remove mmhub_funcs in adev Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Guchun Chen <guchun.chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
d3a5a121 |
|
12-Sep-2019 |
Tao Zhou <tao.zhou1@amd.com> |
drm/amdgpu: add common mmhub member for adev put mmhub_funcs and ras_if pointer into mmhub struct Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Guchun Chen <guchun.chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
6de088a0 |
|
19-Sep-2019 |
Marek Olšák <marek.olsak@amd.com> |
drm/amdgpu: remove gfx9 NGG Never used. Signed-off-by: Marek Olšák <marek.olsak@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
a35ad98b |
|
11-Sep-2019 |
Shirish S <shirish.s@amd.com> |
drm/amdgpu: remove needless usage of #ifdef define sched_policy in case CONFIG_HSA_AMD is not enabled, with this there is no need to check for CONFIG_HSA_AMD else where in driver code. Suggested-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Shirish S <shirish.s@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
8c9f69bc |
|
09-Sep-2019 |
Shirish S <shirish.s@amd.com> |
drm/amdgpu: fix build error without CONFIG_HSA_AMD If CONFIG_HSA_AMD is not set, build fails: drivers/gpu/drm/amd/amdgpu/amdgpu_device.o: In function `amdgpu_device_ip_early_init': drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1626: undefined reference to `sched_policy' Use CONFIG_HSA_AMD to guard this. Fixes: 1abb680ad371 ("drm/amdgpu: disable gfxoff while use no H/W scheduling policy") Signed-off-by: Shirish S <shirish.s@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
aa978594 |
|
02-Sep-2019 |
Huang Rui <ray.huang@amd.com> |
drm/amdgpu: disable gfxoff while use no H/W scheduling policy While gfxoff is enabled, the mmVM_XXX registers will be 0xfffffff while the GFX is in "off" state. KFD queue creattion doesn't use ring based method, so it will trigger a VM fault. Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
4e66d7d2 |
|
30-Aug-2019 |
Yong Zhao <Yong.Zhao@amd.com> |
drm/amdgpu: Add a kernel parameter for specifying the asic type As more and more new asics start to reuse the old device IDs before launch, there is a need to quickly override the existing asic type corresponding to the reused device ID through a kernel parameter. With this, engineers no longer need to rely on local hack patches, facilitating cooperation across teams. Signed-off-by: Yong Zhao <Yong.Zhao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
f1d59e00 |
|
02-Sep-2019 |
Jack Zhang <Jack.Zhang1@amd.com> |
drm/amd/amdgpu: add sw_fini interface for df_funcs add sw_fini interface of df_funcs. This interface will remove sysfs file of df_cntr_avail function. The old behavior only create sysfs of df_cntr_avail in sw_init, but never remove it for lack of sw_fini interface. With this,driver will report create sysfs fail when it's loaded for the second time. Signed-off-by: Jack Zhang <Jack.Zhang1@amd.com> Reviewed-by: Jonathan Kim <Jonathan.Kim@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
43ce6bab |
|
30-Aug-2019 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: remove amdgpu_cs_try_evict Trying to evict things from the current working set doesn't work that well anymore because of per VM BOs. Rely on reserving VRAM for page tables to avoid contention. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
bebc0762 |
|
23-Aug-2019 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu: switch to new amdgpu_nbio structure no functional change, just switch to new structures Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
e3526257 |
|
27-Aug-2019 |
Monk Liu <Monk.Liu@amd.com> |
drm/amdgpu: introduce vram lost for reset (v2) for SOC15/vega10 the BACO reset & mode1 would introduce vram lost in high end address range, current kmd's vram lost checking cannot catch it since it only check very ahead visible frame buffer v2: cover NV as well Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
244511f3 |
|
15-Aug-2019 |
Christoph Hellwig <hch@lst.de> |
drm/amdgpu: simplify and cleanup setting the dma mask Use dma_set_mask_and_coherent to set both masks in one go, and remove the no longer required fallback, as the kernel now always accepts larger than required DMA masks. Fail the driver probe if we can't set the DMA mask, as that means the system can only support a larger mask. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
3d093da0 |
|
06-Aug-2019 |
Tao Zhou <tao.zhou1@amd.com> |
drm/amdgpu: add amdgpu_mmhub_funcs definition add amdgpu_mmhub_funcs definition and initialize it, prepare for mmhub ras enablement Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
6ca523d7 |
|
09-Aug-2019 |
Tao Zhou <tao.zhou1@amd.com> |
drm/amdgpu: remove RREG64/WREG64 atomic 64 bits REG operations are useless currently Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
045c0216 |
|
22-Jul-2019 |
Tao Zhou <tao.zhou1@amd.com> |
drm/amdgpu: switch to amdgpu_umc structure create new amdgpu_umc structure to for more umc settings in future and switch to the new structure Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Dennis Li <dennis.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
4fa1c6a6 |
|
24-Jul-2019 |
Tao Zhou <tao.zhou1@amd.com> |
drm/amdgpu: add RREG64/WREG64(_PCIE) operations add 64 bits register access functions v2: implement 64 bit functions in low level Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Dennis Li <dennis.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
9e585a52 |
|
23-Jul-2019 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu: add amdgpu_umc_functions structure This is common structure as UMC callback function Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Dennis Li <dennis.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
6501a771 |
|
17-Jul-2019 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu: init RSMU and UMC ip base address for vega20 the driver needs to program RSMU and UMC registers to support vega20 RAS feature Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Dennis Li <dennis.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
a3a09142 |
|
25-Jul-2019 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: put the SMC into the proper state on reset/unload When doing a GPU reset or unloading the driver, we need to put the SMU into the apprpriate state for the re-init after the reset or unload to reliably work. I don't think this is necessary for BACO because the SMU actually controls the BACO state to it needs to be active. For suspend (S3), the asic is put into D3 so the SMU would be powered down so I don't think we need to put the SMU into any special state. Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
0cf3c64f |
|
23-Jul-2019 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: add an asic callback to determine the reset method Sometimes the driver may have to behave differently depending on the method we are using to reset the GPU. Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
64671c0f |
|
09-Jul-2019 |
Jonathan Kim <jonathan.kim@amd.com> |
drm/amdgpu: add perfmon and fica atomics for df adding perfmon and fica atomic operations to adhere to data fabrics finite state machine requirements for indirect register access. Signed-off-by: Jonathan Kim <Jonathan.Kim@amd.com> Reviewed-by: Kent Russell <Kent.Russell@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
989b6a05 |
|
10-Jul-2019 |
James Zhu <James.Zhu@amd.com> |
drm/amdgpu: add vcn nbio doorbell range setting for 2nd vcn instance add vcn nbio doorbell range setting for 2nd vcn instance Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
0fe6a7b4 |
|
10-Sep-2018 |
Le Ma <le.ma@amd.com> |
drm/amdgpu: support hdp flush for more sdma instances The bit RSVD_ENG0 to RSVD_ENG5 in GPU_HDP_FLUSH_REQ/GPU_HDP_FLUSH_DONE can be leveraged for sdma instance 2~7 to poll register/memory. Signed-off-by: Le Ma <le.ma@amd.com> Acked-by: Snow Zhang < Snow.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
113b47e7 |
|
09-Jul-2019 |
Le Ma <le.ma@amd.com> |
drm/amdgpu: increase max number of ip base instances to 8 For Arcturus, the number of IP base instances is 8. Signed-off-by: Le Ma <le.ma@amd.com> Acked-by: Snow Zhang < Snow.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
fa5d2e6f |
|
03-Sep-2018 |
Le Ma <le.ma@amd.com> |
drm/amdgpu: add SDMA 2~7 ip block type Add IP block type. Signed-off-by: Le Ma <le.ma@amd.com> Acked-by: Snow Zhang < Snow.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
1daa2bfa |
|
31-Aug-2018 |
Le Ma <le.ma@amd.com> |
drm/amdgpu: add new member in amdgpu_device for vmhub counts per asic chip It aims to replace AMDGPU_MAX_VMHUBS in for loop to initialize registers. Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
c8ff09bf |
|
24-Dec-2018 |
Xiaojie Yuan <xiaojie.yuan@amd.com> |
drm/amdgpu: increase max instance number for hw ip max instance number is 6 for navi10 and 7 for navi14, and we increase the reg_offset array size to avoid out-of-bound access Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
75ee6487 |
|
21-Jun-2019 |
Felix Kuehling <Felix.Kuehling@amd.com> |
drm/amdkfd: Consistently apply noretry setting Apply the same setting to SH_MEM_CONFIG and VM_CONTEXT1_CNTL. This makes the noretry param no longer KFD-specific. On GFX10 I'm not changing SH_MEM_CONFIG in this commit because GFX10 has different retry behaviour in the SQ and I don't have a way to test it at the moment. Suggested-by: Christian König <Christian.Koenig@amd.com> CC: Philip Yang <Philip.Yang@amd.com> Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by : Shaoyun.liu < Shaoyun.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
bae17d2a |
|
28-May-2019 |
Jack Xiao <Jack.Xiao@amd.com> |
drm/amdgpu: add field indicating if has PCIE atomics support The new field in amdgpu device is used to record whether the system has PCIE atomics support. The field can be exposed to UMD or kfd whether PCIE atomics have supported. Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
fdafb359 |
|
25-Jun-2019 |
Evan Quan <evan.quan@amd.com> |
drm/amdgpu: fix MGPU fan boost enablement for XGMI reset MGPU fan boost feature should not be enabled until all the devices from the same hive are all back from reset. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
f3f48d73 |
|
21-Jun-2019 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: drop unused df init callback It was replaced with the sw_init callback so is no longer needed. Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
a538bbe7 |
|
24-Jan-2019 |
Jack Xiao <Jack.Xiao@amd.com> |
drm/amdgpu/mes: add mes header file and definition Add dummy header file and definitions of mes. Acked-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
38487284 |
|
24-Jan-2019 |
Jack Xiao <Jack.Xiao@amd.com> |
drm/amdgpu/mes: add amdgpu_mes driver parameter amdgpu_mes, which is a driver scope parameter, is used to whether enable mes or not. MES (Micro Engine Scheduler) is the new on chip hw scheduling microcontroller. It can be used to handle queue scheduling and preemption and priorities. Acked-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
a190d1c7 |
|
26-Mar-2019 |
Xiaojie Yuan <xiaojie.yuan@amd.com> |
drm/amdgpu/discovery: add module param for ip discovery enablement to control enablement. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
f39f5bb1 |
|
20-Jun-2019 |
Xiaojie Yuan <xiaojie.yuan@amd.com> |
drm/amdgpu/discovery: add ip discovery initial support The IP discovery table lists is populated by the psp at power on and includes all of the hw details on the board: - List of IPs and MMIO offsets - IP harvest details - IP configuration details v2: prefix struct and function names with 'amdgpu' v3: read table binary from vram using mmMM_INDEX and mmMM_DATA update TABLE_BINARY_MAX_SIZE to 64kb (1 TMR) add 'instance_number' field per ip info consider endianness and replace uint8/16/32_t with u8/16/32 initialize register base addresses initialize adev->gfx.config and adev->gfx.cu_info to replace gpu info fw get major and minor version using a single api don't expose internal data structures in amdgpu_discovery.h v4: RCC_CONFIG_MEMSIZE is in MB units hold mmio_idx_lock while reading ip discovery binary v5: pick out discovery.h as a cross-OS header do structure pointer cast directly consider endianness while using the member of structure convert base addresses to dword at boot up, PSP BL copies ip discovery binary from VBIOS(SPIROM) image to the top of the frame buffer (just below the reserved regions for PSP & SMU). ip discovery data table includes the collection of each ip's identification number, base addresses, version number, and harvest setting placeholder. gc data table includes gfx info structure. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
6698a3d0 |
|
20-Jun-2019 |
Jack Xiao <Jack.Xiao@amd.com> |
drm/amdgpu: add mcbp unit test in debugfs (v3) The MCBP unit test is used to test the functionality of MCBP. It emualtes to send preemption request and resubmit the unfinished jobs. v2: squash in fixes (Alex) v3: squash in memory leak fix (Jack) Acked-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
b239c017 |
|
10-Jan-2019 |
Jack Xiao <Jack.Xiao@amd.com> |
drm/amdgpu: add mcbp driver parameter Add mcbp driver parameter, so that mcbp feature can be enabled/disabled by driver parameter. Acked-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
51bcce46 |
|
31-Jul-2018 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu: add module parameter for async_gfx_ring enablement 0 means disable async_gfx_ring and is the default setting 1 means enable async_gfx_ring Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Jack Xiao <jack.xiao@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Acked-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
53b2fe41 |
|
11-Mar-2019 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu: enable gfx eop interrupt per gfx pipe Navi10 has 2 gfx pipe and need to enable gfx eop interrupt per pipe, instead of enable eop int for all gfx pipes at one time. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
b45ddfe8 |
|
16-Oct-2018 |
Leo Liu <leo.liu@amd.com> |
drm/amdgpu: add nbio callbacks for vcn doorbell support For Navi10 VCN2.0, the engine supports Doorbell Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
e4cf4bf5 |
|
19-Jun-2019 |
Jonathan Kim <jonathan.kim@amd.com> |
drm/amdgpu: update df_v3_6 for xgmi perfmons (v2) add pmu attribute groups and structures for perf events. add sysfs to track available df perfmon counters fix overflow handling in perfmon counter reads. v2: squash in fix (Alex) Signed-off-by: Jonathan Kim <Jonathan.Kim@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
ad4de27f |
|
06-Jun-2019 |
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> |
drm/amdgpu: Add module parameter for specifying default ABM level [Why] It's non trivial to configure or specify an ABM reduction level for userspace outside of X. There is also no method to specify the default ABM value at boot time. A parameter should be added to configure this. [How] Expose a module parameter that can specify the default ABM level to use for eDP connectors on DC enabled hardware that loads the DMCU firmware. The default is still disabled (0), but levels can range from 1-4. Levels control how much the backlight can be reduced, with being the least amount of reduction and four being the most reduction. Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by: David Francis <david.francis@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
b4559a16 |
|
04-Jun-2019 |
Tom St Denis <tom.stdenis@amd.com> |
drm/amd/amdgpu: remove vram_page_split kernel option (v3) This option is no longer needed. The default code paths are now the only option. v2: Add HPAGE support and a default for non contiguous maps v3: Misread 512 pages as MiB ... Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
f867723b |
|
09-Jun-2019 |
Sam Ravnborg <sam@ravnborg.org> |
drm/amd: drop use of drmP.h in amdgpu.h Delete the unused drmP.h from amdgpu.h. Fix fallout in various files. Signed-off-by: Sam Ravnborg <sam@ravnborg.org> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Cc: "Christian König" <christian.koenig@amd.com> Cc: "David (ChunMing) Zhou" <David1.Zhou@amd.com> Cc: David Airlie <airlied@linux.ie> Cc: Daniel Vetter <daniel@ffwll.ch> Link: https://patchwork.freedesktop.org/patch/msgid/20190609220757.10862-5-sam@ravnborg.org
|
#
beff74bc |
|
28-May-2019 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: fix a race in GPU reset with IB test (v2) Split late_init into two functions, one (do_late_init) which just does the hw init, and late_init which calls do_late_init and schedules the IB test work. Call do_late_init in the GPU reset code to run the init code, but not schedule the IB test code. The IB test code is called directly in the gpu reset code so no need to run the IB tests in a separate work thread. If we do, we end up racing. v2: Rework late_init. Pull out the mgpu fan boost and xgmi pstate code into late_init so they get called in all cases. rename the late_init worker thread to delayed work since it's just the IB tests now which can happen later. Schedule the work at init and resume time. It's not needed at reset time because the IB tests are called directly. Reviewed-by: Christian König <christian.koenig@amd.com> Cc: Xinhui Pan <xinhui.pan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
fb2dbfd2 |
|
15-May-2019 |
Kent Russell <kent.russell@amd.com> |
drm/amdgpu: Add Unique Identifier sysfs file unique_id v2 Add a file that provides a Unique ID for the GPU. This will persist across machines and is guaranteed to be unique. This is only available for GFX9 and newer, so older ASICs will not have this file in the sysfs pool v2: Store it in adev for ASICs that don't have a hwmgr Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Kent Russell <kent.russell@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
992af942 |
|
02-May-2019 |
Jonathan Kim <jonathan.kim@amd.com> |
drm/amdgpu: add df perfmon regs and funcs for xgmi v6: Squash in warning fix (Colin Ian King) v5: Fix warnings (Alex) v4: fixed mixed delaration and code warnings and minor errors v3: exposing df funcs in amdgpu_df_funcs in amdgpu.h v2: moving permonctl/perfmonctr from default to offset - adding df perfmonctl and perfmonctr registers for df counters - adding df funcs to set perfmonctl and get perfmonctr for df and xgmi counters - exposing df funcs in amdgpu_df_funcs Signed-off-by: Jonathan Kim <jonathan.kim@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
dcea6e65 |
|
30-Apr-2019 |
Kent Russell <kent.russell@amd.com> |
drm/amdgpu: Add PCIe replay count sysfs file Add a sysfs file for reporting the number of PCIe replays (NAKs). This returns the sum of NAKs received and NAKs generated Signed-off-by: Kent Russell <kent.russell@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
912dfc84 |
|
29-Apr-2019 |
Evan Quan <evan.quan@amd.com> |
drm/amdgpu: enable separate timeout setting for every ring type V4 Every ring type can have its own timeout setting. - V2: update lockup_timeout parameter format and cosmetic fixes - V3: invalidate 0 and negative values - V4: update lockup_timeout parameter format Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
88807dc8 |
|
04-Apr-2019 |
Oak Zeng <Oak.Zeng@amd.com> |
drm/amdgpu: Remap hdp coherency registers Remap HDP_MEM_COHERENCY_FLUSH_CNTL and HDP_REG_COHERENCY_FLUSH_CNTL to an empty page in mmio space. We will later map this page to process space so application can flush hdp. This can't be done properly at those registers' original location because it will expose more than desired registers to process space. v2: Use explicit register hole location v3: Moved remapped hdp registers into adev struct v4: Use more generic name for remapped page Expose register offset in kfd_ioctl.h v5: Move hdp register remap function to nbio ip function v6: Fixed operator precedence issue and other bugs Signed-off-by: Oak Zeng <Oak.Zeng@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
2624dd15 |
|
01-Apr-2019 |
Chunming Zhou <david1.zhou@amd.com> |
drm/amdgpu: add timeline support in amdgpu CS v3 syncobj wait/signal operation is appending in command submission. v2: separate to two kinds in/out_deps functions v3: fix checking for timeline syncobj Signed-off-by: Chunming Zhou <david1.zhou@amd.com> Cc: Tobias Hector <Tobias.Hector@amd.com> Cc: Jason Ekstrand <jason@jlekstrand.net> Cc: Dave Airlie <airlied@redhat.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
d2574c33 |
|
29-Mar-2019 |
Mario Kleiner <mario.kleiner.de@gmail.com> |
drm/amd/display: In VRR mode, do DRM core vblank handling at end of vblank. (v2) In VRR mode, proper vblank/pageflip timestamps can only be computed after the display scanout position has left front-porch. Therefore delay calls to drm_crtc_handle_vblank(), and thereby calls to drm_update_vblank_count() and pageflip event delivery, to after the end of front-porch when in VRR mode. We add a new vupdate irq, which triggers at the end of the vupdate interval, ie. at the end of vblank, and calls the core vblank handler function. The new irq handler is not executed in standard non-VRR mode, so vblank handling for fixed refresh rate mode is identical to the past implementation. v2: Implement feedback by Nicholas and Paul Menzel. Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
86f7bae5 |
|
19-Mar-2019 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: revert "XGMI pstate switch initial support" This reverts commit 9b638f9751308ae3ae8f28e0c6e9decffd97f5f9. Adding this to the mapping is complete nonsense and the whole implementation looks racy. This patch wasn't thoughtfully reviewed and should be reverted for now. Signed-off-by: Christian König <christian.koenig@amd.com> Acked-by: Liu, Shaoyun <Shaoyun.Liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
1218252f |
|
25-Oct-2018 |
xinhui pan <xinhui.pan@amd.com> |
drm/amdgpu: add module parameters for ras Allow RAS feature enable/disable via boot parameter. Signed-off-by: xinhui pan <xinhui.pan@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
0c5ccf14 |
|
06-Mar-2019 |
Evan Quan <evan.quan@amd.com> |
drm/amd/powerplay: apply Vega20 BACO workaround Applied vdci flush workaround for Vega20 BACO. Signed-off-by: Evan Quan <evan.quan@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
9b638f97 |
|
21-Feb-2019 |
shaoyunl <shaoyun.liu@amd.com> |
drm/amdgpu: XGMI pstate switch initial support Driver vote low to high pstate switch whenever there is an outstanding XGMI mapping request. Driver vote high to low pstate when all the outstanding XGMI mapping is terminated. Signed-off-by: shaoyunl <shaoyun.liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
3b94fb10 |
|
30-Jan-2019 |
Likun Gao <Likun.Gao@amd.com> |
drm/amd/powerplay: add limit of pp_feature for smu (v3) Move pp_feature from the struct of amd_powerplay to amdgpu_device. Add pp_feature limit for overdrive interface. v2: put pp_feature into struct amdgpu_pm. v3: merge feature_mask with pp_feature. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Suggested-by: Alex Deucher <alexander.deucher@amd.com> Suggested-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
137d63ab |
|
28-Nov-2018 |
Huang Rui <ray.huang@amd.com> |
drm/amd/powerplay: add new smu ip block This patch add amdgpu_smu ip block skeleton as placeholder. We plan use new smu ip block from Vega20. Signed-off-by: Huang Rui <ray.huang@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
021830d2 |
|
29-Jan-2019 |
Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> |
drm/amdgpu: Check if fd really is an amdgpu fd. Otherwise we interpret the file private data as drm & amdgpu data while it might not be, possibly allowing one to get memory corruption. Signed-off-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
8987e2e2 |
|
17-Dec-2018 |
Oak Zeng <Oak.Zeng@amd.com> |
drm/amdgpu: Fix sdma doorbell range setting Different ASIC has different SDMA queue number so different SDMA doorbell range. Introduce an extra parameter to sdma_doorbell_range function and set sdma doorbell range correctly. Signed-off-by: Oak Zeng <Oak.Zeng@amd.com> Reviewed-by: Philip Yang <Philip.Yang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
44401889 |
|
31-Oct-2018 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: add need_reset_on_init asic callback (v2) Used to determine if we need to reset the asic on init due to the driver having been previously loaded or not shutdown cleanly. E.g., kexec or VM passthrough. v2: rebase Reviewed-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
b45e18ac |
|
03-Jan-2019 |
Kent Russell <kent.russell@amd.com> |
drm/amdgpu: Add sysfs file for PCIe usage v5 Add a sysfs file that reports the number of bytes transmitted and received in the last second. This can be used to approximate the PCIe bandwidth usage over the last second. v2: Clarify use of mps as estimation of bandwidth v3: Don't make the file on APUs v4: Early exit for APUs in the read function, change output to display "packets-received packets-sent mps" v5: fix missing header for si (Alex) Signed-off-by: Kent Russell <kent.russell@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
08d1bdd4 |
|
24-Oct-2018 |
Rex Zhu <Rex.Zhu@amd.com> |
drm/amdgpu: Limit vm max ctx number to 4096 driver need to reserve resource for each ctx for some hw features. so add this limitation. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
611736d8 |
|
19-Nov-2018 |
Felix Kuehling <Felix.Kuehling@amd.com> |
drm/amdgpu: Add KFD VRAM limit checking We don't want KFD processes evicting each other over VRAM usage. Therefore prevent overcommitting VRAM among KFD applications with a per-GPU limit. Also leave enough room for page tables on top of the application memory usage. Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Eric Huang <JinHuiEric.Huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
4944af67 |
|
02-Dec-2018 |
wentalou <wentalou@amd.com> |
drm/amdgpu: enlarge maximum waiting time of KIQ KIQ in VF’s init delayed by another VF’s reset, which would cause late_init failed occasionally. MAX_KIQ_REG_TRY enlarged from 20 to 80 would fix this issue. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Wentao Lou <Wentao.Lou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
d4535e2c |
|
29-Nov-2018 |
Andrey Grodzovsky <andrey.grodzovsky@amd.com> |
drm/amdgpu: Implement concurrent asic reset for XGMI. Use per hive wq to concurrently send reset commands to all nodes in the hive. v2: Switch to system_highpri_wq after dropping dedicated queue. Fix non XGMI code path KASAN error. Stop the hive reset for each node loop if there is a reset failure on any of the nodes. Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
26bc5340 |
|
22-Nov-2018 |
Andrey Grodzovsky <andrey.grodzovsky@amd.com> |
drm/amdgpu: Refactor GPU reset for XGMI hive case For XGMI hive case do reset in steps where each step iterates over all devs in hive. This especially important for asic reset since all PSP FW in hive must come up within a limited time (around 1 sec) to properply negotiate the link. Do this by refactoring amdgpu_device_gpu_recover and amdgpu_device_reset into pre_asic_reset, asic_reset and post_asic_reset functions where is part is exectued for all the GPUs in the hive before going to the next step. v2: Update names for amdgpu_device_lock/unlock functions. v3: Introduce per hive locking to avoid multiple resets for GPUs in same hive. v4: Remove delayed_workqueue()/ttm_bo_unlock_delayed_workqueue() - they are copy & pasted over from radeon and on amdgpu there isn't any reason for that any more. Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
5183411b |
|
12-Nov-2018 |
Andrey Grodzovsky <andrey.grodzovsky@amd.com> |
drm/amdgpu: Refactor amdgpu_xgmi_add_device This is prep work for updating each PSP FW in hive after GPU reset. Split into build topology SW state and update each PSP FW in the hive. Save topology and count of XGMI devices for reuse. v2: Create seperate header for XGMI. Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
cde577bd |
|
23-Nov-2018 |
Oak Zeng <ozeng@amd.com> |
drm/amdgpu: Move doorbell structures to seperate file Move doorbell structures, enum definitions and helper functions from amdgpu.h to amdgpu_doorbell.h. No functional change Signed-off-by: Oak Zeng <ozeng@amd.com> Proposed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
c93aa775 |
|
19-Nov-2018 |
Oak Zeng <ozeng@amd.com> |
drm/amdgpu: Doorbell layout for vega20 and future asic This introduces new doorbell layout for vega20 and future asics v2: Use enum definition instead of hardcoded value Signed-off-by: Oak Zeng <ozeng@amd.com> Suggested-by: Felix Kuehling <Felix.Kuehling@amd.com> Suggested-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
062f3807 |
|
19-Nov-2018 |
Oak Zeng <ozeng@amd.com> |
drm/amdgpu: Vega10 doorbell index initialization v2: Use enum definition instead of hardcoded value v3: Remove unused enum definition Signed-off-by: Oak Zeng <ozeng@amd.com> Suggested-by: Felix Kuehling <Felix.Kuehling@amd.com> Suggested-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
5253163a |
|
26-Nov-2018 |
Oak Zeng <ozeng@amd.com> |
drm/amdgpu: Add asic func interface to init doorbell index This is preparation to move doorbell index initialization to amdgpu_asic_funcs Signed-off-by: Oak Zeng <ozeng@amd.com> Proposed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
409c5191 |
|
16-Nov-2018 |
Oak Zeng <ozeng@amd.com> |
drm/amdgpu: Add field in amdgpu_dev to hold reserved doorbell index This is a preparation work to make reserved doorbell index per device, instead of using a global macro definition. By doing this, we can easily change doorbell layout for future ASICs while not affecting ASICs in production. Signed-off-by: Oak Zeng <ozeng@amd.com> Suggested-by: Felix Kuehling <Felix.Kuehling@amd.com> Suggested-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
206bbafe |
|
26-Nov-2018 |
David Francis <David.Francis@amd.com> |
drm/amd: Query and use ACPI backlight caps ACPI ATIF has a function called query backlight transfer characteristics. Among the information returned by this function is the minimum and maximum input signals for the backlight Call that function on ACPI init. When DM backlight device is updated, copy over the backlight caps into DM, but only once. Use the backlight caps in the backlight-to-dc calculation Signed-off-by: David Francis <David.Francis@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
79d197f3 |
|
06-Nov-2018 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: add DC feature mask module parameter Similar to ppfeaturemask. Allows you to selectively enable/disable DC features. Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
7875a226 |
|
06-Nov-2018 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: add DC feature mask module parameter Similar to ppfeaturemask. Allows you to selectively enable/disable DC features. Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
7946340f |
|
18-Oct-2018 |
Rex Zhu <Rex.Zhu@amd.com> |
drm/amdgpu: Move csa related code to separate file In baremetal, also need to reserve csa for preemption. so move the csa related code out of sriov. Reviewed-by: Monk Liu <Monk.Liu@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
898c2cb5 |
|
16-Oct-2018 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: use scheduler fault instead of reset work Signal a fault to the scheduler on an illegal instruction or register access violation instead of kicking of the reset handler directly. Signed-off-by: Christian König <christian.koenig@amd.com> Acked-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
c3bce35c |
|
02-Oct-2018 |
Frank.Min <Frank.Min@amd.com> |
drm/amdgpu: fix sdma doorbell comments typo Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Frank.Min <Frank.Min@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
44779b43 |
|
29-Sep-2018 |
Rex Zhu <Rex.Zhu@amd.com> |
drm/amdgpu: Move gfx flag in_suspend to adev Move in_suspend flag to adev from gfx, so can be used in other ip blocks, also keep consistent with gpu_in_reset flag. Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
e5081e30 |
|
29-Sep-2018 |
Rex Zhu <Rex.Zhu@amd.com> |
drm/amdgpu: Drop dead define in amdgpu.h the struct was not in use any more. Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
62d73fbc |
|
26-Sep-2018 |
Evan Quan <evan.quan@amd.com> |
drm/amdgpu: added AMD GPU instance counting V2 Count all GPU instances from AMD(including iGPUs and dGPUs) in the system. V2: drop unnecessary initialization for other gpu_info members except mutex Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
a2a8fb51 |
|
09-Aug-2018 |
Emily Deng <Emily.Deng@amd.com> |
drm/amdgpu/sriov: Correct the setting about sdma doorbell offset of Vega10 Correct the format For vega10 sriov, the sdma doorbell must be fixed as follow to keep the same setting with host driver, or it will happen conflicts. Signed-off-by: Emily Deng <Emily.Deng@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
c5892230 |
|
23-Mar-2018 |
Shaoyun Liu <Shaoyun.Liu@amd.com> |
drm/amdgpu: Doorbell assignment for 8 sdma user queue per engine Change doorbell assignments to allow routing doorbells for 8 user mode SDMA queues per engine. Signed-off-by: Shaoyun Liu <Shaoyun.Liu@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com>
|
#
8c5e13ec |
|
21-Sep-2018 |
Andrey Grodzovsky <andrey.grodzovsky@amd.com> |
Revert "drm/amdgpu: remove fence fallback" This reverts commit 9b0df0937a852d299fbe42a5939c9a8a4cc83c55. This commit breaks KCQ IB test and S3 on Polaris 11. Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
3e14bedc |
|
18-Sep-2018 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: remove fence fallback DC doesn't seem to have a fallback path either. So when interrupts doesn't work any more we are pretty much busted no matter what. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
fb30fc59 |
|
27-Jun-2018 |
Shaoyun Liu <Shaoyun.Liu@amd.com> |
drm/amdgpu : Generate XGMI topology info from driver level Driver will save an array of XGMI hive info, each hive will have a list of devices that have the same hive ID. Signed-off-by: Shaoyun Liu <Shaoyun.Liu@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
961c75cf |
|
23-Aug-2018 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: move amdgpu_device_(vram|gtt)_location Move that into amdgpu_gmc.c since we are really deadling with GMC address space here. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
12938fad |
|
21-Aug-2018 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: cleanup GPU recovery check a bit (v2) Check if we should call the function instead of providing the forced flag. v2: rebase on KFD changes (Alex) Signed-off-by: Christian König <christian.koenig@amd.com> Acked-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
3890d111 |
|
17-Aug-2018 |
Emily Deng <Emily.Deng@amd.com> |
drm/amdgpu: use kiq to do invalidate tlb To avoid the tlb flush not interrupted by world switch, use kiq and one command to do tlb invalidate. v2: Refine the invalidate lock position. Signed-off-by: Emily Deng <Emily.Deng@amd.com> Reviewed-and-Tested-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
0d346a14 |
|
19-Jul-2018 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: use entity instead of ring for CS Further demangle ring from entity handling. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
8290268f |
|
18-Jul-2018 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: move context related stuff to amdgpu_ctx.h Further unmangle amdgpu.h. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
869a53d4 |
|
16-Jul-2018 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: remove the queue manager Not needed any more since that is now done by the scheduler. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
c2d358d7 |
|
06-Aug-2018 |
Huang Rui <ray.huang@amd.com> |
drm/amdgpu: move missed gfxoff entry into amdgpu_gfx header Move missed gfxoff entry to amdgpu_gfx.h. Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
4473e1db |
|
03-Aug-2018 |
Huang Rui <ray.huang@amd.com> |
drm/amdgpu: move vm definitions into amdgpu_vm header Demangle amdgpu.h. Signed-off-by: Huang Rui <ray.huang@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
c082b998 |
|
03-Aug-2018 |
Huang Rui <ray.huang@amd.com> |
drm/amdgpu: move gmc macros into amdgpu_gmc header Demangle amdgpu.h. Signed-off-by: Huang Rui <ray.huang@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
5df58525 |
|
09-Aug-2018 |
Huang Rui <ray.huang@amd.com> |
drm/amdgpu: move display definitions into amdgpu_display header Demangle amdgpu.h. Signed-off-by: Huang Rui <ray.huang@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
9e21fc56 |
|
03-Aug-2018 |
Huang Rui <ray.huang@amd.com> |
drm/amdgpu: remove useless gds switch macro Demangle amdgpu.h. Signed-off-by: Huang Rui <ray.huang@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
0a7845db |
|
03-Aug-2018 |
Huang Rui <ray.huang@amd.com> |
drm/amdgpu: move ring macros into amdgpu_ring header Demangle amdgpu.h. Signed-off-by: Huang Rui <ray.huang@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
2cddc50e |
|
13-Aug-2018 |
Huang Rui <ray.huang@amd.com> |
drm/amdgpu: move gem definitions into amdgpu_gem header Demangle amdgpu.h. Signed-off-by: Huang Rui <ray.huang@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
6462c007 |
|
02-Aug-2018 |
Huang Rui <ray.huang@amd.com> |
drm/amdgpu: move psp macro into amdgpu_psp header Demangle amdgpu.h. Signed-off-by: Huang Rui <ray.huang@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
55560046 |
|
02-Aug-2018 |
Huang Rui <ray.huang@amd.com> |
drm/amdgpu: move firmware definitions into amdgpu_ucode header Demangle amdgpu.h. Signed-off-by: Huang Rui <ray.huang@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
bb7743bc |
|
02-Aug-2018 |
Huang Rui <ray.huang@amd.com> |
drm/amdgpu: move sdma definitions into amdgpu_sdma header Demangle amdgpu.h. Furthermore, SDMA is used for moving and clearing the data buffer, so the header also need be included in ttm. Signed-off-by: Huang Rui <ray.huang@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
aa47d117 |
|
02-Aug-2018 |
Huang Rui <ray.huang@amd.com> |
drm/amdgpu: move ih definitions into amdgpu_ih header Demangle amdgpu.h Signed-off-by: Huang Rui <ray.huang@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
448fe192 |
|
02-Aug-2018 |
Huang Rui <ray.huang@amd.com> |
drm/amdgpu: move gfx definitions into amdgpu_gfx header Demangle amdgpu.h Signed-off-by: Huang Rui <ray.huang@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
1e317b99 |
|
27-Jul-2018 |
Rex Zhu <Rex.Zhu@amd.com> |
drm/amdgpu: Put enable gfx off feature to a delay thread delay to enable gfx off feature to avoid gfx on/off frequently suggested by Alex and Evan. Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
d23ee13f |
|
30-Jul-2018 |
Rex Zhu <Rex.Zhu@amd.com> |
drm/amdgpu: Add amdgpu_gfx_off_ctrl function v2: 1. drop the special handling for the hw IP suggested by hawking and Christian. 2. refine the variable name suggested by Flora. This funciton as the entry of gfx off feature. we arbitrat gfx off feature enable/disable in this function. Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
4a8c21a1 |
|
30-Jul-2018 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: move bo_list defines to amdgpu_bo_list.h Further demangle amdgpu.h Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Acked-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
52c054ca |
|
27-Jul-2018 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: add proper error handling to amdgpu_bo_list_get Otherwise we silently don't use a BO list when the handle is invalid. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
9d248517 |
|
23-Jul-2018 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: add support for inplace IB patching for MM engines v2 We are going to need that for the second UVD instance on Vega20. v2: rename to patch_cs_in_place Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-and-tested-by: James Zhu <James.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
c704ab18 |
|
16-Jul-2018 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: consistenly name amdgpu_bo_ functions Just rename functions, no functional change. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
f3cdadb6 |
|
17-Jul-2018 |
Sonny Jiang <sonny.jiang@amd.com> |
drm/amdgpu: remove internal/unused kernel module parameters Remove internal/unused kernel module parameters Signed-off-by: Sonny Jiang <sonny.jiang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
3320b8d2 |
|
13-Jul-2018 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: remove job->ring We can easily get that from the scheduler. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com> Acked-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
050d9d43 |
|
13-Jul-2018 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: cleanup job header Move job related defines, structure and function declarations to amdgpu_job.h Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com> Acked-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
964d0fbf |
|
06-Jul-2018 |
Andrey Grodzovsky <andrey.grodzovsky@amd.com> |
drm/amdgpu: Allow to create BO lists in CS ioctl v3 This change is to support MESA performace optimization. Modify CS IOCTL to allow its input as command buffer and an array of buffer handles to create a temporay bo list and then destroy it when IOCTL completes. This saves on calling for BO_LIST create and destry IOCTLs in MESA and by this improves performance. v2: Avoid inserting the temp list into idr struct. v3: Remove idr alloation from amdgpu_bo_list_create. Remove useless argument from amdgpu_cs_parser_fini Minor cosmetic stuff. v4: Revert amdgpu_bo_list_destroy back to static Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
a5ccfe5c2 |
|
10-Jul-2018 |
Michel Dänzer <michel.daenzer@amd.com> |
drm/amdgpu: Make pin_size values atomic Concurrent execution of the non-atomic arithmetic could result in completely bogus values. v2: * Rebased on v2 of the previous patch Cc: stable@vger.kernel.org Bugzilla: https://bugs.freedesktop.org/106872 Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
ddc21af4 |
|
10-Jul-2018 |
Michel Dänzer <michel.daenzer@amd.com> |
drm/amdgpu: Keep track of amount of pinned CPU visible VRAM Instead of CPU invisible VRAM. Preparation for the following, no functional change intended. v2: * Also change amdgpu_vram_mgr_bo_invisible_size to amdgpu_vram_mgr_bo_visible_size, allowing further simplification (Christian König) Cc: stable@vger.kernel.org Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
73b19174 |
|
05-Jul-2018 |
Rex Zhu <rex.zhu@amd.com> |
drm/amdgpu: Add CLK IP base offset so we can read/write the registers in CLK domain through RREG32/WREG32_SOC15 Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
24aeefcd |
|
25-Jun-2018 |
Lyude Paul <lyude@redhat.com> |
drm/amdgpu: Add amdgpu_atpx_get_dhandle() Since it seems that some vendors are storing the ATIF ACPI methods under the same handle that ATPX lives under instead of the device's own handle, we're going to need to be able to retrieve this handle later so we can probe for ATIF there. Signed-off-by: Lyude Paul <lyude@redhat.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
102c16a0 |
|
25-Jun-2018 |
Lyude Paul <lyude@redhat.com> |
drm/amdgpu: Make struct amdgpu_atif private to amdgpu_acpi.c Currently, there is nothing in amdgpu that actually uses these structs other than amdgpu_acpi.c. Additionally, since we're about to start saving the correct ACPI handle to use for calling ATIF in this struct this saves us from having to handle making sure that the acpi_handle (and by proxy, the type definition for acpi_handle and all of the other acpi headers) doesn't need to be included within the amdgpu_drv struct itself. This follows the example set by amdgpu_atpx_handler.c. Signed-off-by: Lyude Paul <lyude@redhat.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
c49d8280 |
|
04-Jun-2018 |
Andrey Grodzovsky <andrey.grodzovsky@amd.com> |
drm/amdgpu: Rename entity cleanup finctions. Everything in the flush code path (i.e. waiting for SW queue to become empty) names with *_flush() and everything in the release code path names *_fini() Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Suggested-by: Christian König <christian.koenig@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
9bdc2092 |
|
19-Jun-2018 |
Andrey Grodzovsky <andrey.grodzovsky@amd.com> |
drm/amdgpu: Add parsing SQ_EDC_INFO to SQ IH v3. Access to SQ_EDC_INFO requires selecting register instance and hence mutex lock when accessing GRBM_GFX_INDEX for which a work is schedueled from IH. But SQ interrupt can be raised on many instances at once which means queuing work will usually succeed for the first one but fail for the rest since the work takes time to process. To avoid losing info about other interrupt instances call the parsing function directly from high IRQ when current work hasn't finished and avoid accessing SQ_EDC_INFO in that case. v2: Simplify high IRQ and BH handlers synchronization using work_pending. Remove {READ,WRITE}_ONCE notations since smp_{r,w}mb are implicit compiler barriers. v3: Remove exlicit memory barriers as scedule_work has r/w barriers. Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
4aa5d5eb |
|
25-Jun-2018 |
Lyude Paul <lyude@redhat.com> |
drm/amdgpu: Add amdgpu_atpx_get_dhandle() Since it seems that some vendors are storing the ATIF ACPI methods under the same handle that ATPX lives under instead of the device's own handle, we're going to need to be able to retrieve this handle later so we can probe for ATIF there. Signed-off-by: Lyude Paul <lyude@redhat.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
|
#
2cd5fe22 |
|
25-Jun-2018 |
Lyude Paul <lyude@redhat.com> |
drm/amdgpu: Make struct amdgpu_atif private to amdgpu_acpi.c Currently, there is nothing in amdgpu that actually uses these structs other than amdgpu_acpi.c. Additionally, since we're about to start saving the correct ACPI handle to use for calling ATIF in this struct this saves us from having to handle making sure that the acpi_handle (and by proxy, the type definition for acpi_handle and all of the other acpi headers) doesn't need to be included within the amdgpu_drv struct itself. This follows the example set by amdgpu_atpx_handler.c. Signed-off-by: Lyude Paul <lyude@redhat.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
|
#
981658c6 |
|
22-May-2018 |
David Panariti <David.Panariti@amd.com> |
drm/amdgpu: Add interrupt SQ source struct to amdgpu_gfx struct v2. SQ can generate interrupts on EDC/ECC errors and this struct controls how the interrupt is handled. The guts are filled in in the gf_v<major>_<minor>.c files. v2: Rebase. Signed-off-by: David Panariti <David.Panariti@amd.com> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
5a2f2913 |
|
15-May-2018 |
David Panariti <David.Panariti@amd.com> |
drm/amdgpu: Added ISR for CP ECC/EDC interrupt v2. ISR will DRM_ERROR ECC error message. v2: Remove CZ only limitation. Rebase. Signed-off-by: David Panariti <David.Panariti@amd.com> Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
8f9b2e50 |
|
10-May-2018 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: add new DF callback for ECC setup The ForceParWrRMW setting needs to be enabled for ECC, but disabled when ECC is not enabled. Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
6c8d74ca |
|
18-Apr-2018 |
Samuel Li <Samuel.Li@amd.com> |
drm/amdgpu: Enable scatter gather display support Enables sg display if vram size <= THRESHOLD(256M); otherwise still use vram as display buffer. This patch fixed some potention issues introduced by change "allow framebuffer in GART memory as well" due to CZ/ST hardware limitation. v2: Change default setting to auto. v3: Move some logic from amdgpu_display_framebuffer_domains() to pin function, suggested by Christian. v4: Split into several patches. v5: Drop module parameter for now. Signed-off-by: Samuel Li <Samuel.Li@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
00f54b97 |
|
27-Feb-2018 |
Huang Rui <ray.huang@amd.com> |
drm/amdgpu: use pp_feature member to store the mask Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
621a6318 |
|
22-Jan-2018 |
Huang Rui <ray.huang@amd.com> |
drm/amdgpu: add save restore list cntl gpm and srm firmware support RLC save/restore list cntl/gpm_mem/srm_mem ucodes are used for CGPG and gfxoff function. Signed-off-by: Huang Rui <ray.huang@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
7951e376 |
|
13-Apr-2018 |
Rex Zhu <Rex.Zhu@amd.com> |
drm/amdgpu: Reserved vram for smu to save debug info. v2: check reserved vram size before allocate. Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
8ee3a52e |
|
15-Apr-2018 |
Emily Deng <Emily.Deng@amd.com> |
drm/gpu-sched: fix force APP kill hang(v4) issue: there are VMC page fault occurred if force APP kill during 3dmark test, the cause is in entity_fini we manually signal all those jobs in entity's queue which confuse the sync/dep mechanism: 1)page fault occurred in sdma's clear job which operate on shadow buffer, and shadow buffer's Gart table is cleaned by ttm_bo_release since the fence in its reservation was fake signaled by entity_fini() under the case of SIGKILL received. 2)page fault occurred in gfx' job because during the lifetime of gfx job we manually fake signal all jobs from its entity in entity_fini(), thus the unmapping/clear PTE job depend on those result fence is satisfied and sdma start clearing the PTE and lead to GFX page fault. fix: 1)should at least wait all jobs already scheduled complete in entity_fini() if SIGKILL is the case. 2)if a fence signaled and try to clear some entity's dependency, should set this entity guilty to prevent its job really run since the dependency is fake signaled. v2: splitting drm_sched_entity_fini() into two functions: 1)The first one is does the waiting, removes the entity from the runqueue and returns an error when the process was killed. 2)The second one then goes over the entity, install it as completion signal for the remaining jobs and signals all jobs with an error code. v3: 1)Replace the fini1 and fini2 with better name 2)Call the first part before the VM teardown in amdgpu_driver_postclose_kms() and the second part after the VM teardown 3)Keep the original function drm_sched_entity_fini to refine the code. v4: 1)Rename entity->finished to entity->last_scheduled; 2)Rename drm_sched_entity_fini_job_cb() to drm_sched_entity_kill_jobs_cb(); 3)Pass NULL to drm_sched_entity_fini_job_cb() if -ENOENT; 4)Replace the type of entity->fini_status with "int"; 5)Remove the check about entity->finished. Signed-off-by: Monk Liu <Monk.Liu@amd.com> Signed-off-by: Emily Deng <Emily.Deng@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
82853638 |
|
27-Mar-2018 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: add emit_reg_write_reg_wait ring callback This callback writes a value to a register and then reads back another register and waits for a value in a single operation. Provide a helper function using two operations for engines that don't support this opertion. Reviewed-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
5eeae247 |
|
10-Apr-2018 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu/gfx9: cache DB_DEBUG2 and make it available to userspace Userspace needs to query this value to work around a hw bug in certain cases. Acked-by: Nicolai Hähnle <nicolai.haehnle@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
e6636ae1 |
|
09-Apr-2018 |
Evan Quan <evan.quan@amd.com> |
drm/amdgpu: add MP1 and THM hw ip base reg offset Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
1b59fb03 |
|
09-Apr-2018 |
Evan Quan <evan.quan@amd.com> |
drm/amdgpu: add MP1 and THM hw ip base reg offset Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
69070690 |
|
29-Mar-2018 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: add asic need_full_reset callback Allow us to determine at the soc level whether the asic requires full reset or if soft reset will work. Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
634c96e3 |
|
22-Mar-2018 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu: add df callback functions structure Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
43fa561f |
|
28-Mar-2018 |
Rex Zhu <Rex.Zhu@amd.com> |
drm/amdgpu: remove duplicate cg/pg wrapper functions Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Acked-by: Christian König<christian.koenig@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
f7a9ee81 |
|
29-Mar-2018 |
Andrey Grodzovsky <andrey.grodzovsky@amd.com> |
drm/amdgpu: Add support for SRBM selection v3 Also remove code duplication in write and read regs functions. This also fixes potential missing unlock in amdgpu_debugfs_regs_write in case get_user would fail. v2: Add SRBM mutex locking. v3: Fix TO counter and fix comment location. Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
b905090d |
|
12-Mar-2018 |
Rex Zhu <Rex.Zhu@amd.com> |
drm/amdgpu: Remove wrapper layer of smu ip functions 1. delete amdgpu_powerplay.c used for wrapping smu ip functions 2. delete struct pp_instance, 3. make struct hwmgr as the smu hw handle. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
5494d864 |
|
09-Mar-2018 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: move getting pcie info to common code No need to replicate it in several places. Reviewed-by: Rex Zhu <rezhu@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
eab3de23 |
|
14-Mar-2018 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: explicit give BO type to amdgpu_bo_create Drop the "kernel" and sg parameter and give the BO type to create explicit to amdgpu_bo_create instead of figuring it out from the parameters. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Roger He <Hongbo.He@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
421a2a30 |
|
04-Jan-2018 |
Monk Liu <Monk.Liu@amd.com> |
drm/amdgpu: implement mmio byte access helper for MB mailbox registers can be accessed with a byte boundry according to BIF team, so this patch prepares register byte access and will be used by following patches. Actually, for mailbox registers once the byte field is touched even not changed, the mailbox behaves, so we need the byte width accessing to those sort of regs. Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Pixel Ding <Pixel.Ding@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
c396ef9b |
|
01-Mar-2018 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: move some functions into amdgpu_ttm.h Those belong to the TTM handling. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
c41d1cf6 |
|
24-Dec-2017 |
Monk Liu <Monk.Liu@amd.com> |
drm/amdgpu: cleanups for vram lost handling 1)create a routine "handle_vram_lost" to do the vram recovery, and put it into amdgpu_device_reset/reset_sriov, this way no need of the extra paramter to hold the VRAM LOST information and the related macros can be removed. 3)show vram_recover failure if time out, and set TMO equal to lockup_timeout if vram_recover is under SRIOV runtime mode. 4)report error if any ip reset failed for SR-IOV Signed-off-by: Monk Liu <Monk.Liu@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Acked-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
f812dec5 |
|
29-Dec-2017 |
Monk Liu <Monk.Liu@amd.com> |
drm/amdgpu: fix&cleanups for wb_clear fix: should do right shift on wb before clearing cleanups: 1,should memset all wb buffer 2,set max wb number to 128 (total 4KB) is big enough Signed-off-by: Monk Liu <Monk.Liu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
73469585 |
|
29-Dec-2017 |
Monk Liu <Monk.Liu@amd.com> |
drm/amdgpu: fix&cleanups for wb_clear fix: should do right shift on wb before clearing cleanups: 1,should memset all wb buffer 2,set max wb number to 128 (total 4KB) is big enough Signed-off-by: Monk Liu <Monk.Liu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
92e71b06 |
|
22-Feb-2018 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: use the TTM dummy page instead of allocating one We have a global dummy page in TTM, use that one instead of allocating a new one. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
5a13761f |
|
16-Feb-2018 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: implement amdgpu_gem_map_(attach/detach) Instead of the pin/unpin callback implement the attach/detach ones. Functional identical, but allows us access to the attachment. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
c633c00b |
|
04-Feb-2018 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: separate PASID mapping from VM flush v2 Stuffing the PASID mapping into the VM flush isn't flexible enough since the PASID mapping changes not as often as we need a VM flush. v2: add missing use of gmc_v7_0_emit_pasid_mapping Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
9475a943 |
|
01-Feb-2018 |
Shaoyun Liu <Shaoyun.Liu@amd.com> |
drm/amdgpu: Add place holder for soc15 asic init on emulation Add common smu_soc_asic_init function to emulate the sillicon post sequence Signed-off-by: Shaoyun Liu <Shaoyun.Liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
bfca0289 |
|
01-Feb-2018 |
Shaoyun Liu <Shaoyun.Liu@amd.com> |
drm/amdgpu: Basic emulation support Add amdgpu_emu_mode module parameter to control the emulation mode Avoid vbios operation on emulation since there is no vbios post duirng emulation, use the common hw_init to simulate the post Signed-off-by: Shaoyun Liu <Shaoyun.Liu@amd.com> Acked-By: Alex Deucher <alexander.deucher@amd.com> Acked-By: Christian Konig <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
a3405d0c |
|
01-Feb-2018 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: remove unused display_vblank_wait interface No longer used since we changed the MC programming sequence. Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
c1e877da |
|
25-Jan-2018 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: add new emit_reg_wait callback Allows us to wait for a register value/mask on a ring. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Felix Kuehling <felix.kuehling@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
44e1baeb |
|
24-Jan-2018 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: revert "Add support for filling a buffer with 64 bit value" This reverts commit 7bdc53f925af085ffa0580f10489f82b36cc2f1c and commit 330df03b3abf944f8f5180f2abc61367749984c0. Neither are needed any more. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
166140fb |
|
19-Jan-2018 |
Samuel Li <Samuel.Li@amd.com> |
drm/amdgpu: rename amdgpu_update_display_priority Rename as amdgpu_display_update_priority for consistency. Signed-off-by: Samuel Li <Samuel.Li@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
2ee150cd |
|
19-Jan-2018 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: remove now superflous *_hdp operation All HDP invalidation and most flush can now be replaced by the generic ASIC function. Signed-off-by: Christian König <christian.koenig@amd.com> Acked-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
69882565 |
|
19-Jan-2018 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: add optional ring to *_hdp callbacks This adds an optional ring to the invalidate_hdp and flush_hdp callbacks. If the ring isn't specified or the emit_wreg function not available the HDP operation will be done with the CPU otherwise by writing on the ring. Signed-off-by: Christian König <christian.koenig@amd.com> Acked-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
7ef11047 |
|
12-Jan-2018 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: add new amdgpu_gmc_emit_flush_gpu_tlb callback Add a new GMC function to unify vm flushing. Signed-off-by: Christian König <christian.koenig@amd.com> Acked-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
5a4633c4 |
|
08-Jan-2018 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: forward pasid to backend flush implementations rd the pasid from the VM code to the emit_vm_flush function and update all implementations with the new parameter. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
132f34e4 |
|
12-Jan-2018 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: move struct gart_funcs into amdgpu_gmc.h And rename it to struct gmc_funcs. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Samuel Li <Samuel.Li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
770d13b1 |
|
12-Jan-2018 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: move struct amdgpu_mc into amdgpu_gmc.h And rename it to amdgpu_gmc as well. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Samuel Li <Samuel.Li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
da320625 |
|
12-Jan-2018 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: remove agp_base No AGP support for in this driver. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Samuel Li <Samuel.Li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
09052fc3 |
|
08-Dec-2017 |
Samuel Li <Samuel.Li@amd.com> |
drm/amdgpu: Move to gtt before cpu accesses dma buf. To improve cpu read performance. This is implemented for APUs currently. v2: Adapt to change https://lists.freedesktop.org/archives/amd-gfx/2017-October/015174.html v3: Adapt to change "forward begin_cpu_access callback to drivers" v4: Instead of v3, reuse drm_gem dmabuf_ops here. Also some minor fixes as suggested. v5: only set dma_buf ops when it is valid (Samuel) Signed-off-by: Samuel Li <Samuel.Li@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
2df1b8b6 |
|
06-Sep-2017 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: add new asic callbacks for HDP flush/invalidation Needed to properly flush the HDP cache with the CPU from rather than the GPU. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Samuel Li <Samuel.Li@amd.com>
|
#
fd5fd480 |
|
08-Feb-2018 |
Chunming Zhou <david1.zhou@amd.com> |
drm/amdgpu: only enable swiotlb alloc when need v2 get the max io mapping address of system memory to see if it is over our card accessing range. v2: move checking later Signed-off-by: Chunming Zhou <david1.zhou@amd.com> Reviewed-by: Monk Liu <monk.liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180209024410.1469-2-david1.zhou@amd.com
|
#
c4f46f22 |
|
18-Dec-2017 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: rename vm_id to vmid sed -i "s/vm_id/vmid/g" drivers/gpu/drm/amd/amdgpu/*.c sed -i "s/vm_id/vmid/g" drivers/gpu/drm/amd/amdgpu/*.h Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
6a42fd6f |
|
05-Dec-2017 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: implement 2+1 PD support for Raven v3 Instead of falling back to 2 level and very limited address space use 2+1 PD support and 128TB + 512GB of virtual address space. v2: cleanup defines, rebase on top of level enum v3: fix inverted check in hardware setup Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-and-Tested-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
041d9d93 |
|
15-Dec-2017 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: rename amdgpu_get_pcie_info add device to the name for consistency. Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
6b8f4ee5 |
|
15-Dec-2017 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: move amdgpu_need_backup to amdgpu_object.c It's the only place it's used. Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
5f152b5e |
|
15-Dec-2017 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: rename amdgpu_gpu_recover add device to the name for consistency. Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
55e0037a |
|
15-Dec-2017 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: move dummy page functions to amdgpu_gart.c It's the only place they are used. Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
39c640c0 |
|
15-Dec-2017 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: rename amdgpu_need_post add device to the name for consistency. Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
2990a1fc |
|
15-Dec-2017 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: rename ip block helper functions add device to the name for consistency. Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
f5ec697e |
|
14-Dec-2017 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: move fw_reserve functions to amdgpu_ttm.c It's the only place they are used. Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
2543e28a |
|
14-Dec-2017 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: rename amdgpu_*_location functions add device to the name for consistency. Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
22cb0164 |
|
14-Dec-2017 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: move amdgpu_doorbell_get_kfd_info to amdgpu_amdkfd.c It's the only place it's used. Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
8111c387 |
|
14-Dec-2017 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: rename amdgpu_pci_config_reset add device for consistency with other functions in this file. Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
9c3f2b54 |
|
14-Dec-2017 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: rename amdgpu_program_register_sequence add device for consistency with other functions in this file. Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
131b4b36 |
|
14-Dec-2017 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: rename amdgpu_wb_* functions add device for consistency. Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
75758255 |
|
14-Dec-2017 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: move debugfs functions to their own file amdgpu_device.c was getting pretty cluttered. Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
cdd61df6 |
|
14-Dec-2017 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: rename amdgpu_suspend to amdgpu_device_ip_suspend for consistency with the other functions in that file. Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
dcebf026 |
|
12-Dec-2017 |
Andrey Grodzovsky <andrey.grodzovsky@amd.com> |
drm/amdgpu: Add gpu_recovery parameter Add new parameter to control GPU recovery procedure. v2: Add auto logic where reset is disabled for bare metal and enabled for SR-IOV. Allow forced reset from debugfs. Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
670b603c |
|
08-Dec-2017 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: drop the bios scratch reg callbacks from nbio They are not used any longer. We get the scratch register locations from the vbios directly now. Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
bf383fb6 |
|
08-Dec-2017 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: convert nbio to use callbacks (v2) Cleans up and consolidates all of the per-asic logic. v2: squash in "drm/amdgpu: fix NULL err for sriov detect" (Chunming) Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
3de676d8 |
|
29-Nov-2017 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: allow get_vm_pde to change flags as well And also provide the level for which we need a PDE. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
763efb6c |
|
06-Dec-2017 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: cleanup debugfs handling a bit Remove the superflous .debugfs_init callback and register all files in amdgpu_device.c in just one function. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
ebdebf42 |
|
08-Dec-2017 |
Flora Cui <flora.cui@amd.com> |
drm/amdgpu: add amdgpu interface to query cu info Signed-off-by: Flora Cui <flora.cui@amd.com> Signed-off-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com> Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Oded Gabbay <oded.gabbay@gmail.com> Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com>
|
#
946a4d5b |
|
28-Nov-2017 |
Shaoyun Liu <Shaoyun.Liu@amd.com> |
drm/amdgpu: Avoid use SOC15_REG_OFFSET in static const array Handle dynamic offsets correctly in static arrays. Acked-by: Christian Konig <christian.koenig@amd.com> Signed-off-by: Shaoyun Liu <Shaoyun.Liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
4522824c |
|
27-Nov-2017 |
Shaoyun Liu <Shaoyun.Liu@amd.com> |
drm/amdgpu: Dynamic initialize IP base offset The base offsets of the IP blocks may change across asics even though the relative register offsets are the same for an IP. Handle this dynamically. Acked-by: Christian Konig <christian.koenig@amd.com> Signed-off-by: Shaoyun Liu <Shaoyun.Liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
1b1f42d8 |
|
06-Dec-2017 |
Lucas Stach <l.stach@pengutronix.de> |
drm: move amd_gpu_scheduler into common location This moves and renames the AMDGPU scheduler to a common location in DRM in order to facilitate re-use by other drivers. This is mostly a straight forward rename with no code changes. One notable exception is the function to_drm_sched_fence(), which is no longer a inline header function to avoid the need to export the drm_sched_fence_ops_scheduled and drm_sched_fence_ops_finished structures. Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
cebb52b7 |
|
13-Nov-2017 |
Andrey Grodzovsky <andrey.grodzovsky@amd.com> |
drm/amdgpu: Get rid of dep_sync as a seperate object. Instead mark fence as explicit in it's amdgpu_sync_entry. v2: Fix use after free bug and add new parameter description. Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
f59548c8 |
|
13-Nov-2017 |
Monk Liu <Monk.Liu@amd.com> |
drm/amdgpu:fix NULL pointer access during drv remove NULL pointer is because original logic will step into set_pde_pte() even after the gart.ptr is freed due to there are twice gart_unbind() on all gart area. also, there are other minor fixes: 1,since gart_init only create dummy page, the corresponding gart_fini shouldn't do more like unbinding all GART, this is unnecessary because in driver fini stage all GART unbinding had already been done during each IP's SW_FINI (GMC's SW_FINI is the last one called), so remove the step for the GART unbinding in gart_fini(). 2,gart_fini() is already invoked during each GMC IP's gart_fini routine,e.g. gmc_vx_0_gart_fini(), so no need to manually call it during ttm_fini(). 3,amdgpu_gem_force_release() should be put ahead of amdgpu_vm_manager_fini() Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
d6895ad3 |
|
28-Feb-2017 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: resize VRAM BAR for CPU access v6 Try to resize BAR0 to let CPU access all of VRAM. v2: rebased, style cleanups, disable mem decode before resize, handle gmc_v9 as well, round size up to power of two. v3: handle gmc_v6 as well, release and reassign all BARs in the driver. v4: rename new function to amdgpu_device_resize_fb_bar, reenable mem decoding only if all resources are assigned. v5: reorder resource release, return -ENODEV instead of BUG_ON(). v6: squash in rebase fix Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
c1c7ce8f |
|
16-Oct-2017 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: move GART recovery into GTT manager v2 The GTT manager handles the GART address space anyway, so it is completely pointless to keep the same information around twice. v2: rebased Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
13a752e3 |
|
17-Oct-2017 |
Monk Liu <Monk.Liu@amd.com> |
drm/amdgpu:cleanup in_sriov_reset and lock_reset since now gpu reset is unified with gpu_recover for both bare-metal and SR-IOV: 1)rename in_sriov_reset to in_gpu_reset 2)move lock_reset from adev->virt to adev Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
5740682e |
|
25-Oct-2017 |
Monk Liu <Monk.Liu@amd.com> |
drm/amdgpu:implement new GPU recover(v3) 1,new imple names amdgpu_gpu_recover which gives more hint on what it does compared with gpu_reset 2,gpu_recover unify bare-metal and SR-IOV, only the asic reset part is implemented differently 3,gpu_recover will increase hang job karma and mark its entity/context as guilty if exceeds limit V2: 4,in scheduler main routine the job from guilty context will be immedialy fake signaled after it poped from queue and its fence be set with "-ECANCELED" error 5,in scheduler recovery routine all jobs from the guilty entity would be dropped 6,in run_job() routine the real IB submission would be skipped if @skip parameter equales true or there was VRAM lost occured. V3: 7,replace deprecated gpu reset, use new gpu recover Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
c79563a3 |
|
29-Sep-2017 |
Rex Zhu <Rex.Zhu@amd.com> |
drm/amdgpu: add header kgd_pp_interface.h move powerplay and amdgpu shared structures and definitions to kgd_pp_interface.h. This is the interface between the base driver and powerplay. Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
11dc9364 |
|
29-Sep-2017 |
Rex Zhu <Rex.Zhu@amd.com> |
drm/amdgpu: move struct amd_powerplay to amdgpu.h Clean up the interface. Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
668ca1b4 |
|
17-Oct-2017 |
Monk Liu <Monk.Liu@amd.com> |
drm/amdgpu:don't change ctx->reset_couner upon query reset_counter marks the reset counter number once the context is created, shouldn't be changed due to query. To keep U/K interface on the ctx_query and keep ctx's reset_counter logic compatible with GPU RESET feature, now use another var named "reset_counter_query" to replace the original checked & updated in amdgpu_ctx_query. Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
1102900d |
|
22-Oct-2017 |
Monk Liu <Monk.Liu@amd.com> |
drm/amdgpu:pass ctx->guilty address to entity init this way the real interested guilty is connected to entity->guilty pointer, and we can use entity->pointer later in gpu recovery procedure Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Chunming Zhou <David1.Zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
fa7c7939 |
|
22-Nov-2017 |
Michel Dänzer <michel.daenzer@amd.com> |
drm/amdgpu: Use unsigned ring indices in amdgpu_queue_mgr_map This matches the corresponding UAPI fields. Treating the ring index as signed could result in accessing random unrelated memory if the MSB was set. Fixes: effd924d2f3b ("drm/amdgpu: untie user ring ids from kernel ring ids v6") Cc: stable@vger.kernel.org Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
b43aaee6 |
|
21-Nov-2017 |
Leo Liu <leo.liu@amd.com> |
drm/amdgpu: move UVD/VCE and VCN structure out from union With the enablement of VCN Dec and Enc from user space, User space queries kernel for the IP information, if HW has UVD/VCE, the info comes from these IP blocks, but this could end up mis-interpret for VCN when they are in the union, the other way same when HW with VCN block. Signed-off-by: Leo Liu <leo.liu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Fixes: 95d0906f8506 ("drm/amdgpu: add initial vcn support and decode tests") Cc: stable@vger.kernel.org Reviewed-and-Tested-by: Michel Dänzer <michel.daenzer@amd.com>
|
#
43ca8efa |
|
13-Oct-2017 |
pding <Pixel.Ding@amd.com> |
drm/amdgpu: busywait KIQ register accessing (v4) Register accessing is performed when IRQ is disabled. Never sleep in this function. Known issue: dead sleep in many use cases of index/data registers. v2: - wrap polling fence functions. - don't trigger IRQ for polling in case of wrongly fence signal. v3: - handle wrap round gracefully. - add comments for polling function v4: - don't return negative timeout confused with error code Signed-off-by: pding <Pixel.Ding@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
896a664c |
|
17-Oct-2017 |
Monk Liu <Monk.Liu@amd.com> |
drm/amdgpu:reduce wb to 512 slot with current WB usage we only use 57 slots, so 512 is extreamly sufficient, and reduce to 512 can make WB fit into one page. Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
e55f2b64 |
|
09-Oct-2017 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: move the VRAM lost counter per context Instead of per device track the VRAM lost per context and return ECANCELED instead of ENODEV. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
14e47f93 |
|
09-Oct-2017 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: keep copy of VRAM lost counter in job Instead of reading the current counter from fpriv. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
0ae94444 |
|
10-Oct-2017 |
Andrey Grodzovsky <andrey.grodzovsky@amd.com> |
drm/amdgpu: Move old fence waiting before reservation lock is aquired v2 Helps avoiding deadlock during GPU reset. Added mutex to amdgpu_ctx to preserve order of fences on a ring. v2: Put waiting logic in a function in a seperate function in amdgpu_ctx.c Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
c23be4ae |
|
06-Jun-2017 |
Andres Rodriguez <andresx7@gmail.com> |
drm/amdgpu: add plumbing for ctx priority changes v2 Introduce amdgpu_ctx_priority_override(). A mechanism to override a context's priority. An override can be terminated by setting the override to AMD_SCHED_PRIORITY_UNSET. v2: change refcounted interface for a direct set Signed-off-by: Andres Rodriguez <andresx7@gmail.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
b8866c26 |
|
28-Apr-2017 |
Andres Rodriguez <andresx7@gmail.com> |
drm/amdgpu: implement ring set_priority for gfx_v8 compute v9 Programming CP_HQD_QUEUE_PRIORITY enables a queue to take priority over other queues on the same pipe. Multiple queues on a pipe are timesliced so this gives us full precedence over other queues. Programming CP_HQD_PIPE_PRIORITY changes the SPI_ARB_PRIORITY of the wave as follows: 0x2: CS_H 0x1: CS_M 0x0: CS_L The SPI block will then dispatch work according to the policy set by SPI_ARB_PRIORITY. In the current policy CS_H is higher priority than gfx. In order to prevent getting stuck in loops of resources bouncing between GFX and high priority compute and introducing further latency, we statically reserve a portion of the pipe. v2: fix srbm_select to ring->queue and use ring->funcs->type v3: use AMD_SCHED_PRIORITY_* instead of AMDGPU_CTX_PRIORITY_* v4: switch int to enum amd_sched_priority v5: corresponding changes for srbm_lock v6: change CU reservation to PIPE_PERCENT allocation v7: use kiq instead of MMIO v8: back to MMIO, and make the implementation sleep safe. v9: corresponding changes for splitting HIGH into _HW/_SW Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Andres Rodriguez <andresx7@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
a05502e5 |
|
29-Sep-2017 |
Horace Chen <horace.chen@amd.com> |
drm/amdgpu: Reserve shared memory on VRAM for SR-IOV SR-IOV need to reserve a piece of shared VRAM at the exact place to exchange data betweem PF and VF. The start address and size of the shared mem are passed to guest through VBIOS structure VRAM_UsageByFirmware. VRAM_UsageByFirmware is a general feature in VBIOS, it indicates that VBIOS need to reserve a piece of memory on the VRAM. Because the mem address is specified. Reserve it early in amdgpu_ttm_init to make sure that it can monoplize the space. Signed-off-by: Horace Chen <horace.chen@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
7ca24cf2 |
|
12-Sep-2017 |
Marek Olšák <marek.olsak@amd.com> |
drm/amdgpu: add FENCE_TO_HANDLE ioctl that returns syncobj or sync_file for being able to convert an amdgpu fence into one of the handles. Mesa will use this. Reviewed-by: Dave Airlie <airlied@redhat.com> Signed-off-by: Marek Olšák <marek.olsak@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
6d07fe7b |
|
25-Sep-2017 |
Rex Zhu <Rex.Zhu@amd.com> |
drm/amdgpu: delete pp_enable in adev amdgpu not care powerplay or dpm is enabled. just check ip functions and pp functions Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
4a75aefe |
|
25-Sep-2017 |
Andres Rodriguez <andresx7@gmail.com> |
drm/amdgpu: add option for force enable multipipe policy for compute Useful for testing the effects of multipipe compute without recompiling. Acked-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Andres Rodriguez <andresx7@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
02e749dc |
|
12-Sep-2017 |
Harry Wentland <harry.wentland@amd.com> |
drm/amdgpu: Add dc_log module parameter We want to make DC less chatty but still allow bug reporters to provide more detailed logs. Signed-off-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
4562236b |
|
12-Sep-2017 |
Harry Wentland <harry.wentland@amd.com> |
drm/amd/dc: Add dc display driver (v2) Supported DCE versions: 8.0, 10.0, 11.0, 11.2 v2: rebase against 4.11 Signed-off-by: Harry Wentland <harry.wentland@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
dfced2e4 |
|
22-Aug-2017 |
Samuel Li <Samuel.Li@amd.com> |
drm/amdgpu: Add gem_prime_mmap support v2: drop hdp invalidate/flush. v3: honor pgoff during prime mmap. Add a barrier after cpu access. v4: drop begin/end_cpu_access() for now, revisit later. Signed-off-by: Samuel Li <Samuel.Li@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
e6d92197 |
|
18-Sep-2017 |
Yong Zhao <yong.zhao@amd.com> |
drm/amdgpu: Add copy_pte_num_dw member in amdgpu_vm_pte_funcs Use it to replace the hard coded value in amdgpu_vm_bo_update_mapping(). Signed-off-by: Yong Zhao <yong.zhao@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
7bdc53f9 |
|
15-Sep-2017 |
Yong Zhao <yong.zhao@amd.com> |
drm/amdgpu: Fix a bug in amdgpu_fill_buffer() When max_bytes is not 8 bytes aligned and bo size is larger than max_bytes, the last 8 bytes in a ttm node may be left unchanged. For example, on pre SDMA 4.0, max_bytes = 0x1fffff, and the bo size is 0x200000, the problem will happen. In order to fix the problem, we separately store the max nums of PTEs/PDEs a single operation can set in amdgpu_vm_pte_funcs structure, rather than inferring it from bytes limit of SDMA constant fill, i.e. fill_max_bytes. Together with the fix, we replace the hard code value "10" in amdgpu_vm_bo_update_mapping() with the corresponding values from structure amdgpu_vm_pte_funcs. Signed-off-by: Yong Zhao <yong.zhao@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
d59c026b |
|
15-Sep-2017 |
Monk Liu <Monk.Liu@amd.com> |
drm/amdgpu/sriov:fix memory leak after gpu reset GPU reset will require all hw doing hw_init thus ucode_init_bo will be invoked again, which lead to memory leak skip the fw_buf allocation during sriov gpu reset to avoid memory leak. Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
eb01abc7 |
|
14-Sep-2017 |
Monk Liu <Monk.Liu@amd.com> |
drm/amdgpu:make ctx_add_fence interruptible(v2) otherwise a gpu hang will make application couldn't be killed under timedout=0 mode v2: Fix memoryleak job/job->s_fence issue unlock mn remove the ERROR msg after waiting being interrupted Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
3224a12b |
|
15-Sep-2017 |
Monk Liu <Monk.Liu@amd.com> |
drm/amdgpu/sriov:move in_reset to adev and rename currently in_reset is only used in sriov gpu reset, and it will be used for other non-gfx hw component later, like PSP, so move it from gfx to adev and rename to in_sriov_reset make more sense. Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
0b693f0b |
|
19-Sep-2017 |
Rex Zhu <Rex.Zhu@amd.com> |
drm/amdgpu: fix checkpatch.pl warning to amdgpu_drv.c fix checkpatch.pl WARNING: Prefer 'unsigned int' to bare use of 'unsigned' Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
00ecd8a2 |
|
26-Aug-2017 |
Felix Kuehling <Felix.Kuehling@amd.com> |
drm/amdgpu: Add prescreening stage in IH processing (v2) To filter out high-frequency interrupts that can be safely ignored. v2: squash in trivial typo fix for si (Alex) Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
9a189996 |
|
12-Sep-2017 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: move MMU notifier related defines to amdgpu_mn.h Just some cleanup. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
711becf0 |
|
08-Sep-2017 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: move amdgpu_ttm_tt_* declarations into amdgpu_ttm.h Just some cleanup. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
1ed3d256 |
|
05-Sep-2017 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: keep the MMU lock until the update ends v4 This is quite controversial because it adds another lock which is held during page table updates, but I don't see much other option. v2: allow multiple updates to be in flight at the same time v3: simplify the patch, take the read side only once v4: correctly fix rebase conflict Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
9cca0b8e |
|
06-Sep-2017 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: move amdgpu_cs_sysvm_access_required into find_mapping When we need to find the mapping we need sysvm access anyway. Signed-off-by: Christian König <christian.koenig@amd.com> Acked-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
3fe89771 |
|
12-Sep-2017 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: stop reserving the BO in the MMU callback v3 Instead take the callback lock during the final parts of CS. This should solve the last remaining locking order problems with BO reservations. v2: rebase, make dummy functions static inline v3: add one more missing inline and comments Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
1b0c0f9d |
|
05-Sep-2017 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: move userptr BOs to CPU domain during CS v2 Instead of moving them in the MMU notifier move them during CS. v2: still mark pages as accessed/dirty Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> (v1) Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
ca666a3c |
|
05-Sep-2017 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: stop using BO status for user pages Instead use a counter to figure out if we need to set new pages or not. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
a216ab09 |
|
02-Sep-2017 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: fix userptr put_page handling Move calling put_page into the unpopulate callback. Otherwise we mess up the pages reference count when it is unbound multiple times. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
e1eb899b4 |
|
25-Aug-2017 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: add IOCTL interface for per VM BOs v3 Add the IOCTL interface so that applications can allocate per VM BOs. Still WIP since not all corner cases are tested yet, but this reduces average CS overhead for 10K BOs from 21ms down to 48us. v2: add some extra checks, remove the WIP tag v3: rename new flag to AMDGPU_GEM_CREATE_VM_ALWAYS_VALID Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
83e74db6 |
|
21-Aug-2017 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: add automatic per asic settings for gart_size We need a larger gart for asics that do not support GPUVM on all engines (e.g., MM) to make sure we have enough space for all gtt buffers in physical mode. Change the default size based on the asic type. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
db63042b |
|
21-Aug-2017 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: add automatic per asic settings for gart_size We need a larger gart for asics that do not support GPUVM on all engines (e.g., MM) to make sure we have enough space for all gtt buffers in physical mode. Change the default size based on the asic type. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
d07f14be |
|
15-Aug-2017 |
Roger He <Hongbo.He@amd.com> |
drm/amd/amdgpu: expose fragment size as module parameter (v2) Allow overrides on the command line. v2: agd: sqaush in spelling fix and bogus default value warning Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Roger He <Hongbo.He@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
0f4b3c68 |
|
31-Jul-2017 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: cleanup static CSA handling Move the CSA bo_va from the VM to the fpriv structure. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
3c848bb3 |
|
07-Aug-2017 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: move vram usage tracking into the vram manager v2 Looks like a better place for this. v2: use atomic64_t members instead Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
9255d77d |
|
07-Aug-2017 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: move gtt usage tracking into the gtt manager v2 It doesn't make much sense to count those numbers twice. v2: use and atomic64_t instead Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
5af2c10d |
|
08-Aug-2017 |
Kent Russell <kent.russell@amd.com> |
drm/amdgpu: Fix stolen typo Change "stollen" to "stolen" Signed-off-by: Kent Russell <kent.russell@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
97407b63 |
|
27-Jul-2017 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: use 256 bit buffers for all wb allocations (v2) May waste a bit of memory, but simplifies the interface significantly. v2: convert internal accounting to use 256bit slots Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
34c3a82b |
|
28-Jul-2017 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu/sdma4: drop allocation of poll_mem_offs We already allocate this as part of the ring structure, use that instead. Cc: Frank Min <Frank.Min@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
eacf3e14 |
|
27-Jul-2017 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: make wb 256bit function names consistent Use a lower case b to be consistent with the other wb functions. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
9124a398 |
|
20-Jul-2017 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: move some defines around Move amdgpu_bo and related structures into amdgpu_object.h. Move amdgpu_bo_list structures to the amdgpu_bo_list functions. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
f5e1c740 |
|
20-Jul-2017 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: cleanup kptr handling Don't keep around the same pointer twice. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
51668b0b |
|
28-Jun-2017 |
Frank Min <Frank.Min@amd.com> |
drm/amdgpu/sdma4: Enable sdma poll mem addr on vega10 for SRIOV While doing flr on VFs, there is possibility to lost the doorbell writing for sdma, so enable poll mem for sdma, then sdma fw would check the pollmem holding wptr. Signed-off-by: Frank Min <Frank.Min@amd.com> Signed-off-by: Xiangliang.Yu <Xiangliang.Yu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
4ed11d79 |
|
11-Jun-2017 |
Frank Min <Frank.Min@amd.com> |
drm/amdgpu: According hardware design revert vce and uvd doorbell assignment Now uvd doorbell is from 0xf8-0xfb and vce doorbell is from 0xfc-0xff Signed-off-by: Frank Min <Frank.Min@amd.com> Signed-off-by: Xiangliang.Yu <Xiangliang.Yu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
0915fdbc |
|
19-Jun-2017 |
Monk Liu <Monk.Liu@amd.com> |
drm/amdgpu:fix gfx fence allocate size 1, for sriov, we need 8dw for the gfx fence due to CP behaviour 2, cleanup wrong logic in wptr/rptr wb alloc and free Change-Id: Ifbfed17a4621dae57244942ffac7de1743de0294 Signed-off-by: Monk Liu <Monk.Liu@amd.com> Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
a667386c |
|
15-Jul-2016 |
Felix Kuehling <Felix.Kuehling@amd.com> |
drm/amdgpu: Make SDMA phase quantum configurable Set a configurable SDMA phase quantum when enabling SDMA context switching. The default value significantly reduces SDMA latency in page table updates when user-mode SDMA queues have concurrent activity, compared to the initial HW setting. Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Andres Rodriguez <andres.rodriguez@amd.com> Reviewed-by: Shaoyun Liu <shaoyun.liu@amd.com> Acked-by: Chunming Zhou <david1.zhou@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
00f06b24 |
|
27-Jun-2017 |
John Brooks <john@fastquake.com> |
drm/amdgpu: Throttle visible VRAM moves separately The BO move throttling code is designed to allow VRAM to fill quickly if it is relatively empty. However, this does not take into account situations where the visible VRAM is smaller than total VRAM, and total VRAM may not be close to full but the visible VRAM segment is under pressure. In such situations, visible VRAM would experience unrestricted swapping and performance would drop. Add a separate counter specifically for moves involving visible VRAM, and check it before moving BOs there. v2: Only perform calculations for separate counter if visible VRAM is smaller than total VRAM. (Michel Dänzer) v3: [Michel Dänzer] * Use BO's location rather than the AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED flag to determine whether to account a move for visible VRAM in most cases. * Use a single if (adev->mc.visible_vram_size < adev->mc.real_vram_size) { block in amdgpu_cs_get_threshold_for_moves. Fixes: 95844d20ae02 (drm/amdgpu: throttle buffer migrations at CS using a fixed MBps limit (v2)) Signed-off-by: John Brooks <john@fastquake.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
218b5dcd |
|
27-Jun-2017 |
John Brooks <john@fastquake.com> |
drm/amdgpu: Add vis_vramlimit module parameter Allow specifying a limit on visible VRAM via a module parameter. This is helpful for testing performance under visible VRAM pressure. v2: Add cast to 64-bit (Christian König) Signed-off-by: John Brooks <john@fastquake.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
f9321cc4 |
|
07-Jul-2017 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: change gartsize default to 256MB Limit the default GART size and save a lot of VRAM. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
36d38372 |
|
07-Jul-2017 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: add new gttsize module parameter v2 This allows setting the gtt size independent of the gart size. v2: fix copy and paste typo Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
6f02a696 |
|
07-Jul-2017 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: consistent name all GART related parts Rename symbols from gtt_ to gart_ as appropriate. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
ed21c047 |
|
06-Jul-2017 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: remove gtt_base_align handling Not used any more. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
3490bdb5 |
|
06-Jul-2017 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: move GART struct and function into amdgpu_gart.h v2 No functional change, just cleanup. v2: rebased, keep gart name. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
16abb5d2 |
|
03-Jul-2017 |
Evan Quan <evan.quan@amd.com> |
drm/amd/powerplay: added new se_cac_idx r/w APIs v2 - v2: added missing spinlock init Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
0c2c421e |
|
29-Jun-2017 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: add amdgpu_gart_map function v2 This allows us to write the mapped PTEs into an IB instead of the table directly. v2: fix build with debugfs enabled, remove unused assignment Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
47ed4e1c |
|
03-Jul-2017 |
Ken Wang <Ken.Wang@amd.com> |
drm/amdgpu: add workaround for S3 issues on some vega10 boards Certain MC registers need a delay after writing them to properly update in the init sequence. Signed-off-by: Ken Wang <Ken.Wang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
e8110b1c |
|
28-Jun-2017 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: move ring helpers to amdgpu_ring.h Keep them where they belong. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Acked-by: Felix Kuehling <Felix.Kuehling@amd.com>
|
#
011d4bbe |
|
26-Jun-2017 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: cleanup initializing gtt_size Stop spreading the code over all GMC generations. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
e4f6b39e |
|
08-Dec-2016 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: remove *_mc_access from display funcs These are no longer needed now that we use the fb_location programmed by the vbios. Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
b3fba8ad |
|
22-Nov-2016 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: drop set_vga_render_state from display funcs Not used. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
9211c784 |
|
20-Jun-2017 |
Alex Xie <AlexBin.Xie@amd.com> |
drm/amdgpu: Make amdgpu_cs_parser_init static (v2) The function is called only once inside the .c file. v2: update the commit message (Michel) Signed-off-by: Alex Xie <AlexBin.Xie@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
dbfe85ea |
|
19-Jun-2017 |
Flora Cui <Flora.Cui@amd.com> |
drm/amdgpu: Fix the exported always on CU bitmap Newer asics with 4 SEs are not able to fit the entire bitmask in the original field, use an array instead. v2: keep cu_ao_mask for backward compatibility. Signed-off-by: Flora Cui <Flora.Cui@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
5ac55629 |
|
16-Jun-2017 |
Alex Xie <AlexBin.Xie@amd.com> |
drm/amdgpu: Optimize mutex usage (v4) In original function amdgpu_bo_list_get, the waiting for result->lock can be quite long while mutex bo_list_lock was holding. It can make other tasks waiting for bo_list_lock for long period. Secondly, this patch allows several tasks(readers of idr) to proceed at the same time. v2: use rcu and kref (Dave Airlie and Christian König) v3: update v1 commit message (Michel Dänzer) v4: rebase on upstream (Alex Deucher) Signed-off-by: Alex Xie <AlexBin.Xie@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com>
|
#
660e8558 |
|
13-Mar-2017 |
Dave Airlie <airlied@redhat.com> |
amdgpu: use drm sync objects for shared semaphores (v6) This creates a new command submission chunk for amdgpu to add in and out sync objects around the submission. Sync objects are managed via the drm syncobj ioctls. The command submission interface is enhanced with two new chunks, one for syncobj pre submission dependencies, and one for post submission sync obj signalling, and just takes a list of handles for each. This is based on work originally done by David Zhou at AMD, with input from Christian Konig on what things should look like. In theory VkFences could be backed with sync objects and just get passed into the cs as syncobj handles as well. NOTE: this interface addition needs a version bump to expose it to userspace. TODO: update to dep_sync when rebasing onto amdgpu master. (with this - r-b from Christian) v1.1: keep file reference on import. v2: move to using syncobjs v2.1: change some APIs to just use p pointer. v3: make more robust against CS failures, we now add the wait sems but only remove them once the CS job has been submitted. v4: rewrite names of API and base on new syncobj code. v5: move post deps earlier, rename some apis v6: lookup post deps earlier, and just replace fences in post deps stage (Christian) Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Dave Airlie <airlied@redhat.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
ab4fe3e1 |
|
05-Jun-2017 |
Huang Rui <ray.huang@amd.com> |
drm/amdgpu: fix missed gpu info firmware when cache firmware during S3 gpu_info firmware is released after data is used. But when system enters into suspend, upper class driver will cache all firmware names. At that time, gpu_info will be failing to load. It seems an upper class issue, that we should not release gpu_info firmware until device finished. [ 903.236589] cache_firmware: amdgpu/vega10_sdma1.bin [ 903.236590] fw_set_page_data: fw-amdgpu/vega10_sdma1.bin buf=ffff88041eee10c0 data=ffffc90002561000 size=17408 [ 903.236591] cache_firmware: amdgpu/vega10_sdma1.bin ret=0 [ 903.464160] __allocate_fw_buf: fw-amdgpu/vega10_gpu_info.bin buf=ffff88041eee2c00 [ 903.471815] (NULL device *): loading /lib/firmware/updates/4.11.0-custom/amdgpu/vega10_gpu_info.bin failed with error -2 [ 903.482870] (NULL device *): loading /lib/firmware/updates/amdgpu/vega10_gpu_info.bin failed with error -2 [ 903.492716] (NULL device *): loading /lib/firmware/4.11.0-custom/amdgpu/vega10_gpu_info.bin failed with error -2 [ 903.503156] (NULL device *): direct-loading amdgpu/vega10_gpu_info.bin Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
51fd0370 |
|
09-Jun-2017 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu: add new member in gpu_info fw Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
a7dba648 |
|
08-Jun-2017 |
Alex Xie <AlexBin.Xie@amd.com> |
drm/amdgpu: remove duplicate function prototypes There are two identical function prototypes in same header file Signed-off-by: Alex Xie <AlexBin.Xie@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
9a4b7d4c |
|
09-Jun-2017 |
Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com> |
drm/amdgpu: Add vm context module param Add VM update mode module param (amdgpu.vm_update_mode) that can used to control how VM pde/pte are updated for Graphics and Compute. BIT0 controls Graphics and BIT1 Compute. BIT0 [= 0] Graphics updated by SDMA [= 1] by CPU BIT1 [= 0] Compute updated by SDMA [= 1] by CPU By default, only for large BAR system vm_update_mode = 2, indicating that Graphics VMs will be updated via SDMA and Compute VMs will be updated via CPU. And for all all other systems (by default) vm_update_mode = 0 Signed-off-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
6dd13096 |
|
05-Jun-2017 |
Felix Kuehling <Felix.Kuehling@amd.com> |
drm/amdgpu: Add module param to control SI support If AMDGPU supports SI, add a module parameter to control SI support. It's off by default in AMDGPU as long as SI suppost is experimental, while it is on by default in radeon. Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Acked-by: Michel Dänzer <michel.daenzer@amd.com> [ Michel Dänzer: Squash in amdgpu_si_support initialization fix ] Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
|
#
7df28986 |
|
05-Jun-2017 |
Felix Kuehling <Felix.Kuehling@amd.com> |
drm/amdgpu: Add module param to control CIK support If AMDGPU supports CIK, add a module parameter to control CIK support. It's on by default in AMDGPU, while it is off by default in radeon. Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Acked-by: Michel Dänzer <michel.daenzer@amd.com>
|
#
2db0cdbe |
|
06-Jun-2017 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: move mec queue helpers to amdgpu_gfx.h They are gfx related, not general helpers. Reviewed-by: Alex Xie <AlexBin.Xie@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
916910ad |
|
30-May-2017 |
Huang Rui <ray.huang@amd.com> |
drm/amdgpu: fix the gart table cleared issue for S3 Something writes over the first 8 MB so reserve this on vega10 until we root cause it. Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
795f2813 |
|
06-Mar-2017 |
Andres Rodriguez <andresx7@gmail.com> |
drm/amdgpu: implement lru amdgpu_queue_mgr policy for compute v4 Use an LRU policy to map usermode rings to HW compute queues. Most compute clients use one queue, and usually the first queue available. This results in poor pipe/queue work distribution when multiple compute apps are running. In most cases pipe 0 queue 0 is the only queue that gets used. In order to better distribute work across multiple HW queues, we adopt a policy to map the usermode ring ids to the LRU HW queue. This fixes a large majority of multi-app compute workloads sharing the same HW queue, even though 7 other queues are available. v2: use ring->funcs->type instead of ring->hw_ip v3: remove amdgpu_queue_mapper_funcs v4: change ring_lru_list_lock to spinlock, grab only once in lru_get() Signed-off-by: Andres Rodriguez <andresx7@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
effd924d |
|
15-Feb-2017 |
Andres Rodriguez <andresx7@gmail.com> |
drm/amdgpu: untie user ring ids from kernel ring ids v6 Add amdgpu_queue_mgr, a mechanism that allows disjointing usermode's ring ids from the kernel's ring ids. The queue manager maintains a per-file descriptor map of user ring ids to amdgpu_ring pointers. Once a map is created it is permanent (this is required to maintain FIFO execution guarantees for a context's ring). Different queue map policies can be configured for each HW IP. Currently all HW IPs use the identity mapper, i.e. kernel ring id is equal to the user ring id. The purpose of this mechanism is to distribute the load across multiple queues more effectively for HW IPs that support multiple rings. Userspace clients are unable to check whether a specific resource is in use by a different client. Therefore, it is up to the kernel driver to make the optimal choice. v2: remove amdgpu_queue_mapper_funcs v3: made amdgpu_queue_mgr per context instead of per-fd v4: add context_put on error paths v5: rebase and include new IPs UVD_ENC & VCN_* v6: drop unused amdgpu_ring_is_valid_index (Alex) Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Andres Rodriguez <andresx7@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
7b2124a5 |
|
05-Apr-2017 |
Andres Rodriguez <andresx7@gmail.com> |
drm/amdgpu: avoid KIQ clashing with compute or KFD queues v2 Instead of picking an arbitrary queue for KIQ, search for one according to policy. The queue must be unused. Also report the KIQ as an unavailable resource to KFD. In testing I ran into KCQ initialization issues when using pipes 2/3 of MEC2 for the KIQ. Therefore the policy disallows grabbing one of these. v2: fix (ring.me + 1) to (ring.me -1) in amdgpu_amdkfd_device_init Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Andres Rodriguez <andresx7@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
e33fec48 |
|
03-Feb-2017 |
Andres Rodriguez <andresx7@gmail.com> |
drm/amdgpu: allocate queues horizontally across pipes Pipes provide better concurrency than queues, therefore we want to make sure that apps use queues from different pipes whenever possible. Optimize for the trivial case where an app will consume rings in order, therefore we don't want adjacent rings to belong to the same pipe. Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net> Acked-by: Felix Kuehling <Felix.Kuehling@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Andres Rodriguez <andresx7@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
78c16834 |
|
01-Feb-2017 |
Andres Rodriguez <andresx7@gmail.com> |
drm/amdgpu: allow split of queues with kfd at queue granularity v4 Previously the queue/pipe split with kfd operated with pipe granularity. This patch allows amdgpu to take ownership of an arbitrary set of queues. It also consolidates the last few magic numbers in the compute initialization process into mec_init. v2: support for gfx9 v3: renamed AMDGPU_MAX_QUEUES to AMDGPU_MAX_COMPUTE_QUEUES v4: fix off-by-one in num_mec checks in *_compute_queue_acquire Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Andres Rodriguez <andresx7@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
42794b27 |
|
01-Feb-2017 |
Andres Rodriguez <andresx7@gmail.com> |
drm/amdgpu: take ownership of per-pipe configuration v3 Make amdgpu the owner of all per-pipe state of the HQDs. This change will allow us to split the queues between kfd and amdgpu with a queue granularity instead of pipe granularity. This patch fixes kfd allocating an HDP_EOP region for its 3 pipes which goes unused. v2: support for gfx9 v3: fix gfx7 HPD intitialization Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Andres Rodriguez <andresx7@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
b1166325 |
|
12-May-2017 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: cleanup adjust_mc_addr handling v4 Rename adjust_mc_addr to get_vm_pde and check the address bits in one place. v2: handle vcn as well, keep setting the valid bit manually, add a BUG_ON() for GMC v6, v7 and v8 as well. v3: handle vcn_v1_0_enc_ring_emit_vm_flush as well. v4: fix the BUG_ON mask for GFX6-8 Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
e8835e0e |
|
26-May-2017 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu: enable lbpw on raven Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
2dc80b00 |
|
24-May-2017 |
Shirish S <shirish.s@amd.com> |
drm/amdgpu: optimize amdgpu driver load & resume time amdgpu_device_resume() & amdgpu_device_init() have a high time consuming call of amdgpu_late_init() which sets the clock_gating state of all IP blocks and is blocking. This patch defers only this setting of clock gating state operation to post resume of amdgpu driver but ideally before the UI comes up or in some cases post ui as well. With this change the resume time of amdgpu_device comes down from 1.299s to 0.199s which further helps in reducing the overall system resume time. V1: made the optimization applicable during driver load as well. TEST:(For ChromiumOS on STONEY only) * UI comes up * amdgpu_late_init() call gets called consistently and no errors reported. Signed-off-by: Shirish S <shirish.s@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
68e2c5ff |
|
17-May-2017 |
Marek Olšák <marek.olsak@amd.com> |
drm/amdgpu: add an INFO query for monitoring VRAM CPU page faults v2: bump the DRM version Signed-off-by: Marek Olšák <marek.olsak@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
a340c7bc |
|
18-May-2017 |
Chunming Zhou <David1.Zhou@amd.com> |
drm/amdgpu: add dep_sync for amdgpu job The fence in dep_sync cannot be optimized. Signed-off-by: Chunming Zhou <David1.Zhou@amd.com> Tested and Reviewed-by: Roger.He <Hongbo.He@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
f1892138 |
|
15-May-2017 |
Chunming Zhou <David1.Zhou@amd.com> |
drm/amdgpu: return -ENODEV to user space when vram is lost v2 below ioctl will return -ENODEV: amdgpu_cs_ioctl amdgpu_cs_wait_ioctl amdgpu_cs_wait_fences_ioctl amdgpu_gem_va_ioctl amdgpu_info_ioctl v2: only for map and replace cases in amdgpu_gem_va_ioctl Signed-off-by: Chunming Zhou <David1.Zhou@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
0c49e0b8 |
|
15-May-2017 |
Chunming Zhou <David1.Zhou@amd.com> |
drm/amdgpu: check if vram is lost v2 backup first 64 byte of gart table as reset magic, check if magic is same after gpu hw reset. v2: use memcmp instead of manual innovation. Signed-off-by: Chunming Zhou <David1.Zhou@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
95aa13f6 |
|
11-May-2017 |
Leo Liu <leo.liu@amd.com> |
drm/amdgpu: move amdgpu_vcn structure to vcn header Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
95d0906f |
|
21-Dec-2016 |
Leo Liu <leo.liu@amd.com> |
drm/amdgpu: add initial vcn support and decode tests VCN is the new media block on Raven. Add core support and the ring and ib tests for decode. Signed-off-by: Leo Liu <leo.liu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
65781c78 |
|
10-May-2017 |
Monk Liu <Monk.Liu@amd.com> |
drm/amdgpu/SRIOV:implement guilty job TDR for(V2) 1,TDR will kickout guilty job if it hang exceed the threshold of the given one from kernel paramter "job_hang_limit", that way a bad command stream will not infinitly cause GPU hang. by default this threshold is 1 so a job will be kicked out after it hang. 2,if a job timeout TDR routine will not reset all sched/ring, instead if will only reset on the givn one which is indicated by @job of amdgpu_sriov_gpu_reset, that way we don't need to reset and recover each sched/ring if we already know which job cause GPU hang. 3,unblock sriov_gpu_reset for AI family. V2: 1:put kickout guilty job after sched parked. 2:since parking scheduler prior to kickout already occupies a while, we can do last check on the in question job before doing hw_reset. TODO: 1:when a job is considered as guilty, we should mark some flag in its fence status flag, and let UMD side aware that this fence signaling is not due to job complete but job hang. 2:if gpu reset cause all video memory lost, we need introduce a new policy to implement TDR, like drop all jobs not yet signaled, and all IOCTL on this device will return ERROR DEVICE_LOST. this will be implemented later. Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
b9bf33d5 |
|
11-May-2017 |
Chunming Zhou <David1.Zhou@amd.com> |
drm/amdgpu: make pipeline sync be in same place v2 v2: directly return for 'if' case. Signed-off-by: Chunming Zhou <David1.Zhou@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
df83d1eb |
|
09-May-2017 |
Chunming Zhou <David1.Zhou@amd.com> |
drm/amdgpu: add sched sync for amdgpu job v2 this is an improvement for previous patch, the sched_sync is to store fence that could be skipped as scheduled, when job is executed, we didn't need pipeline_sync if all fences in sched_sync are signalled, otherwise insert pipeline_sync still. v2: handle error when adding fence to sync failed. Signed-off-by: Chunming Zhou <David1.Zhou@amd.com> Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com> (v1) Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
738f64cc |
|
04-May-2017 |
Roger.He <Hongbo.He@amd.com> |
drm/amdgpu: extend lock range for race condition when gpu reset to cover below case: 1. A task gart bind/unbind but not add to adev->gtt_list yet 2. at this time gpu reset, gtt only recover those gtt in adev->gtt_list Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Roger.He <Hongbo.He@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
5b9c58f9 |
|
03-May-2017 |
Nikola Pajkovsky <npajkovsky@suse.cz> |
drm/amd/amdgpu: get rid of else branch else branch is pointless if it's right at the end of function and use unlikely() on err path. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Nikola Pajkovsky <npajkovsky@suse.cz> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
503bb31b |
|
03-May-2017 |
Monk Liu <Monk.Liu@amd.com> |
drm/amdgpu:cleanup flag not used Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
3b4d68e9 |
|
01-May-2017 |
Monk Liu <Monk.Liu@amd.com> |
drm/amdgpu:use FRAME_CNTL for new GFX ucode (v2) AI affected: CP/HW team requires KMD insert FRAME_CONTROL(end) after the last IB and before the fence of this DMAframe. this is to make sure the cache are flushed, and it's a must change no matter MCBP/SR-IOV or bare-metal case because new CP hw won't do the cache flush for each IB anymore, it just leaves it to KMD now. with this patch, certain MCBP hang issue when rendering vulkan/chained-ib are resolved. v2: drop gfx8 changes. gfx8 is not affected (Alex) Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
cdf6adb2 |
|
28-Apr-2017 |
Shaoyun Liu <Shaoyun.Liu@amd.com> |
drm/amdgpu: Move kiq ring lock out of virt structure The usage of kiq should not depend on the virtualization. Signed-off-by: Shaoyun Liu <Shaoyun.Liu@amd.com> Reviewed-by:Andres Rodriquez <andresx7@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
97fcc76b |
|
11-Apr-2017 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: drop support for untouched registers I couldn't figure out what this was original good for, but we don't use it any more. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
b4e40676 |
|
27-Mar-2017 |
David Panariti <David.Panariti@amd.com> |
drm/amdgpu: Switch baremetal to use KIQ for compute ring management. (v3) KIQ is the Kernel Interface Queue for managing the MEC. Rather than setting up rings via direct MMIO of ring registers, the rings are configured via special packets sent to the KIQ. The allows the MEC to better manage shared resources and certain power events. v2: squash in s3/s4 fix from Rex v3: further fixes from Rex Signed-off-by: David Panariti <David.Panariti@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Acked-by: Tom St Denis <tom.stdenis@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
248a1d6f |
|
23-Apr-2017 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
drm/amd: fix include notation and remove -Iinclude/drm flag Include <drm/*.h> instead of relative path from include/drm, then remove the -Iinclude/drm compiler flag. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Link: http://patchwork.freedesktop.org/patch/msgid/1493009447-31524-4-git-send-email-yamada.masahiro@socionext.com
|
#
30514dec |
|
08-May-2017 |
Chunming Zhou <David1.Zhou@amd.com> |
drm/amdgpu: fix dependency issue The problem is that executing the jobs in the right order doesn't give you the right result because consecutive jobs executed on the same engine are pipelined. In other words job B does it buffer read before job A has written it's result. Signed-off-by: Chunming Zhou <David1.Zhou@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
1bf6ad62 |
|
09-May-2017 |
Daniel Vetter <daniel.vetter@ffwll.ch> |
drm/vblank: drop the mode argument from drm_calc_vbltimestamp_from_scanoutpos If we restrict this helper to only kms drivers (which is the case) we can look up the correct mode easily ourselves. But it's a bit tricky: - All legacy drivers look at crtc->hwmode. But that is updated already at the beginning of the modeset helper, which means when we disable a pipe. Hence the final timestamps might be a bit off. But since this is an existing bug I'm not going to change it, but just try to be bug-for-bug compatible with the current code. This only applies to radeon&amdgpu. - i915 tries to get it perfect by updating crtc->hwmode when the pipe is off (i.e. vblank->enabled = false). - All other atomic drivers look at crtc->state->adjusted_mode. Those that look at state->requested_mode simply don't adjust their mode, so it's the same. That has two problems: Accessing crtc->state from interrupt handling code is unsafe, and it's updated before we shut down the pipe. For nonblocking modesets it's even worse. For atomic drivers try to implement what i915 does. To do that we add a new hwmode field to the vblank structure, and update it from drm_calc_timestamping_constants(). For atomic drivers that's called from the right spot by the helper library already, so all fine. But for safety let's enforce that. For legacy driver this function is only called at the end (oh the fun), which is broken, so again let's not bother and just stay bug-for-bug compatible. The benefit is that we can use drm_calc_vbltimestamp_from_scanoutpos directly to implement ->get_vblank_timestamp in every driver, deleting a lot of code. v2: Completely new approach, trying to mimick the i915 solution. v3: Fixup kerneldoc. v4: Drop the WARN_ON to check that the vblank is off, atomic helpers currently unconditionally call this. Recomputing the same stuff should be harmless. v5: Fix typos and move misplaced hunks to the right patches (Neil). v6: Undo hunk movement (kbuild). Cc: Mario Kleiner <mario.kleiner@tuebingen.mpg.de> Cc: Eric Anholt <eric@anholt.net> Cc: Rob Clark <robdclark@gmail.com> Cc: linux-arm-msm@vger.kernel.org Cc: freedreno@lists.freedesktop.org Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Christian König <christian.koenig@amd.com> Cc: Ben Skeggs <bskeggs@redhat.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Acked-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/20170509140329.24114-4-daniel.vetter@ffwll.ch
|
#
3fcdcb27 |
|
09-May-2017 |
Daniel Vetter <daniel.vetter@ffwll.ch> |
drm/vblank: Switch to bool in_vblank_irq in get_vblank_timestamp It's overkill to have a flag parameter which is essentially used just as a boolean. This takes care of core + adjusting drivers. Adjusting the scanout position callback is a bit harder, since radeon also supplies it's own driver-private flags in there. v2: Fixup misplaced hunks (Neil). v3: kbuild says v1 was better ... Cc: Mario Kleiner <mario.kleiner@tuebingen.mpg.de> Cc: Eric Anholt <eric@anholt.net> Cc: Rob Clark <robdclark@gmail.com> Cc: linux-arm-msm@vger.kernel.org Cc: freedreno@lists.freedesktop.org Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Christian König <christian.koenig@amd.com> Cc: Ben Skeggs <bskeggs@redhat.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Daniel Vetter <daniel.vetter@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/20170509140329.24114-2-daniel.vetter@ffwll.ch
|
#
d673c02c |
|
09-May-2017 |
Daniel Vetter <daniel.vetter@ffwll.ch> |
drm/vblank: Switch drm_driver->get_vblank_timestamp to return a bool There's really no reason for anything more: - Calling this while the crtc vblank stuff isn't set up is a driver bug. Those places alrready DRM_ERROR. - Calling this when the crtc is off is either a driver bug (calling drm_crtc_handle_vblank at the wrong time) or a core bug (for anything else). Again, we DRM_ERROR. - EINVAL is checked at higher levels already, and if we'd use struct drm_crtc * instead of (dev, pipe) it would be real obvious that those are again core bugs. The only valid failure mode is crap hardware that couldn't sample a useful timestamp, to ask the core to just grab a not-so-accurate timestamp. Bool is perfectly fine for that. v2: Also fix up the one caller, I lost that in the shuffling (Jani). v3: Fixup commit message (Neil). Cc: Jani Nikula <jani.nikula@linux.intel.com> Cc: Mario Kleiner <mario.kleiner@tuebingen.mpg.de> Cc: Eric Anholt <eric@anholt.net> Cc: Rob Clark <robdclark@gmail.com> Cc: linux-arm-msm@vger.kernel.org Cc: freedreno@lists.freedesktop.org Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Christian König <christian.koenig@amd.com> Cc: Ben Skeggs <bskeggs@redhat.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Acked-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/20170509140329.24114-1-daniel.vetter@ffwll.ch
|
#
af8baf15 |
|
04-May-2017 |
Guenter Roeck <linux@roeck-us.net> |
drm/amdgpu: Use less generic enum definitions alpha:allmodconfig fails to build as follows. drivers/gpu/drm/amd/amdgpu/amdgpu.h:1006:2: error: expected identifier before '(' token drivers/gpu/drm/amd/amdgpu/amdgpu.h:1011:28: error: 'NGG_BUF_MAX' undeclared here The problem is not really the enum definition of NGG_BUF_MAX but PARAM, which happens to be defined differently for alpha and a couple of other architectures. Use less generic defines for NGG enums to solve the problem. Fixes: bce23e00f3369 ("drm/amdgpu: add NGG parameters") Cc: Christian König <christian.koenig@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
f47b77b4 |
|
02-May-2017 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu/gfx: drop max_gs_waves_per_vgt We already have this info: max_gs_threads. Drop the duplicate. Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
408bfe7c |
|
26-Apr-2017 |
Junwei Zhang <Jerry.Zhang@amd.com> |
drm/amdgpu: export more gpu info for gfx9 v2: 64-bit aligned for gpu info v3: squash in wave_front_fix Signed-off-by: Ken Wang <Qingqing.Wang@amd.com> Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Qiang Yu <Qiang.Yu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
55ed8caf |
|
21-Apr-2017 |
Chunming Zhou <David1.Zhou@amd.com> |
drm/amdgpu: increase gtt size to 3GB by default v2 v2: address Alex's comment, add AMDGPU_DEFAULT_GTT_SIZE_MB. Signed-off-by: Chunming Zhou <David1.Zhou@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
b1bb8c01 |
|
07-Apr-2017 |
Tom St Denis <tom.stdenis@amd.com> |
drm/amd/amdgpu: Introduce new read/write macros for SOC15 Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
efe53d8a |
|
05-Apr-2017 |
Tom St Denis <tom.stdenis@amd.com> |
drm/amd/amdgpu: cleanup gfx_v9_0_init_queue() Introduce WREG32_FIELD15 macro for SOC15 architectures. Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
714f88e0 |
|
05-Apr-2017 |
Alex Xie <AlexBin.Xie@amd.com> |
drm/amdgpu: Move function amdgpu_has_atpx near other similar functions Signed-off-by: Alex Xie <AlexBin.Xie@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
03f89feb |
|
04-Apr-2017 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: cleanup get_invalidate_req v2 The two hubs are just instances of the same hardware, so the register bits are identical. v2: keep the function pointer Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
ccaf3574 |
|
04-Apr-2017 |
Tom St Denis <tom.stdenis@amd.com> |
drm/amd/amdgpu: Clean up gfx_v8_0_kiq_set_interrupt_state() Use new WREG32_FIELD_OFFSET() to clean up code. Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
11250164 |
|
30-Mar-2017 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: cleanup VMHUB bit definitions v2 The two hubs are just instances of the same hardware, so the register bits are identical. v2: only remove get_vm_protection_bits for now Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
f75e237c |
|
30-Mar-2017 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: move adjust_mc_addr into amdgpu_gart_funcs We should probably rename amdgpu_gart_funcs sooner or later. Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com> Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
eb60ef2b |
|
30-Mar-2017 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: move VM related defines into amdgpu_vm.h Try to clean up amdgpu.h. Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com> Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
5a9b8e8a |
|
30-Mar-2017 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: fix VMHUB order to match the hardware Match our defines with what the hw uses. Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com> Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
a9f87f64 |
|
30-Mar-2017 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: use a 64bit interval tree for VM management v2 This only makes a difference for 32-bit systems. The idea is to have a fixed virtual address space size with 4-level page tables and to minimize differences between 32 and 64-bit systems. v2: Update commit message. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
5846e355 |
|
23-Mar-2017 |
Monk Liu <Monk.Liu@amd.com> |
drm/amdgpu:fix ring_write_multiple ring_write_multiple should use buf_mask instead of ptr_mask Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
e6b3ecb4 |
|
30-Dec-2016 |
Monk Liu <Monk.Liu@amd.com> |
drm/amdgpu/vega10:fix DOORBELL64 scheme Signed-off-by: Monk Liu <Monk.Liu@amd.com> Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
0e5ca0d1 |
|
03-Mar-2017 |
Huang Rui <ray.huang@amd.com> |
drm/amdgpu: add PSP driver for vega10 (v2) PSP is responsible for firmware loading on SOC-15 asics. v2: fix memory leak (Ken) Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
b1023571 |
|
03-Mar-2017 |
Ken Wang <Qingqing.Wang@amd.com> |
drm/amdgpu: implement GFX 9.0 support (v2) Add support for gfx v9.0. v2: update golden settings from Ken Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Ken Wang <Qingqing.Wang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
e60f8db5 |
|
09-Mar-2017 |
Alex Xie <AlexBin.Xie@amd.com> |
drm/amdgpu: Add GMC 9.0 support (v2) On SOC-15 parts, the GMC (Graphics Memory Controller) consists of two hubs: GFX (graphics and compute) and MM (sdma, uvd, vce). v2: drop sdma from Makefile, fix duplicate return statement. Signed-off-by: Alex Xie <AlexBin.Xie@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
2445b227 |
|
03-Mar-2017 |
Huang Rui <ray.huang@amd.com> |
drm/amdgpu: rework common ucode handling for vega10 Handle ucode differences in vega10. Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
bce23e00 |
|
27-Mar-2017 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: add NGG parameters NGG (Next Generation Graphics) is a new feature in GFX9.0. This adds the relevant parameters. Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
39807b93 |
|
18-Mar-2016 |
Ken Wang <Qingqing.Wang@amd.com> |
drm/amdgpu: add 64bit doorbell assignments Signed-off-by: Ken Wang <Qingqing.Wang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
d0e95758 |
|
12-Dec-2016 |
Andrey Grodzovsky <Andrey.Grodzovsky@amd.com> |
drm/amdgpu: gb_addr_config struct Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com> Reviewed-by: Ken Wang <Qingqing.Wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
e635ee07 |
|
01-Nov-2016 |
Huang Rui <ray.huang@amd.com> |
drm/amdgpu: use new flag to handle different firmware loading method This patch introduces a new flag named "amdgpu_firmware_load_type" to handle different firmware loading method. Since Vega10, there are three ways to load firmware. It would be better to use a flag and a fw_load_type kernel parameter to configure it. Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
a5bde2f9 |
|
23-Sep-2016 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: add basic support for atomfirmware.h (v3) This adds basic support for asics that use atomfirmware.h to define their vbios tables. v2: rebase v3: squash in num scratch reg fix Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Ken Wang <Qingqing.Wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
0cdd5005 |
|
13-Feb-2017 |
Alex Deucher <alexander.deucher@amd.com> |
amdgpu: detect if we are using atomfirmware or atombios for vbios (v2) Supposedly atomfirmware rom header is 3.3 atombios is 1.1. v2: rebased on newer kernel Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
5e568178 |
|
10-Jan-2017 |
Leo Liu <leo.liu@amd.com> |
drm/amdgpu: move amdgpu_vce structure to vce header Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
4df654d2 |
|
02-Jan-2017 |
Leo Liu <leo.liu@amd.com> |
drm/amdgpu: move amdgpu_uvd structure to uvd header Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
bbf282d8 |
|
03-Mar-2017 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: add asic callback to get memsize register Newer asics use different registers so abstract it. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
5463545b |
|
13-Feb-2017 |
Alex Xie <AlexBin.Xie@amd.com> |
drm/amdgpu: add a callback to set vm mapping flags This lets each asic set whichever flags it supports. Signed-off-by: Alex Xie <AlexBin.Xie@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
4b98e0c4 |
|
13-Feb-2017 |
Alex Xie <AlexBin.Xie@amd.com> |
drm/amdgpu: set GART PTE asic specific flags Set asic specific gart pte flags in the gmc IP module for each asic. Signed-off-by: Alex Xie <AlexBin.Xie@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
6b777607 |
|
21-Sep-2016 |
Chunming Zhou <David1.Zhou@amd.com> |
drm/amdgpu: expand pte flags to uint64_t Necessary for new asics. Signed-off-by: Chunming Zhou <David1.Zhou@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
832be404 |
|
18-Mar-2016 |
Ken Wang <Qingqing.Wang@amd.com> |
drm/amdgpu: add 64bit doorbell functions (v2) Newer asics need 64 bit doorbells. v2: fix comment (Nils) Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Ken Wang <Qingqing.Wang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
7014285a |
|
18-Mar-2016 |
Ken Wang <Qingqing.Wang@amd.com> |
drm/amdgpu: add 64bit wb functions Newer asics need 64 bit writeback slots. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Ken Wang <Qingqing.Wang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
536fbf94 |
|
11-Mar-2016 |
Ken Wang <Qingqing.Wang@amd.com> |
drm/amdgpu: change wptr to 64 bits (v2) Newer asics need 64 bit wptrs. If the wptr is now smaller than the rptr that doesn't indicate a wrap-around anymore. v2: integrate Christian's comments. Signed-off-by: Ken Wang <Qingqing.Wang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
8fe73328 |
|
09-Mar-2016 |
Junwei Zhang <Jerry.Zhang@amd.com> |
drm/amdgpu: init aperture definitions (v2) v2: agd: move apertures to mc structure Signed-off-by: Flora Cui <Flora.Cui@amd.com> Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
04e30c9c |
|
08-Mar-2017 |
Daniel Vetter <daniel.vetter@ffwll.ch> |
drm/amdgpu: Merge pre/postclose hooks Again no apparent explanation for the split except hysterical raisins. Merging them also makes it a bit more obviuos what's going on wrt the runtime pm refdancing. Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Christian König <christian.koenig@amd.com> Cc: amd-gfx@lists.freedesktop.org Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Daniel Vetter <daniel.vetter@intel.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
81522f71 |
|
15-Nov-2016 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: remove unused sync testing Not used in a while. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Ken Wang <Qingqing.Wang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
ea323f88 |
|
20-Feb-2017 |
Junwei Zhang <Jerry.Zhang@amd.com> |
drm/amdgpu: rename amdgpu_gca_config to amdgpu_gfx_config Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
df6e2c4a |
|
16-Feb-2017 |
Junwei Zhang <Jerry.Zhang@amd.com> |
drm/amdgpu: export gfx config double offchip LDS buffers (v3) v2: move the config struct to drm_amdgpu_info_device v3: move the config feature to amdgpu_gca_config Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
59a82d7d |
|
17-Feb-2017 |
Xiangliang Yu <Xiangliang.Yu@amd.com> |
drm/amdgpu: change pointer of mqd_ptr & mqd_backup to void vi_mqd is only used by VI family but mqd_ptr and mqd_backup is common for all ASIC, so change the pointer to void. Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Monk Liu <Monk.Liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
9b49c3ab |
|
26-Jan-2017 |
Monk Liu <Monk.Liu@amd.com> |
drm/amdgpu:alloc mqd backup this is required for restoring the mqds after GPU reset. Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Xiangliang Yu <Xiangliang.Yu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
223049cd |
|
26-Jan-2017 |
Monk Liu <Monk.Liu@amd.com> |
drm/amdgpu:new field in_reset introduced for gfx use it to seperate driver load and gpu reset/resume because gfx IP need different approach for different hw_init trigger source Signed-off-by: Monk Liu <Monk.Liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
15d72fd7 |
|
25-Jan-2017 |
Monk Liu <Monk.Liu@amd.com> |
drm/amdgpu:impl RREG32 no kiq version some registers are PF & VF copy, and we can safely use mmio method to access them. and sometime we are forbid to use kiq to access registers for example in INTR context. we need a MACRO that always disable KIQ for regs accessing Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Xiangliang Yu <Xiangliang.Yu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
f7c35abe |
|
27-Jan-2017 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: implement PRT for GFX6 v2 Enable/disable the handling globally for now and print a warning when we enable it for the first time. v2: write to the correct register, adjust bits to that hw generation v3: fix compilation, add the missing register bit definitions Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
b85891bd |
|
15-Jan-2017 |
Junwei Zhang <Jerry.Zhang@amd.com> |
drm/amdgpu: IOCTL interface for PRT support v4 Till GFX8 we can only enable PRT support globally, but with the next hardware generation we can do this on a per page basis. Keep the interface consistent by adding PRT mappings and enable support globally on current hardware when the first mapping is made. v2: disable PRT support delayed and on all error paths v3: PRT and other permissions are mutal exclusive, PRT mappings don't need a BO. v4: update PRT mappings durign CS as well, make va_flags 64bit Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com> Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
284710fa |
|
30-Jan-2017 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: add basic PRT support (v2) Future hardware generations can handle PRT flags on a per page basis, but current hardware can only turn it on globally. Add the basic handling for both, a global callback to enable/disable triggered by setting a per mapping flag. v2: agd: rebase fixes Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
c836fec5 |
|
10-Feb-2017 |
Jim Qu <Jim.Qu@amd.com> |
drm/amd/amdgpu: post card if there is real hw resetting performed Check whether we need to post rather than whether the asic is posted. There are some cases (e.g., GPU reset or resume from hibernate) where we need to force post even if the asic has been posted. Signed-off-by: Jim Qu <Jim.Qu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
254cd2e0 |
|
08-Feb-2017 |
Rex Zhu <Rex.Zhu@amd.com> |
drm/amdgpu: read hw register to check pg status. Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
fad06127 |
|
09-Feb-2017 |
Samuel Pitoiset <samuel.pitoiset@gmail.com> |
drm/amdgpu: report the number of bytes moved at buffer creation Like ttm_bo_validate(), ttm_bo_init() might need to move BO and the number of bytes moved by TTM should be reported. This can help the throttle buffer migration mechanism to make a better decision. v2: fix computation Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
268c3001 |
|
18-Jan-2017 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: fix amdgpu_bo_va_mapping flags They are 64bit not 32 for a while now. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
50ddc75e |
|
23-Jan-2017 |
Junwei Zhang <Jerry.Zhang@amd.com> |
drm/amd/amdgpu: remove the uncessary parameter for ib scheduler Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
7e6bf80f |
|
16-Jan-2017 |
Monk Liu <Monk.Liu@amd.com> |
drm/amdgpu:introduce new flag to identify VM domain for cntx_ctrl To determine whether the context uses GPUVM or not. Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
0a8e1473 |
|
16-Jan-2017 |
Monk Liu <Monk.Liu@amd.com> |
drm/amdgpu:implement ring_write_multiple Write multiple dwords to the ring. Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
50261151 |
|
16-Jan-2017 |
Nils Wallménius <nils.wallmenius@gmail.com> |
drm/amdgpu: simplify allocation of scratch regs The scratch regs are sequential so there's no need to keep them in an array, we can just return the index of the first free register + the base register. Also change the array of bools for keeping track of the free regs to a bitfield. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Nils Wallménius <nils.wallmenius@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
b6091c12 |
|
09-Jan-2017 |
Xiangliang Yu <Xiangliang.Yu@amd.com> |
drm/amdgpu/ring: add two interfaces to support r/w registers with kiq During virtual runtime, need to send command to kiq ring to read/write GPU registers. Add two interface to support the two actions. Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com> Signed-off-by: Monk Linu <Monk.Liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
c79b5561 |
|
05-Jan-2017 |
Huang Rui <ray.huang@amd.com> |
drm/amdgpu: add get clockgating_state method for vce v3 Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
c8781f56 |
|
05-Jan-2017 |
Huang Rui <ray.huang@amd.com> |
drm/amdgpu: add get clockgating_state method for uvd v5&v6 Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
6cb2d4e4 |
|
05-Jan-2017 |
Huang Rui <ray.huang@amd.com> |
drm/amdgpu: introduce an interface to get clock gating status dynamically Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
c8394f38 |
|
08-Jan-2017 |
Xiangliang Yu <Xiangliang.Yu@amd.com> |
drm/amdgpu: remove detect_hw_virtualization interface Call detection function driectly, so remove the interface. V2: ci and si also need to call the detect function. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Monk Liu <monk.liu@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
5a5099cb |
|
09-Jan-2017 |
Xiangliang Yu <Xiangliang.Yu@amd.com> |
drm/amdgpu/virt: rename fieldes of virtualization structure Use acronym to rename fields to make easy to spell out. Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
4e638ae9 |
|
23-Dec-2016 |
Xiangliang Yu <Xiangliang.Yu@amd.com> |
drm/amdgpu/gfx8: add support kernel interface queue(KIQ) KIQ is queue-memory based initialization method: setup KIQ queue firstly, then send command to KIQ to setup other queues, without accessing registers. For virtualization, need KIQ to access virtual function registers when running on guest mode. V2: use amdgpu_bo_create/free_kernel to allocate BO. Signed-off-by: Monk Liu <Monk.Liu@amd.com> Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
b9bc5814 |
|
27-Dec-2016 |
Rex Zhu <Rex.Zhu@amd.com> |
drm/amdgpu: delete dead module parameter:amdgpu_powerplay. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
f7e9e9fe |
|
14-Dec-2016 |
Nils Wallménius <nils.wallmenius@gmail.com> |
drm/amdgpu: Remove checking for atombios This is a left over from radeon, amdgpu doesn't support any non-atombios parts and amdgpu_device_init would bail if the check for atombios failed anyway. Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net> Signed-off-by: Nils Wallménius <nils.wallmenius@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
30a17101 |
|
26-Jan-2017 |
Noralf Trønnes <noralf@tronnes.org> |
drm/amd/amdgpu: Remove drm_debugfs_remove_files() call drm_debugfs_cleanup() now removes all minor->debugfs_list entries automatically, so no need to call drm_debugfs_remove_files(). Also remove empty drm_driver.debugfs_cleanup callback. Cc: alexander.deucher@amd.com Cc: christian.koenig@amd.com Signed-off-by: Noralf Trønnes <noralf@tronnes.org> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Link: http://patchwork.freedesktop.org/patch/msgid/20170126225621.12314-5-noralf@tronnes.org
|
#
11b3c20b |
|
06-Jan-2017 |
Gabriel Krisman Bertazi <krisman@collabora.co.uk> |
drm: Change the return type of the unload hook to void The integer returned by the unload hook is ignored by the drm core, so let's make it void. This patch was created using the following Coccinelle semantic script (except for the declaration and comment in drm_drv.h): Compile-tested only. // <smpl> @ get_name @ struct drm_driver drv; identifier fn; @@ drv.unload = fn; @ replace_type @ identifier get_name.fn; @@ - int + void fn (...) { ... } @ remove_return_param @ identifier get_name.fn; @@ void fn (...) { <... if (...) return - ... ; ...> } @ drop_final_return @ identifier get_name.fn; @@ void fn (...) { ... - return 0; } // </smpl> Suggested-by: Daniel Vetter <daniel.vetter@intel.com> Signed-off-by: Gabriel Krisman Bertazi <krisman@collabora.co.uk> Acked-by: Christian König <christian.koenig@amd.com>. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Link: http://patchwork.freedesktop.org/patch/msgid/20170106175731.29196-1-krisman@collabora.co.uk
|
#
c5a60ce8 |
|
05-Dec-2016 |
Tom St Denis <tom.stdenis@amd.com> |
drm/amd/amdgpu: Add debugfs support for reading GPRs (v2) Implemented for SGPRs for GFX v8 initially. (v2) cleanup minor whitespace and remove sanity check and addressing is in dwords not bytes Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Acked-by: Edward O'Callaghan <funfunctor@folklore1984.net> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
a9f5db9c |
|
06-Dec-2016 |
Evan Quan <evan.quan@amd.com> |
drm/amd/amdgpu: stored bios_size It's necessary if we want to export vbios image out. Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net> Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian Koenig <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
faefba95 |
|
06-Dec-2016 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: just suspend the hw on pci shutdown We can't just reuse pci_remove as there may be userspace still doing things. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=98638 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97980 Reviewed-by: Christian König <christian.koenig@amd.com> Reported-and-tested-by: Mike Lothian <mike@fireburn.co.uk> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
70b5c5aa |
|
15-Nov-2016 |
Alex Deucher <alexander.deucher@amd.com> |
Revert "drm/amdgpu: use the kernel zone memory size as the max remote memory in amdgpu" This reverts commit a693e050edfe794fea81d7cfe72429a406aa380b. This breaks on systems with huge amounts of system memory as we do not have enough vram to store the page tables. Additionally, this is less of an issue with the recent gtt manager changes. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
e7b8243d |
|
22-Nov-2016 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: drop is_display_hung from display funcs Not used. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
3ca67300 |
|
01-Nov-2016 |
Rex Zhu <Rex.Zhu@amd.com> |
drm/amdgpu: delete duplicate module parameter. Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
8e94a46c |
|
08-Nov-2016 |
Mario Kleiner <mario.kleiner.de@gmail.com> |
drm/amdgpu: Attach exclusive fence to prime exported bo's. (v5) External clients which import our bo's wait only for exclusive dmabuf-fences, not on shared ones, ditto for bo's which we import from external providers and write to. Therefore attach exclusive fences on prime shared buffers if our exported buffer gets imported by an external client, or if we import a buffer from an external exporter. See discussion in thread: https://lists.freedesktop.org/archives/dri-devel/2016-October/122370.html Prime export tested on Intel iGPU + AMD Tonga dGPU as DRI3/Present Prime render offload, and with the Tonga standalone as primary gpu. v2: Add a wait for all shared fences before prime export, as suggested by Christian Koenig. v3: - Mark buffer prime_exported in amdgpu_gem_prime_pin, so we only use the exclusive fence when exporting a bo to external clients like a separate iGPU, but not when exporting/importing from/to ourselves as part of regular DRI3 fd passing. - Propagate failure of reservation_object_wait_rcu back to caller. v4: - Switch to a prime_shared_count counter instead of a flag, which gets in/decremented on prime_pin/unpin, so we can switch back to shared fences if all clients detach from our exported bo. - Also switch to exclusive fence for prime imported bo's. v5: - Drop lret, instead use int ret -> long ret, as proposed by Christian. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=95472 Tested-by: Mike Lothian <mike@fireburn.co.uk> (v1) Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com> Reviewed-by: Christian König <christian.koenig@amd.com>. Cc: Christian König <christian.koenig@amd.com> Cc: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
|
#
eef18a82 |
|
04-Nov-2016 |
Junwei Zhang <Jerry.Zhang@amd.com> |
drm/amdgpu: add the interface of waiting multiple fences (v4) v2: agd: rebase and squash in all the previous optimizations and changes so everything compiles. v3: squash in Slava's 32bit build fix v4: rebase on drm-next (fence -> dma_fence), squash in Monk's ioctl update patch Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com> Reviewed-by: Monk Liu <monk.liu@amd.com> Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Sumit Semwal <sumit.semwal@linaro.org> [sumits: fix checkpatch warnings] Link: http://patchwork.freedesktop.org/patch/msgid/1478290570-30982-2-git-send-email-alexander.deucher@amd.com
|
#
472259f0 |
|
14-Oct-2016 |
Tom St Denis <tom.stdenis@amd.com> |
drm/amd/amdgpu: re-factor debugfs wave reader Move IP version specific code into a callback. Also add support for gfx7 devices. Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
a1255107 |
|
13-Oct-2016 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: rework IP block registration (v2) This makes it easier to replace specific IP blocks on asics for handling virtual_dce, DAL, etc. and for building IP lists for hw or tables. This also stored the status information in the same structure. v2: split out spelling fix into a separate patch add a function to add IPs to the list Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
cf097881 |
|
07-Oct-2016 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: move dpm related definitions to amdgpu_dpm.h No intended functional change. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
e12f3d7a |
|
05-Oct-2016 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: move IB and frame size directly into the engine description I should have suggested that on the initial patchset. This saves us a few CPU cycles during CS and a bunch of loc. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
e3fa7630 |
|
10-Oct-2016 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: add additional cached gca config variables We need to cache some additional values to handle SR-IOV and PG. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
073440d2 |
|
28-Sep-2016 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: move VM defines into amdgpu_vm.h Only cleanup, no intended functional change. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
78023016 |
|
28-Sep-2016 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: move fence and ring defines into amdgpu_ring.h Only cleanup, no intended functional change. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
56113504 |
|
27-Sep-2016 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: move sync handling into a separate header Only cleanup, no intended functional change. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
914b4dce |
|
27-Sep-2016 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: stop using a bo list entry for the VM PTs Saves us a bit of memory. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
f7da30d9 |
|
27-Sep-2016 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: move PT validation back into VM code v2 Saves a bunch of CPU cycles when swapping things back in and allows us to split the VM headers into a separate file. v2: rename parameters Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
a7d64de6 |
|
15-Sep-2016 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: remove adev pointer from struct amdgpu_bo v2 It's completely pointless to have two pointers to the device in the same structure. v2: rename function to amdgpu_ttm_adev, fix typos Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
f8991bab |
|
16-Sep-2016 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: update the shadow PD together with the real one v2 Far less CPU cycles needed for this approach. v2: fix typo Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
6a7f76e7 |
|
24-Aug-2016 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: add VRAM manager v2 Split VRAM allocations into 4MB blocks. v2: fix typo in comment, some suggested cleanups v3: document how to disable the feature, fix rebase issue Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net> Tested-by: Mike Lothian <mike@fireburn.co.uk> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
f54d1867 |
|
25-Oct-2016 |
Chris Wilson <chris@chris-wilson.co.uk> |
dma-buf: Rename struct fence to dma_fence I plan to usurp the short name of struct fence for a core kernel struct, and so I need to rename the specialised fence/timeline for DMA operations to make room. A consensus was reached in https://lists.freedesktop.org/archives/dri-devel/2016-July/113083.html that making clear this fence applies to DMA operations was a good thing. Since then the patch has grown a bit as usage increases, so hopefully it remains a good thing! (v2...: rebase, rerun spatch) v3: Compile on msm, spotted a manual fixup that I broke. v4: Try again for msm, sorry Daniel coccinelle script: @@ @@ - struct fence + struct dma_fence @@ @@ - struct fence_ops + struct dma_fence_ops @@ @@ - struct fence_cb + struct dma_fence_cb @@ @@ - struct fence_array + struct dma_fence_array @@ @@ - enum fence_flag_bits + enum dma_fence_flag_bits @@ @@ ( - fence_init + dma_fence_init | - fence_release + dma_fence_release | - fence_free + dma_fence_free | - fence_get + dma_fence_get | - fence_get_rcu + dma_fence_get_rcu | - fence_put + dma_fence_put | - fence_signal + dma_fence_signal | - fence_signal_locked + dma_fence_signal_locked | - fence_default_wait + dma_fence_default_wait | - fence_add_callback + dma_fence_add_callback | - fence_remove_callback + dma_fence_remove_callback | - fence_enable_sw_signaling + dma_fence_enable_sw_signaling | - fence_is_signaled_locked + dma_fence_is_signaled_locked | - fence_is_signaled + dma_fence_is_signaled | - fence_is_later + dma_fence_is_later | - fence_later + dma_fence_later | - fence_wait_timeout + dma_fence_wait_timeout | - fence_wait_any_timeout + dma_fence_wait_any_timeout | - fence_wait + dma_fence_wait | - fence_context_alloc + dma_fence_context_alloc | - fence_array_create + dma_fence_array_create | - to_fence_array + to_dma_fence_array | - fence_is_array + dma_fence_is_array | - trace_fence_emit + trace_dma_fence_emit | - FENCE_TRACE + DMA_FENCE_TRACE | - FENCE_WARN + DMA_FENCE_WARN | - FENCE_ERR + DMA_FENCE_ERR ) ( ... ) Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Gustavo Padovan <gustavo.padovan@collabora.co.uk> Acked-by: Sumit Semwal <sumit.semwal@linaro.org> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Link: http://patchwork.freedesktop.org/patch/msgid/20161025120045.28839-1-chris@chris-wilson.co.uk
|
#
8a2eef1d |
|
02-Oct-2016 |
Grazvydas Ignotas <notasas@gmail.com> |
drm/amdgpu: also track late init state Successful sw_init() and hw_init() states are tracked, but not late_init(). Various error paths may result in amdgpu_fini() being called before .late init is done, so late_init needs to be tracked to avoid unexpected or multiple .late_fini() calls. Signed-off-by: Grazvydas Ignotas <notasas@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
765e7fbf |
|
15-Sep-2016 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: rename all rbo variable to abo v2 Just to cleanup some radeon leftovers. sed -i "s/rbo/abo/g" drivers/gpu/drm/amd/amdgpu/*.c sed -i "s/rbo/abo/g" drivers/gpu/drm/amd/amdgpu/*.h v2: rebased Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
1927ffc0 |
|
15-Sep-2016 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: remove unused member from struct amdgpu_bo Not used in a while. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
efc83cf4 |
|
14-Sep-2016 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu/atpx: check for ATIF dGPU wake for display events support Some ATPX laptops implement special circuitry to generate display hotplug events via ACPI when the dGPU is powered off. Check if this is supported. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
ceeb50ed |
|
18-Sep-2016 |
Monk Liu <Monk.Liu@amd.com> |
drm/amdgpu:cleanup virt related define move virtual machine related structure to amdgpu_virt.h easy for developer to maintain for virualization stuffs Signed-off-by: Monk Liu <Monk.Liu@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
3de4ec57 |
|
18-Sep-2016 |
Tom St Denis <tom.stdenis@amd.com> |
drm/amd/powerplay: Replace per-asic print_performance with generic Replace per-asic print_current_performance() functions with generic that calls read_sensor. Tested on Tonga and Carrizo for aesthetics and accuracy. Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
4e99a44e |
|
30-Mar-2016 |
Monk Liu <Monk.Liu@amd.com> |
drm/amdgpu:changes of virtualization cases probe (v3) 1,Changes on virtualization detections 2,Don't load smu & mc firmware if using sr-iov bios 3,skip vPost for sriov & force vPost if dev pass-through v2: agd: squash in Rays's fix for the missed SI case v3: agd: squash in additional fixes for CIK, SI, cleanup Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
9f31a0b0 |
|
15-Sep-2016 |
Baoyou Xie <baoyou.xie@linaro.org> |
drm/amdgpu: clean function declarations in amdgpu_ttm.c up We get 2 warnings when building kernel with W=1: drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c:985:5: warning: no previous prototype for 'amdgpu_ttm_init' [-Wmissing-prototypes] drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c:1092:6: warning: no previous prototype for 'amdgpu_ttm_fini' [-Wmissing-prototypes] In fact, both functions are declared in drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c, but should be declared in a header file, thus can be recognized in other file. So this patch moves the declarations into drivers/gpu/drm/amd/amdgpu/amdgpu.h. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Baoyou Xie <baoyou.xie@linaro.org> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
b6384ff5 |
|
16-Sep-2016 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu/ring: add an interface to get dma frame and ib size Used to properly calculate space on the ring for ib submissions. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
5141e9d2 |
|
06-Sep-2016 |
Rex Zhu <Rex.Zhu@amd.com> |
drm/amd/powerplay: add module parameter to mask pp features Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
c855e250 |
|
05-Sep-2016 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: bind GTT on demand We don't really need the GTT table any more most of the time. So bind it only on demand. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Acked-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
753ad49c |
|
25-Aug-2016 |
Monk Liu <Monk.Liu@amd.com> |
drm/amdgpu:implement CONTEXT_CONTROL (v5) v1: for gfx8, use CONTEXT_CONTROL package to dynamically skip preamble CEIB and other load_xxx command in sequence. v2: support GFX7 as well. remove cntxcntl in compute ring funcs because CPC doesn't support this packet. v3: fix reduntant judgement in cntxcntl. v4: some cleanups, don't change cs_submit() v5: keep old MESA supported & bump up KMS version. Signed-off-by: Monk Liu <Monk.Liu@amd.com> Ack-by: Chunming Zhou <David1.Zhou@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
3aecd24c |
|
25-Aug-2016 |
Monk Liu <Monk.Liu@amd.com> |
drm/amdgpu: change job->ctx field name job->ctx actually is a fence_context of the entity it belongs to, naming it as ctx is too vague, and we'll need add amdgpu_ctx into the job structure later. Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
662bfa61 |
|
31-Aug-2016 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: prevent command submission failures under memory pressure v2 As last resort try to evict BOs from the current working set into other memory domains. This effectively prevents command submission failures when VM page tables have been swapped out. v2: fix typos Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
2c0d7318 |
|
30-Aug-2016 |
Chunming Zhou <David1.Zhou@amd.com> |
drm/amdgpu: add gart recovery by gtt list V2 V2: a. gart recovery should be ahead of ring test. b. rename to amdgpu_ttm_recover_gart Signed-off-by: Chunming Zhou <David1.Zhou@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
5c1354bd |
|
30-Aug-2016 |
Chunming Zhou <David1.Zhou@amd.com> |
drm/amdgpu: link all gtt when binding them V2 V2: spin lock instead of mutex for gtt list Signed-off-by: Chunming Zhou <David1.Zhou@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
841686df |
|
31-Jul-2016 |
Maruthi Bayyavarapu <maruthi.bayyavarapu@amd.com> |
drm/amdgpu: add SI DPM support (v4) v2: corrected register offset shift v3: rebase fixes v4: fix firmware paths add SI smc firmware versions for sysfs dump remove unused function forward define fix the tahiti specific value of DEEP_SLEEP_CLK_SEL field fix to miss adding thermal controller use vram_type instead of checking mem_gddr5 flag fix incorrect index of CG_FFCT_0 register fix incorrect reading method at si_get_current_pcie_speed Signed-off-by: Maruthi Bayyavarapu <maruthi.bayyavarapu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
36b9a952 |
|
30-Aug-2016 |
Huang Rui <ray.huang@amd.com> |
drm/amdgpu: introduce pcie port read/write entry This patch adds pcie port read/write entry, because it will be also used on si dpm part. Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
30d1574f |
|
18-Jan-2016 |
Ken Wang <Qingqing.Wang@amd.com> |
drm/amdgpu: add DMA implementation for si v8 v4: rebase fixes v5: use the generic nop fill v6: rebase fixes v7: rebase fixes copy count fixes from Jonathan general cleanup add fill buffer implementation v8: adapt write_pte and copy_pte to latest changes Signed-off-by: Ken Wang <Qingqing.Wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
c2167a65 |
|
26-Aug-2016 |
Monk Liu <Monk.Liu@amd.com> |
drm/amdgpu:add switch buffer to end of CS (v2) sync switch buffer scheme with windows kmd for gfx v8, step1: append a switch_buffer to the end of CS v2:rebase on latest staging Signed-off-by: Monk Liu <Monk.Liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
95844d20 |
|
17-Aug-2016 |
Marek Olšák <marek.olsak@amd.com> |
drm/amdgpu: throttle buffer migrations at CS using a fixed MBps limit (v2) The old mechanism used a per-submission limit that didn't take previous submissions within the same time frame into account. It also filled VRAM slowly when VRAM usage dropped due to a big eviction or buffer deallocation. This new method establishes a configurable MBps limit that is obeyed when VRAM usage is very high. When VRAM usage is not very high, it gives the driver the freedom to fill it quickly. The result is more consistent performance. It can't keep the BO move rate low if lots of evictions are happening due to VRAM fragmentation, or if a big buffer is being migrated. The amdgpu.moverate parameter can be used to set a non-default limit. Measurements can be done to find out which amdgpu.moverate setting gives the best results. Mainly APUs and cards with small VRAM will benefit from this. For F1 2015, anything with 2 GB VRAM or less will benefit. Some benchmark results - F1 2015 (Tonga 2GB): Limit MinFPS AvgFPS Old code: 14 32.6 128 MB/s: 28 41 64 MB/s: 15.5 43 32 MB/s: 28.7 43.4 8 MB/s: 27.8 44.4 8 MB/s: 21.9 42.8 (different run) Random drops in Min FPS can still occur (due to fragmented VRAM?), but the average FPS is much better. 8 MB/s is probably a good limit for this game & the current VRAM management. The random FPS drops are still to be tackled. v2: use a spinlock Signed-off-by: Marek Olšák <marek.olsak@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
6f0359ff |
|
24-Aug-2016 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu/vce3: add support for third vce ring Not of much use at the moment (we don't really use the second ring either), but may be useful later. Reviewed-by: JimQu <Jim.Qu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
75c65480 |
|
24-Aug-2016 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: track the number of vce rings Rather than using a hardcoded value. This allows different versions to expose more or less rings. No functional change. Reviewed-by: JimQu <Jim.Qu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
810ddc3a |
|
23-Aug-2016 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: rename suspend_kms and resume_kms The old names were dragged over from radeon. The new ones better match the naming conventions used in the driver. No functional change. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
56615387 |
|
17-Aug-2016 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: fix lru size grouping v2 Adding a BO can make it the insertion point for larger sizes as well. v2: add a comment about the guard structure. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Felix Kuehling <felix.kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
|
#
99e124f4 |
|
16-Aug-2016 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: cleanup amdgpu_vm_bo_update params Make it more obvious what we are doing here. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
0c4e7fa5 |
|
16-Aug-2016 |
Chunming Zhou <David1.Zhou@amd.com> |
drm/amdgpu: link all shadow bo V2 V2: 1. use mutex instead of spinlock for shadow list, since its process could sleep. 2. move list_del to bo destroy phase. Signed-off-by: Chunming Zhou <David1.Zhou@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
6557e3d2 |
|
14-Aug-2016 |
Chunming Zhou <David1.Zhou@amd.com> |
drm/amdgpu: update pd shadow while updating pd V2 V2: Checking if shadow is valid. Signed-off-by: Chunming Zhou <David1.Zhou@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
20f4eff1 |
|
04-Aug-2016 |
Chunming Zhou <David1.Zhou@amd.com> |
drm/amdgpu: sync bo and shadow V3 Use shadow flag to judge which direction to sync. V2: Don't need bo pin, so remove it. V3: 1. Split to two functions, one is backup_to_shadow, another is restore_from_shadow. 2. Clean up previous shadow direction difinitions. Signed-off-by: Chunming Zhou <David1.Zhou@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
3ad81f16 |
|
05-Aug-2016 |
Chunming Zhou <David1.Zhou@amd.com> |
drm/amdgpu: add need backup function V2 V2: add checking if need backup in amdgpu_bo_create. Signed-off-by: Chunming Zhou <David1.Zhou@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
c632d799 |
|
01-Aug-2016 |
Flora Cui <Flora.Cui@amd.com> |
amdgpu: move ttm stuff to amdgpu_ttm.h Signed-off-by: Flora Cui <Flora.Cui@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
96105e53 |
|
11-Aug-2016 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: stop splitting PTE commands into smaller ones It doesn't make much sense to create bigger commands first which we then need to split into smaller one again. Just make sure the commands we create aren't to big in the first place. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
de9ea7bd |
|
12-Aug-2016 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: cleanup the write_pte implementations We don't need the gart mapping handling here any more. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
478feaf6 |
|
04-Aug-2016 |
Chunming Zhou <David1.Zhou@amd.com> |
drm/amdgpu: add shadow flag V2 Indicate if need to sync between bo and shadow, where sync to where. V2: Rename to backup_shadow Signed-off-by: Chunming Zhou <David1.Zhou@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
e7893c4b |
|
26-Jul-2016 |
Chunming Zhou <David1.Zhou@amd.com> |
drm/amdgpu: add shadow bo support V2 shadow bo is the shadow of a bo, which is always in GTT, which can be used to backup the original bo. V2: reference shadow parent, shadow bo will be freed by who allocted him. Signed-off-by: Chunming Zhou <David1.Zhou@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
cab0b8d5 |
|
12-Aug-2016 |
Felix Kuehling <Felix.Kuehling@amd.com> |
drm/amdgpu: Change GART offset to 64-bit The GART aperture size can be bigger than 4GB. Therefore the offset used in amdgpu_gart_bind and amdgpu_gart_unbind must be 64-bit. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
|
#
325cbba1 |
|
03-Aug-2016 |
Michel Dänzer <michel.daenzer@amd.com> |
drm/amdgpu: Provide page_flip_target hook Now we can program a flip during a vertical blank period, if it's the one targeted by the flip (or a later one). This allows simplifying amdgpu_flip_work_func considerably. agd: update dce_virtual.c as well. Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
1303c73c |
|
03-Aug-2016 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: cleanup VM fragment defines We can actually do way more than just the 64KB we currently used as default. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
3a8a6ab4 |
|
03-Aug-2016 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: remove unused VM defines Not used for a long time. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
61cb8cef |
|
09-Aug-2016 |
Tom St Denis <tom.stdenis@amd.com> |
drm/amd/amdgpu: Simplify bitfield operations in gfx v8 This patch introduces a new macro WREG32_FIELD which is used to write to a register with a new value in a field. It's designed to replace the pattern: tmp = RREG32(mmFoo); tmp &= ~REG__FIELD_MASK; tmp |= new_value << REG__FIELD__SHIFT; WREG32(mmFoo, tmp) with: WREG32_FIELD(Foo, FIELD, new_value); Unlike WREG32_P() it understands offsets/masks and doesn't require the caller to shift the value (or mask properly). It's applied where suitable in the gfx_v8_0.c driver to start with. Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
9accf2fd |
|
10-Aug-2016 |
Emily Deng <Emily.Deng@amd.com> |
drm/amdgpu: Change the virtual_display type from int to char*. For virtual display feature, as there may be multiple GPUs, for user could choose whiche GPU need to enable this feature, change the type of virtual_display from int to char*. The variable will be set like this virtual_display="xxxx:xx:xx.x;xxxx:xx:xx.x;". Signed-off-by: Emily Deng <Emily.Deng@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
e443059d |
|
07-Aug-2016 |
Emily Deng <Emily.Deng@amd.com> |
drm/amdgpu: Define one variable for virtual display. For virtual display feature, define on variable in amdgpu.ko. When want to enable virtual display feature, need set the option "amdgpu.virtual_display=1". And then disable vga render and crtc if have DCE engine. Signed-off-by: Emily Deng <Emily.Deng@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
a693e050 |
|
27-Jul-2016 |
Ken Wang <Qingqing.Wang@amd.com> |
drm/amdgpu: use the kernel zone memory size as the max remote memory in amdgpu Signed-off-by: Ken Wang <Qingqing.Wang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
59b4a977 |
|
19-Jul-2016 |
Flora Cui <Flora.Cui@amd.com> |
drm/amdgpu: implement amdgpu_fill_buffer() so that bo could be set to some pattern Signed-off-by: Flora Cui <Flora.Cui@amd.com> Reviewed-by: Chunming Zhou <David1.Zhou@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
66bc3f7f |
|
28-Jul-2016 |
Rex Zhu <Rex.Zhu@amd.com> |
drm/amdgpu: use modules parameter to ctrl deep sleep feature in dpm Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
115933a5 |
|
18-Jul-2016 |
Chunming Zhou <David1.Zhou@amd.com> |
drm/amdgpu: implement vce3 check/post_soft_reset Signed-off-by: Chunming Zhou <David1.Zhou@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
fc0b3b90 |
|
18-Jul-2016 |
Chunming Zhou <David1.Zhou@amd.com> |
drm/amdgpu: implement UVD6 check/pre/post_soft_reset Signed-off-by: Chunming Zhou <David1.Zhou@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
50b0197a |
|
18-Jul-2016 |
Chunming Zhou <David1.Zhou@amd.com> |
drm/amdgpu: implement gmc8 check/pre/post_soft_reset Signed-off-by: Chunming Zhou <David1.Zhou@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
e702a680 |
|
12-Jul-2016 |
Chunming Zhou <David1.Zhou@amd.com> |
drm/amdgpu: implement sdma3 check/pre/post_soft_reset Signed-off-by: Chunming Zhou <David1.Zhou@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
3d7c6384 |
|
14-Jul-2016 |
Chunming Zhou <David1.Zhou@amd.com> |
drm/amdgpu: implement gfx8 check_soft_reset Signed-off-by: Chunming Zhou <David1.Zhou@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
63fbf42f |
|
14-Jul-2016 |
Chunming Zhou <David1.Zhou@amd.com> |
drm/amdgpu: add check_soft_reset ip func It is used to identify if the ip block is hang. Signed-off-by: Chunming Zhou <David1.Zhou@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
4cb5877c |
|
25-Jul-2016 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: enable UVD context buffer for older HW Supported starting on certain FW versions. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
bbec97aa |
|
05-Jul-2016 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: add a fence timeout for the IB tests v2 10ms should be enough for now. v2: fix some typos in CIK code Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
ebff485e |
|
20-Jul-2016 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: use begin/end_use for VCE power/clock gating This fixes turning power and clock on when it is actually needed. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
f06505b8 |
|
20-Jul-2016 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: add begin/end_use ring callbacks For manual UVD/VCE power and clock gating. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
7c23ace2 |
|
19-Jul-2016 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: remove fence_lock Was never used as far as I can see. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
92c023c4 |
|
19-Jul-2016 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: fix indentation in struct amdgpu_ring Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
ccdbb20a |
|
07-Jun-2016 |
Rex Zhu <Rex.Zhu@amd.com> |
drm/amdgpu: add read/write function for GC CAC programming Create a GC_CAC_IND_INDEX/DATA pair of funcitons to program all the CAC registers Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
33b7ed01 |
|
05-Jul-2016 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: remove more of the ring backup code Not used anymore. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
40019dc4 |
|
29-Jun-2016 |
Chunming Zhou <David1.Zhou@amd.com> |
drm/amdgpu: clean up ring_backup code, no need more Signed-off-by: Chunming Zhou <David1.Zhou@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
fd53be30 |
|
01-Jul-2016 |
Chunming Zhou <David1.Zhou@amd.com> |
drm/amdgpu: add a bool to specify if needing vm flush V2 which avoids job->vm_pd_addr be changed. V2: pass job structure to amdgpu_vm_grab_id and amdgpu_vm_flush directly. Signed-off-by: Chunming Zhou <David1.Zhou@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
a5fb4ec2 |
|
29-Jun-2016 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: earlier free SA resources Keep the time we don't have a fence associated with the resource smaller. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
b5f5acbc |
|
29-Jun-2016 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: fix user fence handling once more Same problem as with the VM page tables. The user fence address must be determined before the job is scheduled, not when the IB is executed. This fixes a security problem where user fences could be used to overwrite any part of VRAM. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
9559ef5b |
|
28-Jun-2016 |
Tom St Denis <tom.stdenis@amd.com> |
drm/amd/gfx: add instance field to select_se_sh (v3) Add ability to specify instance in select_se_sh callback. Defaults to 0xffffffff all over the driver. (v2) Don't enable INSTANCE_BROADCAST by default (v3) Style changes Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
6adb0513 |
|
27-Jun-2016 |
Chunming Zhou <David1.Zhou@amd.com> |
drm/amdgpu: must update page table after gpu reset Record the gpu reset count in vmid to identify if gpu reset happened. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Chunming Zhou <David1.Zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
5dbbb60b |
|
23-Jun-2016 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: add IP helpers for wait_for_idle and is_idle Helpers to to call the IP functions for the selected IP. Reviewed-by: Chunming zhou <david1.zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
05fb7291 |
|
20-Jun-2016 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: move select_se_sh into the gfx struct It's gfx IP specific, not asic specific, so move to a gfx callback. Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
b95e31fd |
|
07-Jul-2016 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: move get_gpu_clock_counter into the gfx struct It's gfx IP specific, not asic specific, so move to a gfx callback. Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
4b7d97ac |
|
21-Jun-2016 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: drop wait_for_mc_idle asic callback Only used in the gmc IP modules so just call the local function directly. Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
5a712a87 |
|
21-Jun-2016 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: validate VM PTs only on eviction We don't need to validate them again if the eviction counter didn't changed. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
dbd5ed60 |
|
21-Jun-2016 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: add eviction counter Keep track of the number of evictions since boot. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
6f8941a2 |
|
17-Jun-2016 |
Nicolai Hähnle <nicolai.haehnle@amd.com> |
drm/amdgpu: add disable_cu parameter This parameter will allow disabling individual CUs on module load, e.g. amdgpu.disable_cu=2.0.3,2.0.4 to disable CUs 3 and 4 of SE2. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Nicolai Hähnle <nicolai.haehnle@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
50ab2533 |
|
12-Jun-2016 |
Huang Rui <ray.huang@amd.com> |
drm/amdgpu: introduce a firmware debugfs to dump all current firmware versions This patch implements the debugfs to dump all currect firmware version: root@jenkins-All-Series:/home/jenkins# cat /sys/kernel/debug/dri/0/amdgpu_firmware_info VCE feature version: 0, firmware version: 0x34040300 UVD feature version: 0, firmware version: 0x01451000 MC feature version: 0, firmware version: 0x00000000 ME feature version: 37, firmware version: 0x00000093 PFP feature version: 37, firmware version: 0x000000da CE feature version: 37, firmware version: 0x00000080 RLC feature version: 1, firmware version: 0x0000010e MEC feature version: 37, firmware version: 0x0000029e MEC2 feature version: 37, firmware version: 0x0000029e SMC feature version: 0, firmware version: 0x013353e6 SDMA0 feature version: 31, firmware version: 0x00000036 SDMA1 feature version: 0, firmware version: 0x00000036 Suggested-by: Alex Deucher <Alexander.Deucher@amd.com> Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
3dab83be |
|
01-Jun-2016 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: remove now unnecessary checks vm_flush() now comes directly after vm_grab_id(). Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Christian König <christian.koenig@amd.com> Acked-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
1fbb2e92 |
|
01-Jun-2016 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: use a fence array for VMID management Just wait for any fence to become available, instead of waiting for the last entry of the LRU. Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Christian König <christian.koenig@amd.com> Acked-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
35420238 |
|
23-May-2016 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: add optional ring to amdgpu_sync_is_idle Check if the sync object is idle depending on the ring a submission works with. Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Christian König <christian.koenig@amd.com> Acked-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
a7e7a93e |
|
20-May-2016 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: remove amdgpu_sync_wait Stop hiding bugs, instead print a proper error when the scheduler doesn't handle all dependencies. Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Christian König <christian.koenig@amd.com> Acked-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
395d1fb9 |
|
01-Jun-2016 |
Nicolai Hähnle <Nicolai.Haehnle@amd.com> |
drm/amdgpu: add amdgpu.cg_mask and amdgpu.pg_mask parameters They allow disabling clock and power gating from the kernel command line, which hopefully helps with diagnosing problems in the field. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Nicolai Hähnle <Nicolai.Haehnle@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
a909c6bd |
|
13-Jun-2016 |
Monk Liu <Monk.Liu@amd.com> |
drm/amdgpu: fix ring debugfs bug debugfs file added but not released after driver unloaded Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
2f5af82e |
|
02-Jun-2016 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu/atpx: track whether if this is a hybrid graphics platform hybrid graphics in this case refers to systems which use the new platform d3 cold ACPI methods as opposed to ATPX for dGPU power control. Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
a78fe133 |
|
01-Jun-2016 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu/atpx: add a query for ATPX dGPU power control The runtime pm sequence is different depending on whether or not the platform supports ATPX dGPU power control. Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
f2bdc05f |
|
24-May-2016 |
Eric Huang <JinHuiEric.Huang@amd.com> |
drm/amdgpu: add the common code to support mclk OD This implements mclk OverDrive(OD) through sysfs. The new entry pp_mclk_od is read/write. The value of input/output is an integer of the overclocking percentage. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
6bb6b297 |
|
23-May-2016 |
Huang Rui <ray.huang@amd.com> |
drm/amdgpu: add powercontainment module parameter This patch makes powercontainment feature configurable. Currently, the powercontainment is not very stable, so add a module parameter to enable/disable it via user mode. Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
c5f74f78 |
|
19-May-2016 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: fix and cleanup job destruction Remove the job reference counting and just properly destroy it from a work item which blocks on any potential running timeout handler. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Monk.Liu <monk.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
0e51a772 |
|
18-May-2016 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: properly abstract scheduler timeout handling The driver shouldn't mess with the scheduler internals. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Monk.Liu <monk.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
8b2e574d |
|
19-May-2016 |
Eric Huang <JinHuiEric.Huang@amd.com> |
drm/amdgpu: add the new common pm code to support sclk OD This extends OD (OverDrive) support to the non-Powerplay code paths. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
c85e299f |
|
19-May-2016 |
Eric Huang <JinHuiEric.Huang@amd.com> |
drm/amdgpu: add the new common pm code to select the clock levels This extends dpm clock level selection to the non-powerplay code paths. This interface can be used to select individual clock levels. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
428bafa8 |
|
12-May-2016 |
Eric Huang <JinHuiEric.Huang@amd.com> |
drm/amdgpu: add powerplay sclk OD support through sysfs (v2) Add a new sysfs entry pp_sclk_od to support sclk overdrive(OD) overclocking, the entry is read/write, the value of input/output is an integer which is the over percentage of the highest sclk. v2: drop extra semicolon Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
7c4021d4 |
|
13-Jun-2016 |
Alex Deucher <alexander.deucher@amd.com> |
Revert "drm/amdgpu: add pipeline sync while vmid switch in same ctx" This reverts commit 2ba272d7bde27e1db2cf1c6cee49b01b7ea08989. The issue fixed by this patch is specific to compute rings and the previous patch was enough. Additionally, this patch as been traced to strange behavior on some CZ systems so we might as well drop it.
|
#
048765ad |
|
11-Jun-2016 |
Andres Rodriguez <andres.rodriguez@amd.com> |
amdgpu: fix asic initialization for virtualized environments (v2) When executing in a PCI passthrough based virtuzliation environemnt, the hypervisor will usually attempt to send a PCIe bus reset signal to the ASIC when the VM reboots. In this scenario, the card is not correctly initialized, but we still consider it to be posted. Therefore, in a passthrough based environemnt we should always post the card to guarantee it is in a good state for driver initialization. However, if we are operating in SR-IOV mode it is up to the GIM driver to manage the asic state, therefore we should not post the card (and shouldn't be able to do it either). v2: add missing semi-colon Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Andres Rodriguez <andres.rodriguez@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
2ba272d7 |
|
27-Apr-2016 |
Chunming Zhou <David1.Zhou@amd.com> |
drm/amdgpu: add pipeline sync while vmid switch in same ctx Since vmid-mgr supports vmid sharing in one vm, the same ctx could get different vmids for two emits without vm flush, vm_flush could be done in another ring. Signed-off-by: Chunming Zhou <David1.Zhou@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
76bf0db5 |
|
01-Jun-2016 |
Christian König <christian.koenig@amd.com> |
dma-buf/fence: make fence context 64 bit v2 Fence contexts are created on the fly (for example) by the GPU scheduler used in the amdgpu driver as a result of an userspace request. Because of this userspace could in theory force a wrap around of the 32bit context number if it doesn't behave well. Avoid this by increasing the context number to 64bits. This way even when userspace manages to allocate a billion contexts per second it takes more than 500 years for the context number to wrap around. v2: fix printf formats as well. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Gustavo Padovan <gustavo.padovan@collabora.co.uk> Acked-by: Sumit Semwal <sumit.semwal@linaro.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Link: http://patchwork.freedesktop.org/patch/msgid/1464786612-5010-2-git-send-email-deathsimple@vodafone.de
|
#
d573de2d |
|
11-May-2016 |
Rex Zhu <Rex.Zhu@amd.com> |
drm/amdgpu: create fence slab once when amdgpu module init. This avoids problems with multiple GPUs. For example, if the first GPU failed before amdgpu_fence_init() was called, amdgpu_fence_slab_ref is still 0 and it will get decremented in amdgpu_fence_driver_fini(). This will lead to a crash during init of the second GPU since amdgpu_fence_slab_ref is not 0. v2: add functions for init/exit instead of moving the variables into the driver. Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
758ac17f |
|
06-May-2016 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: fix and cleanup user fence handling v2 We leaked the BO in the error pass, additional to that we only have one user fence for all IBs in a job. v2: remove white space changes Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
d88bf583 |
|
06-May-2016 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: move VM fields into job They are the same for all IBs. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
92f25098 |
|
06-May-2016 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: move the context from the IBs into the job We only have one context for all IBs. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
f153d286 |
|
06-May-2016 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: move context switch handling into common code v2 It was a source of bugs to repeat that in each IP version. v2: rename parameter Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
aa3b73f6 |
|
03-May-2016 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: use fence_context to judge ctx switch v2 Use of the ctx pointer is not safe, because they are likely already be assigned to another ctx when doing comparing. v2: recreate from scratch, avoid all unnecessary changes. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Monk.Liu <monk.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
cb9e59d7 |
|
05-May-2016 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: Support DRM_MODE_PAGE_FLIP_ASYNC (v2) When this flag is set, we program the hardware to execute the flip during horizontal blank (i.e. for the next scanline) instead of during vertical blank (i.e. for the next frame). Ported from radeon commit: drm/radeon: Support DRM_MODE_PAGE_FLIP_ASYNC v2: drop DAL change for upstream Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
7dae69a2 |
|
03-May-2016 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: fetch cu_info once at init Fetch this info once at init and just store the results for future requests. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
edf600da |
|
03-May-2016 |
Christian König <christian.koenig@amd.com> |
drm/amd: cleanup remaining spaces and tabs v2 This is the result of running the following commands: find drivers/gpu/drm/amd/ -name "*.h" -exec sed -i 's/[ \t]\+$//' {} \; find drivers/gpu/drm/amd/ -name "*.c" -exec sed -i 's/[ \t]\+$//' {} \; find drivers/gpu/drm/amd/ -name "*.h" -exec sed -i 's/ \+\t/\t/' {} \; find drivers/gpu/drm/amd/ -name "*.c" -exec sed -i 's/ \+\t/\t/' {} \; v2: drop changes to DAL and internal headers Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
b1c8a81f |
|
04-May-2016 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: remove define for reserved client ID Just set it to zero instead. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
0ea54b9b |
|
04-May-2016 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: make the VMID owner always 64bit Otherwise we could (in theory) run into problems on 32bit systems. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
4d9c514d |
|
03-May-2016 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: two minor 80 char fixes Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
c5637837 |
|
19-Apr-2016 |
Monk Liu <Monk.Liu@amd.com> |
drm/amdgpu: keep vm in job instead of ib (v2) ib.vm is a legacy way to get vm, after scheduler implemented vm should be get from job, and all ibs from one job share the same vm, no need to keep ib.vm just move vm field to job. this patch as well add job as paramter to ib_schedule so it can get vm from job->vm. v2: agd: sqaush in: drm/amdgpu: check if ring emit_vm_flush exists in vm flush No vm flush on engines that don't support VM. bug: https://bugs.freedesktop.org/show_bug.cgi?id=95195 Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
031e2983 |
|
24-Apr-2016 |
Chunming Zhou <David1.Zhou@amd.com> |
drm/amdgpu: add client id for every vm This adds a unique id for each vm client so we can properly track them. Signed-off-by: Chunming Zhou <David1.Zhou@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Monk Liu <monk.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
adcec288 |
|
15-Apr-2016 |
Tom St Denis <tom.stdenis@amd.com> |
drm/amd/amdgpu: Add debugfs entries for smc/didt/pcie This adds 3 new files that can be read/written to access indirect GPU registers. Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
2b6cd977 |
|
14-Apr-2016 |
Eric Huang <JinHuiEric.Huang@amd.com> |
drm/amd/amdgpu: add power gating initialization support for GFX8.0 Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
29b3259a |
|
15-Apr-2016 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: group BOs by log2 of the size on the LRU v2 This allows us to have small BOs on the LRU before big ones. v2: fix of by one and list corruption bug Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
68befebe |
|
13-Apr-2016 |
Chunming Zhou <David1.Zhou@amd.com> |
drm/amdgpu: only update last_flush when vmid doesn't have other new owner Signed-off-by: Chunming Zhou <David1.Zhou@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
79e5412c |
|
08-Apr-2016 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: add a new set of rlc function pointers Different asics tend to have different ways to interact with the RLC. This just covers enter/exit of safe mode for updating CG and PG state, but could be extended to cover other RLC operations in the future if necessary. Acked-by: Tom St Denis <tom.stdenis@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
110e6f26 |
|
11-Apr-2016 |
Dave Airlie <airlied@redhat.com> |
drm/amd: make a type-safe cgs_device struct. (v2) This is just a type-safety things to avoid everyone taking void *, it doesn't change anything. v2: agd5f: split out the dal changes into a separate patch. Signed-off-by: Dave Airlie <airlied@redhat.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
c0365541 |
|
12-Apr-2016 |
Arindam Nath <arindam.nath@amd.com> |
drm/amdgpu: handle more than 10 UVD sessions (v2) Change History -------------- v2: - Make firmware version check correctly. Firmware versions >= 1.80 should all support 40 UVD instances. - Replace AMDGPU_MAX_UVD_HANDLES with max_handles variable. v1: - The firmware can handle upto 40 UVD sessions. Signed-off-by: Arindam Nath <arindam.nath@amd.com> Signed-off-by: Ayyappa Chandolu <ayyappa.chandolu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
06ab6832 |
|
01-May-2016 |
Nils Wallménius <nils.wallmenius@gmail.com> |
drm/amdgpu: Mark all instances of struct drm_info_list as const All these are compile time constand and the drm_debugfs_create/remove_files functions take a const pointer argument. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Nils Wallménius <nils.wallmenius@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
62250a91 |
|
10-Apr-2016 |
Nils Wallménius <nils.wallmenius@gmail.com> |
drm/amd/scheduler: Mark amdgpu_sched_ops const This marks the struct amdgpu_sched_ops const and adjusts amd_sched_init to take a const pointer for the ops param. The ops member of struct amd_gpu_scheduler is also changed to const. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Nils Wallménius <nils.wallmenius@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
f498d9ed |
|
10-Apr-2016 |
Nils Wallménius <nils.wallmenius@gmail.com> |
drm/amd: Mark some tables as const This patch marks some compile-time constant tables 'const'. The tables marked in this patch are the low hanging fruit where little other changes were necesary to avoid casting away constness etc. Also mark some tables that are private to a file as static. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Nils Wallménius <nils.wallmenius@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
41d9eb2c |
|
01-Mar-2016 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: add a fence after the VM flush This way we can track when the flush is done. Signed-off-by: Christian König <christian.koenig@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
832a902f |
|
14-Feb-2016 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: use a sync object for VMID fences v2 v2: rebase & cleanup This way we can store more than one fence as user for each VMID. Signed-off-by: Christian König <christian.koenig@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> (v1) Reviewed-by: Chunming Zhou <david1.zhou@amd.com> (v1) Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
bcb1ba35 |
|
08-Mar-2016 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: merge VM manager and VM context ID structure No need to have two of them any more. Signed-off-by: Christian König <christian.koenig@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
a1d29476 |
|
30-Mar-2016 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: optionally enable GART debugfs file Keeping the pages array around can use a lot of system memory when you want a large GART. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
43251981 |
|
30-Mar-2016 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: remove GART page addr array Not needed any more. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
b6723c8d |
|
09-Mar-2016 |
Monk Liu <Monk.Liu@amd.com> |
drm/amdgpu: use ref to keep job alive this is to fix fatal page fault error that occured if: job is signaled/released after its timeout work is already put to the global queue (in this case the cancel_delayed_work will return false), which will lead to NX-protection error page fault during job_timeout_func. Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
0de2479c |
|
04-Mar-2016 |
Monk Liu <Monk.Liu@amd.com> |
drm/amdgpu: rework TDR in scheduler (v2) Add two callbacks to scheduler to maintain jobs, and invoked for job timeout calculations. Now TDR measures time gap from job is processed by hw. v2: fix typo Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
e472d258 |
|
03-Mar-2016 |
Monk Liu <Monk.Liu@amd.com> |
drm/amdgpu: delay job free to when it's finished (v2) for those jobs submitted through scheduler, do not free it immediately after scheduled, instead free it in global workqueue by its sched fence signaling callback function. v2: call uf's bo_undef after job_run() call job's sync free after job_run() no static inline __amdgpu_job_free() anymore, just use kfree(job) to replace it. Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
03ccf481 |
|
14-Jan-2016 |
Monk Liu <monk.liu@amd.com> |
drm/amdgpu: patch cond exec for SDMA More ground work for conditional execution on SDMA necessary for preemption. Signed-off-by: Monk Liu <monk.liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
128cff1a |
|
14-Jan-2016 |
Monk Liu <monk.liu@amd.com> |
drm/amdgpu: support cond exec This adds the groundwork for conditional execution on SDMA which is necessary for preemption. Signed-off-by: Monk Liu <monk.liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
379548f5 |
|
19-Mar-2016 |
Nils Wallménius <nils.wallmenius@gmail.com> |
drm/amdgpu: do not store bios_header_start in amdgpu_device It is only used locally in amdgpu_get_bios Signed-off-by: Nils Wallménius <nils.wallmenius@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
139768ff |
|
19-Mar-2016 |
Nils Wallménius <nils.wallmenius@gmail.com> |
drm/amdgpu: delete unused struct member suspend from amdgpu_device Signed-off-by: Nils Wallménius <nils.wallmenius@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
562e2689 |
|
18-Apr-2016 |
Sonny Jiang <sonny.jiang@amd.com> |
amdgpu/uvd: add uvd fw version for amdgpu Was previously always hardcoded to 0. Signed-off-by: Sonny Jiang <sonny.jiang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
|
#
e131b914 |
|
04-Apr-2016 |
Chunming Zhou <David1.Zhou@amd.com> |
drm/amdgpu: add invisible pin size statistic Signed-off-by: Chunming Zhou <David1.Zhou@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
3f99dd81 |
|
01-Apr-2016 |
Leo Liu <leo.liu@amd.com> |
drm/amdgpu: save and restore UVD context with suspend and resume and revert fix following it accordingly Revert "drm/amdgpu: stop trying to suspend UVD sessions v2" Revert "drm/amdgpu: fix the UVD suspend sequence order" Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
73cfa5f5 |
|
16-Mar-2016 |
Monk Liu <Monk.Liu@amd.com> |
drm/amdgpu: move ib.fence to job.fence Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
cc55c45d |
|
16-Mar-2016 |
Monk Liu <Monk.Liu@amd.com> |
drm/amdgpu: give a fence param to ib_free thus amdgpu_ib_free() can hook sched fence to SA manager in later patches. BTW: for amdgpu_free_job(), it should only fence_put() the fence of the last ib once, so fix it as well in this patch. Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
742c085f |
|
14-Mar-2016 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: switch back to 32bit hw fences v2 We don't need to extend them to 64bits any more, so avoid the extra overhead. v2: update commit message. Signed-off-by: Christian König <christian.koenig@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
|
#
4a7d74f1 |
|
14-Mar-2016 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: signal fences directly in amdgpu_fence_process Because of the scheduler we need to signal all fences immediately anyway, so try to avoid the waitqueue overhead. Signed-off-by: Christian König <christian.koenig@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
|
#
c89377d1 |
|
13-Mar-2016 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: keep all fences in an RCU protected array v2 Just keep all HW fences in a RCU protected array as a first step to replace the wait queue. v2: update commit message, move fixes into separate patch. Signed-off-by: Christian König <christian.koenig@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
|
#
e6151a08 |
|
15-Mar-2016 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: add number of hardware submissions to amdgpu_fence_driver_init_ring Make this a parameter instead of using the global variable directly. Signed-off-by: Christian König <christian.koenig@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
|
#
22e5a2f4 |
|
11-Mar-2016 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: move fence structure into amdgpu_fence.c No need to have that in the header file any more. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
77163f07 |
|
11-Mar-2016 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: remove amdgpu_fence_wait_next Not used any more. Signed-off-by: Christian König <christian.koenig@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
f104fbcb |
|
11-Mar-2016 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: remove amdgpu_ring_from_fence Not used any more. Signed-off-by: Christian König <christian.koenig@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
6ba60b89 |
|
11-Mar-2016 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: stop using the ring index in the SA The ring index will always collide as hash into the fence list, so use the context number instead. That can still cause collisions, but they are less likely than using ring indices. Signed-off-by: Christian König <christian.koenig@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
32b41ac2 |
|
08-Mar-2016 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: Revert "add mutex for ba_va->valids/invalids" Not needed any more because we need to protect the elements on the list anyway. This reverts commit 38bf516c75b4ef0f5c716e05fa9baab7c52d6c39. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
20250215 |
|
08-Mar-2016 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: Revert "add lock for interval tree in vm" Not needed any more because we need to protect the elements on the list anyway. This reverts commit fe237ed7efec8ac147a4572fdf81173a7f8ddda7. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
2f568dbd |
|
22-Feb-2016 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: move get_user_pages out of amdgpu_ttm_tt_pin_userptr v6 That avoids lock inversion between the BO reservation lock and the anon_vma lock. v2: * Changed amdgpu_bo_list_entry.user_pages to an array of pointers * Lock mmap_sem only for get_user_pages * Added invalidation of unbound userpointer BOs * Fixed memory leak and page reference leak v3 (chk): * Revert locking mmap_sem only for_get user_pages * Revert adding invalidation of unbound userpointer BOs * Sanitize and fix error handling v4 (chk): * Init userpages pointer everywhere. * Fix error handling when get_user_pages() fails. * Add invalidation of unbound userpointer BOs again. v5 (chk): * Add maximum number of tries. v6 (chk): * Fix error handling when we run out of tries. Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> (v4) Acked-by: Alex Deucher <alexander.deucher@amd.com>
|
#
b8c7b39e |
|
01-Mar-2016 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: split pipeline sync and vm flush This allows us to use the pipeline sync for other tasks as well. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
|
#
971fe9a9 |
|
01-Mar-2016 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: switch the GDS only on demand v2 Switching the GDS space to often seems to be problematic. This patch together with the following can avoid VM faults on context switch. v2: extend commit message a bit Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> (v1) Reviewed-by: Chunming Zhou <david1.zhou@amd.com> (v1)
|
#
cffadc83 |
|
01-Mar-2016 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: move the GDS switch into vm flush as well After all it's an operation on the VMID. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
|
#
364beb2c |
|
16-Feb-2016 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: return the common fence from amdgpu_fence_emit Try to avoid using the hardware specific fences even more. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
|
#
257bf15a |
|
16-Feb-2016 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: add slap cache for sync objects as well We need them all the time. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
|
#
336d1f5e |
|
16-Feb-2016 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: remove HW fence owner Not used any more since we now always use the sheduler. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
|
#
211dff55 |
|
22-Feb-2016 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: group userptr in the BO list v2 We need them together with the next patch. v2: Don't take bo reference twice Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
11afbde8 |
|
02-Mar-2016 |
Chunming Zhou <David1.Zhou@amd.com> |
drm/amdgpu: add hdp_invalidate function It's called after emitting ibs. Signed-off-by: Chunming Zhou <David1.Zhou@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
0bf5df3b |
|
04-Mar-2016 |
Nils Wallménius <nils.wallmenius@gmail.com> |
drm/amdgpu: delete set-but-not-read member has_uvd from amdgpu_device Clean up leftover from radeon code. Signed-off-by: Nils Wallménius <nils.wallmenius@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
4ff37a83 |
|
26-Feb-2016 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: fix VM faults caused by vm_grab_id() v4 The owner must be per ring as long as we don't support sharing VMIDs per process. Also move the assigned VMID and page directory address into the IB structure. v3: assign the VMID to all IBs, not just the first one. v4: use correct pointer for owner Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
418aa0c2 |
|
15-Feb-2016 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: cleanup gem init/finit Remove the double housekeeping and use something sane to forcefuly delete BOs on unload. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
|
#
7ea23565 |
|
15-Feb-2016 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: rework GEM info printing Print BOs grouped per client. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
|
#
c3874b75 |
|
11-Feb-2016 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: stop blocking for page filp fences Just register an callback and reschedule the work item if necessary. Signed-off-by: Christian König <christian.koenig@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com>
|
#
8f8e00c1 |
|
11-Feb-2016 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu/gfx: clean up harvest configuration (v2) Read back harvest configuration from registers and simplify calculations. No need to program the raster config registers. These are programmed as golden registers and the user mode drivers program them as well. v2: rebase on Tom's patches Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
20874179 |
|
11-Feb-2016 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: nuke the kernel context Not used any more. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
|
#
c594989c |
|
10-Feb-2016 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: use separate scheduler entity for VCE submissions This allows us to remove the kernel context and use a better priority for the submissions. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
|
#
ead833ec |
|
10-Feb-2016 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: use separate scheduler entity for UVD submissions This allows us to remove the kernel context and use a better priority for the submissions. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
|
#
703297c1 |
|
10-Feb-2016 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: use separate scheduler entitiy for buffer moves This allows us to remove the global kernel context. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
|
#
2d55e45a |
|
08-Feb-2016 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: use SDMA round robin for VM updates v3 Distribute the load on both rings. v2: use a loop for the initialization v3: agd: rebase on upstream Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
|
#
3ee94136 |
|
08-Feb-2016 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: remove is_pte_ring Not used for anything. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
|
#
2bd9ccfa |
|
31-Jan-2016 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: use per VM entity for page table updates (v2) Updates from different VMs can be processed independently. v2: agd: rebase on upstream Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
|
#
e86f9cee |
|
07-Feb-2016 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: move sync into job object No need to keep that for every IB. Signed-off-by: Christian König <christian.koenig@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
d71518b5 |
|
31-Jan-2016 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: cleanup in kernel job submission Add a job_alloc_with_ib helper and proper job submission. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
ec72b800 |
|
01-Feb-2016 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: directly return fence from ib_schedule Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
b07c60c0 |
|
30-Jan-2016 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: move ring from IBs into job We can't submit to multiple rings at the same time anyway. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
9e5d5309 |
|
30-Jan-2016 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: make pad_ib a ring function v3 The padding depends on the firmware version and we need that for BO moves as well, not only for VM updates. v2: new approach of making pad_ib a ring function v3: fix typo in macro name Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
4c0b242c |
|
01-Feb-2016 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: cleanup user fence handling in the CS Don't keep that around twice. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
50838c8c |
|
03-Feb-2016 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: add proper job alloc/free functions And use them in the CS instead of allocating IBs and jobs separately. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
867d0517 |
|
03-Feb-2016 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: remove AMDGPU_NUM_SYNCS Just a leftover from semaphores. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
8a8f0b48 |
|
03-Feb-2016 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: remove adev and fence from amdgpu_sync_free Just leftovers from the semaphores. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
cc325d19 |
|
08-Feb-2016 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: check userptrs mm earlier Instead of when we try to bind it check the usermm when we try to use it in the IOCTLs. Signed-off-by: Christian König <christian.koenig@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com>
|
#
7270f839 |
|
31-Jan-2016 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: add amdgpu_set_ib_value helper (v2) And use it in UVD/VCE command patching. v2: squash in Christian's fix Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
7e471e6f |
|
01-Feb-2016 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: track whether the asic supports SR-IOV Required to make desicions about certain code pathes. Reviewed-by: Monk Liu <monk.liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
383b6f60 |
|
01-Feb-2016 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: remove unused function amdgpu_boot_test_post_card() is not used anywhere. Probably a leftover from the original port from radeon. Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom St Denis <tom.stdenis@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
a8fe58ce |
|
22-Sep-2015 |
Maruthi Bayyavarapu <maruthi.bayyavarapu@amd.com> |
drm/amd: add ACP driver support This adds the ACP (Audio CoProcessor) IP driver and wires it up to the amdgpu driver. The ACP block provides the DMA engine for i2s based ALSA driver. This is required for audio on APUs that utilize an i2s codec. Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com> Reviewed-by: Maruthi Bayyavarapu <maruthi.bayyavarapu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Murali Krishna Vemuri <murali-krishna.vemuri@amd.com> Signed-off-by: Maruthi Bayyavarapu <maruthi.bayyavarapu@amd.com> Signed-off-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
b07c9d2a |
|
30-Nov-2015 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: move more logic into amdgpu_vm_map_gart v3 No need to duplicate that code over and over again. Also stop using the flags to determine if we need to map the addresses. v2: constify the pages_addr v3: rebased, fix typo in commit message Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
f3898ea1 |
|
11-Dec-2015 |
Eric Huang <JinHuiEric.Huang@amd.com> |
drm/amd/powerplay: add some sysfs interfaces for powerplay. The new sysfs interfaces: pp_num_states: Read-only, return the number of all pp states, 0 if powerplay is not available. pp_cur_state: Read-only, return the index number of current pp state. pp_force_state: Read-write, to write a power state index will switch to selected state forcedly and enable forced state mode, disable forced state mode. such as "echo >...". pp_table: Read-write, binary output, to be used to read or write the dpm table, the maximum file size is 4KB of page size. pp_dpm_sclk: Read-write, reading will return a dpm levels list, to write an index number will force powerplay to set the corresponding dpm level. pp_dpm_mclk: same as sclk. pp_dpm_pcie: same as sclk. And add new setting "manual" to the existing interface power_dpm_force_performance_level. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
c7e6be23 |
|
21-Jan-2016 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: remove rptr checking With the scheduler enabled we don't need that any more. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
a27de35c |
|
21-Jan-2016 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: remove the ring lock v2 It's not needed any more because all access goes through the scheduler now. v2: Update commit message. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
a9a78b32 |
|
21-Jan-2016 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: use a global LRU list for VMIDs With the scheduler enabled managing per ring LRUs don't make much sense any more. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
94dd0a4a |
|
18-Jan-2016 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: merge vm_grab_id and vm_fence v2 No need for an extra function any more. v2: comment cleanups Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
8d0a7cea |
|
03-Nov-2015 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: grab VMID before submitting job v5 This allows the scheduler to handle the dependencies on ID contention as well. v2: grab id only once v3: use a separate lock for the VMIDs v4: cleanup after semaphore removal v5: minor coding style change Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
1c343fc9 |
|
15-Jan-2016 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: drop hard_reset module parameter It doesn't currently do anything and there's no need for it going forward since pci config reset will be required as a fallback even when we have fine grained reset implemented. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
5907a0d8 |
|
18-Jan-2016 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: cleanup sync_seq handling Not used any more without semaphores Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
046c12c6 |
|
18-Jan-2016 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: remove sync_to from sync obj v2 Not needed any more without semaphores. v2: remove unused variables as well Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com>
|
#
ea5e4c87 |
|
15-Jan-2016 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: remove some more semaphore leftovers No longer needed since semaphores were removed. Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chunming Zhou <David1.Zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
cadf97b1 |
|
14-Jan-2016 |
Chunming Zhou <David1.Zhou@amd.com> |
drm/amdgpu: clean up non-scheduler code path (v2) Non-scheduler code is longer supported. v2: agd: rebased on upstream Signed-off-by: Chunming Zhou <David1.Zhou@amd.com> Reviewed-by: Ken Wang <Qingqing.Wang@amd.com> Reviewed-by: Monk Liu <monk.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
be86c606 |
|
14-Jan-2016 |
Chunming Zhou <David1.Zhou@amd.com> |
drm/amdgpu: cleanup amdgpu_sync_rings V2 No longer needed now that semaphores are gone. V2: remove the first amdgpu_sync_wait in amdgpu_ib_schedule Signed-off-by: Chunming Zhou <David1.Zhou@amd.com> Reviewed-by: Ken Wang <Qingqing.Wang@amd.com> (V1) Reviewed-by: Monk Liu <monk.liu@amd.com> (V2) Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
2f4b9400 |
|
14-Jan-2016 |
Chunming Zhou <David1.Zhou@amd.com> |
drm/amdgpu: clean up hw semaphore support in driver No longer used. Signed-off-by: Chunming Zhou <David1.Zhou@amd.com> Reviewed-by: Ken Wang <Qingqing.Wang@amd.com> Reviewed-by: Monk Liu <monk.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
1ea863fd |
|
18-Dec-2015 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: keep the prefered/allowed domains in the BO Stop copying that to the bo list entry, it doesn't change anyway. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
636ce25c |
|
18-Dec-2015 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: cleanup bo list bucket handling Move that into the BO list. No functional change. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
c3cca41e |
|
15-Dec-2015 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: cleanup amdgpu_cs_parser structure Remove unused user_ptr field, group fields by usage. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
25cfc3c2 |
|
19-Dec-2015 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: group VM mapping tree with its lock (v2) And also update the comment. v2: agd: rebase on usptream. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
f69f90a1 |
|
21-Dec-2015 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: fix amdgpu_cs_get_threshold_for_moves handling The threshold should only be computed once. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
d7006964 |
|
08-Feb-2016 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: fix issue with overlapping userptrs Otherwise we could try to evict overlapping userptr BOs in get_user_pages(), leading to a possible circular locking dependency. Signed-off-by: Christian König <christian.koenig@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com>
|
#
cc1de6e8 |
|
08-Feb-2016 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: fix issue with overlapping userptrs Otherwise we could try to evict overlapping userptr BOs in get_user_pages(), leading to a possible circular locking dependency. Signed-off-by: Christian König <christian.koenig@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
|
#
b19763d0 |
|
05-Feb-2016 |
Nicolai Hähnle <nicolai.haehnle@amd.com> |
drm/amdgpu: remove unnecessary forward declaration Signed-off-by: Nicolai Hähnle <nicolai.haehnle@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Cc: stable@vger.kernel.org
|
#
e3b04bc7 |
|
05-Feb-2016 |
Alex Deucher <alexander.deucher@amd.com> |
drma/dmgpu: move cg and pg flags into shared headers So they can be used by powerplay. Reviewed-by: Eric Huang <JinHuiEric.Huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
b118af70 |
|
05-Feb-2016 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: remove unused cg defines Leftover from radeon. Reviewed-by: Eric Huang <JinHuiEric.Huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
cd474ba0 |
|
04-Feb-2016 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: add pcie cap module parameters (v2) Allows the user to force the supported pcie gen and lane config on both the asic and the chipset. Useful for debugging pcie problems and for virtualization where we may not be able to query the pcie bridge caps. Default to: gen: chipset 1/2, asic 1/2/3 lanes: 1/2/4/8/16 v2: fix bare metal case Reviewed-by: monk liu <monk.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
4b5ece24 |
|
19-Jan-2016 |
Eric Huang <JinHuiEric.Huang@amd.com> |
drm/amd/amdgpu: Improve amdgpu_dpm* macros to avoid unexpected result (v2) The two macros returns are values which probably are used in the expression of calculation. Without the brackets the result of the expression may be wrong. v2: agd: squash both patches together Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com>
|
#
eceb8a15 |
|
11-Jan-2016 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: move VM page tables to the LRU end on CS v2 This makes it less likely to run into an ENOMEM because VM page tables are evicted last. v2: move the BOs in the LRU tail after validation Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
7fb72a1f |
|
18-Nov-2015 |
Rex Zhu <Rex.Zhu@amd.com> |
drm/amd/powerplay: export interface to DAL to init/change display configuration. Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: David Rokhvarg <David.Rokhvarg@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
|
#
d0dd7f0c |
|
11-Nov-2015 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: store pcie gen mask and link width We'll need this later for pcie dpm. Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
e61710c5 |
|
10-Nov-2015 |
Jammy Zhou <Jammy.Zhou@amd.com> |
drm/amdgpu: support per device powerplay enablement (v2) The amdgu_powerplay variable is global for multiple GPU instances. v2: fold in Flora's module option change, protect adev reference in macros Signed-off-by: Jammy Zhou <Jammy.Zhou@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com>
|
#
3af76f23 |
|
15-Oct-2015 |
Rex Zhu <Rex.Zhu@amd.com> |
drm/amdgpu: export fan control functions to amdgpu Hook up the amdgpu thermal control callbacks for powerplay. Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
|
#
1b5708ff |
|
10-Nov-2015 |
Rex Zhu <Rex.Zhu@amd.com> |
drm/amdgpu: export amd_powerplay_func to amdgpu and other ip block Update amdgpu to deal with the new powerplay module properly. v2: squash in fixes v3: squash in Rex's power state reporting fix Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Acked-by: Jammy Zhou <Jammy.Zhou@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
|
#
1f7371b2 |
|
02-Dec-2015 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amd/powerplay: add basic powerplay framework amdgpu_pp_ip_funcs is introduced to handle the two code paths, the legacy one and the new powerplay implementation. CONFIG_DRM_AMD_POWERPLAY kernel configuration option is introduced for the powerplay component. v4: squash in fixes v3: register debugfs file when powerplay module enable v2: add amdgpu_ucode_init_bo in hw init when amdgpu_powerplay enable. Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Jammy Zhou <Jammy.Zhou@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
|
#
3a2c788d |
|
25-Aug-2015 |
Rex Zhu <Rex.Zhu@amd.com> |
drm/amdgpu: share struct amdgpu_pm_state_type with powerplay module rename amdgpu_pm_state_type to amd_pm_state_type Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Acked-by: Jammy Zhou <Jammy.Zhou@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
|
#
ee1782c3 |
|
11-Dec-2015 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: keep the PTs validation list in the VM v2 This avoids allocating it on the fly. v2: fix grammar in comment Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
|
#
56467ebf |
|
11-Dec-2015 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: split VM PD and PT handling during CS This way we avoid the extra allocation for the page directory entry. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
|
#
3c0eea6c |
|
11-Dec-2015 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: put VM page tables directly into duplicates list They share the reservation object with the page directory anyway. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
|
#
91acbeb6 |
|
14-Dec-2015 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: fix user fence handling This fixes a random corruption under memory pressure. We need to fence the BO for the user fence as well, otherwise it might be swapped out and the GPU could write the fence value to an undesired location. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
|
#
37cd0ca2 |
|
10-Dec-2015 |
Chunming Zhou <David1.Zhou@amd.com> |
drm/amdgpu: unify AMDGPU_CTX_MAX_CS_PENDING and amdgpu_sched_jobs Signed-off-by: Chunming Zhou <David1.Zhou@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
81d75a30 |
|
04-Dec-2015 |
jimqu <Jim.Qu@amd.com> |
drm/amdgpu: add spin lock to protect freed list in vm (v2) there is a protection fault about freed list when OCL test. add a spin lock to protect it. v2: drop changes in vm_fini Signed-off-by: JimQu <jim.qu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com>
|
#
9c4153b1 |
|
04-Dec-2015 |
jimqu <Jim.Qu@amd.com> |
drm/amdgpu: add spin lock to protect freed list in vm (v2) there is a protection fault about freed list when OCL test. add a spin lock to protect it. v2: drop changes in vm_fini Signed-off-by: JimQu <jim.qu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com>
|
#
d033a6de |
|
05-Nov-2015 |
Chunming Zhou <David1.Zhou@amd.com> |
drm/amd: abstract kernel rq and normal rq to priority of run queue Allows us to set priorities in the scheduler. Signed-off-by: Chunming Zhou <David1.Zhou@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
|
#
7946b878 |
|
24-Nov-2015 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: add a callback for reading the bios from the rom directly This is necessary when the vbios image is not directly accessible via the rom BAR or legacy vga location. Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Monk Liu <monk.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
82b9c55b |
|
27-Nov-2015 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: fix VM page table reference counting We use the reservation object of the page directory for the page tables as well, because of this the page directory should be freed last. Ensure that by keeping a reference from the page tables to the directory. Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
e98c1b0d |
|
13-Nov-2015 |
Chunming Zhou <David1.Zhou@amd.com> |
drm/amdgpu: remove vm->mutex Signed-off-by: Chunming Zhou <David1.Zhou@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com>
|
#
69b576a1 |
|
17-Nov-2015 |
Chunming Zhou <David1.Zhou@amd.com> |
drm/amdgpu: add mutex for ba_va->valids/invalids Signed-off-by: Chunming Zhou <David1.Zhou@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com>
|
#
c25867df |
|
12-Nov-2015 |
Chunming Zhou <David1.Zhou@amd.com> |
drm/amdgpu: add lock for interval tree in vm Change-Id: I62b892a22af37b32e6b4aefca80a25cf45426ed2 Signed-off-by: Chunming Zhou <David1.Zhou@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com>
|
#
1c16c0a7 |
|
14-Nov-2015 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: keep the owner for VMIDs We don't need the last VM use any more, keep the owner directly. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chunming Zhou <davdi1.zhou@amd.com>
|
#
ea89f8c9 |
|
15-Nov-2015 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: move VM manager clean into the VM code again It's not a good idea to duplicate that code. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chunming Zhou <davdi1.zhou@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
|
#
8b4fb00b |
|
15-Nov-2015 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: cleanup VM coding style Fix the indentation and move the VM functions to the structures. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chunming Zhou <davdi1.zhou@amd.com> Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
|
#
eeed25ab |
|
15-Nov-2015 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: remove unused VM manager field Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chunming Zhou <davdi1.zhou@amd.com> Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
|
#
984810fc |
|
14-Nov-2015 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: cleanup scheduler command submission Unify the two code path again, cause they do pretty much the same thing. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chunming Zhou <davdi1.zhou@amd.com> Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
|
#
e2840221 |
|
05-Nov-2015 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: fix incorrect mutex usage v3 Before this patch the scheduler fence was created when we push the job into the queue, so we could only get the fence after pushing it. The mutex now was necessary to prevent the thread pushing the jobs to the hardware from running faster than the thread pushing the jobs into the queue. Otherwise the thread pushing jobs into the queue would have accessed possible freed up memory when it tries to get a reference to the fence. So what you get in the end is thread A: mutex_lock(&job->lock); ... Kick of thread B. ... mutex_unlock(&job->lock); And thread B: mutex_lock(&job->lock); .... mutex_unlock(&job->lock); kfree(job); I'm actually not sure if I'm still up to date on this, but this usage pattern used to be not allowed with mutexes. See here as well https://lwn.net/Articles/575460/. v2: remove unrelated changes, fix missing owner v3: rebased, add more commit message Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
|
#
7e52a81c |
|
04-Nov-2015 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: cleanup amdgpu_cs_parser handling No need any more to allocate that structure dynamically, just put it on the stack. This is a start to cleanup some of the scheduler fallouts. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
|
#
16ae42fe |
|
03-Nov-2015 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: use common fence for amdgpu_vm_fence Just cleanup the function parameters. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
|
#
c2776afe |
|
03-Nov-2015 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: use a timer for fence fallback Less overhead than a work item and also adds proper cleanup handling. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com>
|
#
7a91d6cb |
|
27-Oct-2015 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: remove AMDGPU_FENCE_OWNER_MOVE Moves are exclusive operations anyway, just use the undefined owner for those. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
|
#
a67bcd34 |
|
26-Oct-2015 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: remove now unused fence functions Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
|
#
1d1106b0 |
|
15-Jul-2015 |
Harry Wentland <harry.wentland@amd.com> |
drm/amdgpu: Make amdgpu_mn functions inline Unused amdgpu_mn functions threw warnings for every file that includes amdgpu.h. It makes sense to inline this amdgpu_mn stubs to avoid the warning. Signed-off-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Cc: stable@vger.kernel.org
|
#
6ef68c17 |
|
22-Oct-2015 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: remove amdgpu_fence_ref/unref Just move the remaining users to fence_put/get. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
|
#
16545c32 |
|
22-Oct-2015 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: use common fence for sync Stop using the driver internal functions. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
|
#
d5283298 |
|
22-Oct-2015 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: use common fences for VMID management v2 v2: add missing NULL check. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
|
#
8120b61f |
|
22-Oct-2015 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: move ring_from_fence to common code Going to need that elsewhere as well. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
|
#
ee327caf |
|
20-Oct-2015 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: switch to common fence_wait_any_timeout v2 No need to duplicate the functionality any more. v2: fix handling if no fence is available. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> (v1)
|
#
c86f5ebf |
|
23-Oct-2015 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: don't try to recreate sysfs entries on resume Fixes an error on resume caused by: fa022a9b65d2886486a022fd66b20c823cd76ad9 Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
|
#
ce16b0e5 |
|
05-Sep-2015 |
Junwei Zhang <Jerry.Zhang@amd.com> |
drm/amdgpu: remove the unnecessary parameter adev for amdgpu_fence_wait_any() Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com>
|
#
0c418f10 |
|
01-Sep-2015 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: remove the exclusive lock Finally getting rid of it. Signed-off-by: Christian König <christian.koenig@amd.com>
|
#
b7e4dad3 |
|
01-Sep-2015 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: remove old lockup detection infrastructure It didn't worked to well anyway. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
|
#
b495bd3a |
|
10-Sep-2015 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: add option to clear VM page tables after every submit This makes it much easier to find when userspace misses to send some buffers. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
|
#
d9c13156 |
|
27-Sep-2015 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: add option to stop on VM fault Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
|
#
c113ea1c |
|
08-Oct-2015 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: rework sdma structures Rework the sdma structures in the driver to consolidate all of the sdma info into a single structure and allow for asics that may have different numbers of sdma instances. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
88e72717 |
|
24-Sep-2015 |
Thierry Reding <treding@nvidia.com> |
drm/irq: Use unsigned int pipe in public API This continues the pattern started in commit cc1ef118fc09 ("drm/irq: Make pipe unsigned and name consistent"). This is applied to the public APIs and driver callbacks, so pretty much all drivers need to be updated to match the new prototypes. Cc: Christian König <christian.koenig@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Russell King <rmk+kernel@arm.linux.org.uk> Cc: Inki Dae <inki.dae@samsung.com> Cc: Jianwei Wang <jianwei.wang.chn@gmail.com> Cc: Alison Wang <alison.wang@freescale.com> Cc: Patrik Jakobsson <patrik.r.jakobsson@gmail.com> Cc: Daniel Vetter <daniel.vetter@intel.com> Cc: Jani Nikula <jani.nikula@linux.intel.com> Cc: Philipp Zabel <p.zabel@pengutronix.de> Cc: David Airlie <airlied@linux.ie> Cc: Rob Clark <robdclark@gmail.com> Cc: Ben Skeggs <bskeggs@redhat.com> Cc: Tomi Valkeinen <tomi.valkeinen@ti.com> Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Cc: Mark Yao <mark.yao@rock-chips.com> Cc: Benjamin Gaignard <benjamin.gaignard@linaro.org> Cc: Vincent Abriou <vincent.abriou@st.com> Cc: Thomas Hellstrom <thellstrom@vmware.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
|
#
5c3422b0 |
|
22-Sep-2015 |
monk.liu <monk.liu@amd.com> |
drm/amdgpu: sync ce and me with SWITCH_BUFFER(2) we used to adopt wait_reg_mem to let CE wait before DE finish page updating, but from Tonga+, CE doesn't support wait_reg_mem package so this logic no longer works. so here is another approach to do same thing: Insert two of SWITCH_BUFFER at both front and end of vm_flush can guarantee that CE not go further to process IB_const before vm_flush done. Insert two of SWITCH_BUFFER also works on CI, so remove legency method to sync CE and ME v2: Insert double SWITCH_BUFFER at front of vm flush as well. Signed-off-by: monk.liu <monk.liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com>
|
#
4f839a24 |
|
08-Sep-2015 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: more scheduler cleanups v2 Embed the scheduler into the ring structure instead of allocating it. Use the ring name directly instead of the id. v2: rebased, whitespace cleanup Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com> Reviewed-by: Chunming Zhou<david1.zhou@amd.com>
|
#
9b398fa5 |
|
07-Sep-2015 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: rename fence->scheduler to sched v2 Just to be consistent with the other members. v2: rename the ring member as well. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com> (v1) Reviewed-by: Chunming Zhou<david1.zhou@amd.com>
|
#
a6db8a33 |
|
08-Sep-2015 |
Junwei Zhang <Jerry.Zhang@amd.com> |
drm/amdgpu: refine the scheduler job type conversion Use container_of rather than casting. Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: David Zhou <david1.zhou@amd.com> Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com>
|
#
4c7eb91c |
|
08-Sep-2015 |
Junwei Zhang <Jerry.Zhang@amd.com> |
drm/amdgpu: refine the job naming for amdgpu_job and amdgpu_sched_job Use consistent naming across functions. Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: David Zhou <david1.zhou@amd.com> Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com>
|
#
3daea9e3d |
|
05-Sep-2015 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: add option to disable semaphores Provide module parameter to enable/disable them. Still enabled by default. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
|
#
edff0e28 |
|
31-Aug-2015 |
Jammy Zhou <Jammy.Zhou@amd.com> |
drm/amdgpu: add insert_nop ring func and default implementation The insert_nop function is added to amdgpu_ring_funcs structure as well as the default implementation Signed-off-by: Jammy Zhou <Jammy.Zhou@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
|
#
4b2f7e2c |
|
31-Aug-2015 |
Jammy Zhou <Jammy.Zhou@amd.com> |
drm/amdgpu: add amdgpu_get_sdma_instance helper function This function is added to map the ring to sdma instance Signed-off-by: Jammy Zhou <Jammy.Zhou@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
|
#
36f523a7 |
|
31-Aug-2015 |
Jammy Zhou <Jammy.Zhou@amd.com> |
drm/amdgpu: add AMDGPU_MAX_SDMA_INSTANCES Remove the hardcoded usage Signed-off-by: Jammy Zhou <Jammy.Zhou@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
|
#
18111de0 |
|
31-Aug-2015 |
Jammy Zhou <Jammy.Zhou@amd.com> |
drm/amdgpu: add burst_nop flag for sdma The burst NOP is supported for SDMA when feature_version is >= 20. Signed-off-by: Jammy Zhou <Jammy.Zhou@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
|
#
8221d706 |
|
01-Sep-2015 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: partially revert "modify amdgpu_fence_wait_any() to amdgpu_fence_wait_multiple()" v2 That isn't used any more. v2: rebase Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
6e7a3840 |
|
26-Aug-2015 |
Chunming Zhou <david1.zhou@amd.com> |
drm/amdgpu: use IB for fill_buffer instead of direct command Signed-off-by: Chunming Zhou <david1.zhou@amd.com> Reviewed-by: Christian K?nig <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
|
#
8f8202f7 |
|
07-May-2015 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: stop trying to suspend UVD sessions v2 Saving the current UVD state on suspend and restoring it on resume just doesn't work reliable. Just close cleanup all sessions on suspend. Ported from radeon commit "12e49feadff6d7b7ebbe852b36943a71524d8d34". v2: rebased Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> (v1)
|
#
e61235db |
|
25-Aug-2015 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: add scheduler dependency callback v2 This way the scheduler doesn't wait in it's work thread any more. v2: fix race conditions Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
|
#
c7ae72c0 |
|
25-Aug-2015 |
Chunming Zhou <david1.zhou@amd.com> |
drm/amdgpu: use IB for copy buffer of eviction This aids handling buffers moves with the scheduler. Signed-off-by: Chunming Zhou <david1.zhou@amd.com> Reviewed-by: Christian K?nig <christian.koenig@amd.com>
|
#
3c62338c |
|
20-Aug-2015 |
Chunming Zhou <david1.zhou@amd.com> |
drm/amdgpu: fix last_vm_update fence is not effetive for sched fence Signed-off-by: Chunming Zhou <david1.zhou@amd.com> Reviewed-by: Christian K?nig <christian.koenig@amd.com>
|
#
84f76ea6 |
|
23-Aug-2015 |
Chunming Zhou <david1.zhou@amd.com> |
drm/amdgpu: add owner for sched fence Signed-off-by: Chunming Zhou <david1.zhou@amd.com> Reviewed-by: Christian K?nig <christian.koenig@amd.com>
|
#
87e0a87d |
|
20-Aug-2015 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: remove amdgpu_bo_list_clone Not used any more. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
|
#
3a185a33 |
|
20-Aug-2015 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: remove the context from amdgpu_job Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
|
#
f91b3a69 |
|
20-Aug-2015 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: fix fence wait in sync_fence, instead should be in sync_rings Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Chunming Zhou <david1.zhou@amd.com> Reviewed-by: Christian K?nig <christian.koenig@amd.com>
|
#
ce882e6d |
|
19-Aug-2015 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: remove v_seq handling from the scheduler v2 Simply not used any more. Only keep 32bit atomic for fence sequence numbering. v2: trivial rebase Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> (v1) Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com> (v1) Reviewed-by: Chunming Zhou <david1.zhou@amd.com> (v1)
|
#
4ce9891e |
|
19-Aug-2015 |
Chunming Zhou <david1.zhou@amd.com> |
drm/amdgpu: improve sa_bo->fence by kernel fence Signed-off-by: Chunming Zhou <david1.zhou@amd.com> Reviewed-by: Christian K?nig <christian.koenig@amd.com>
|
#
1aa4051b |
|
19-Aug-2015 |
Junwei Zhang <Jerry.Zhang@amd.com> |
drm/amdgpu: modify amdgpu_fence_wait_any() to amdgpu_fence_wait_multiple() Rename the function and update the related code with this modified function. Add the new parameter of bool wait_all. If wait_all is true, it will return when all fences are signaled or timeout. If wait_all is false, it will return when any fence is signaled or timeout. Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com> Reviewed-by: Monk Liu <monk.liu@amd.com> Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com>
|
#
3c4adead |
|
18-Aug-2015 |
Chunming Zhou <david1.zhou@amd.com> |
drm/amdgpu: some clean up for cs_ioctl Signed-off-by: Chunming Zhou <david1.zhou@amd.com> Reviewed-by: Christian K?nig <christian.koenig@amd.com>
|
#
bb977d37 |
|
18-Aug-2015 |
Chunming Zhou <david1.zhou@amd.com> |
drm/amdgpu: abstract amdgpu_job for scheduler Signed-off-by: Chunming Zhou <david1.zhou@amd.com> Reviewed-by: Christian K?nig <christian.koenig@amd.com>
|
#
05906dec |
|
14-Aug-2015 |
Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> |
drm/amdgpu: wait on page directory changes. v2 Pagetables can be moved and therefore the page directory update can be necessary for the current cs even if none of the the bo's are moved. In that scenario there is no fence between the sdma0 and gfx ring, so we add one. v2 (chk): rebased Signed-off-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
|
#
1ffd2652 |
|
11-Aug-2015 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: fix waiting for all fences before flipping Otherwise we might see corruption. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
|
#
02bc0650 |
|
07-Aug-2015 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: remove amdgpu_fence_wait It was just a wrapper for fence_wait anyway. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
|
#
3cdb8119 |
|
06-Aug-2015 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: remove amdgpu_fence_signaled The common kernel function does the same thing. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
|
#
f556cb0c |
|
01-Aug-2015 |
Chunming Zhou <david1.zhou@amd.com> |
drm/amd: add scheduler fence implementation (v2) scheduler fence is based on kernel fence framework. v2: squash in Christian's build fix Signed-off-by: Chunming Zhou <david1.zhou@amd.com> Reviewed-by: Christian K?nig <christian.koenig@amd.com>
|
#
4af9f07c |
|
02-Aug-2015 |
Chunming Zhou <david1.zhou@amd.com> |
drm/amdgpu: use kernel submit helper in vm Signed-off-by: Chunming Zhou <david1.zhou@amd.com> Reviewed-by: Christian K?nig <christian.koenig@amd.com>
|
#
91404fb2 |
|
05-Aug-2015 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: merge amd_sched_entity and amd_context_entity v2 Avoiding a couple of casts. v2: rename c_entity to entity as well Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
|
#
4cef9267 |
|
05-Aug-2015 |
Chunming Zhou <david1.zhou@amd.com> |
drm/amdgpu: process sched job exactly triggered by fence signal Signed-off-by: Chunming Zhou <david1.zhou@amd.com> Reviewed-by: Christian K?nig <christian.koenig@amd.com>
|
#
47f38501 |
|
04-Aug-2015 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: cleanup amdgpu_ctx inti/fini v2 Cleanup the kernel context handling. v2: rebased Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> (v1)
|
#
efd4ccb5 |
|
04-Aug-2015 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: cleanup ctx_mgr init/fini Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
|
#
34cb581a |
|
04-Aug-2015 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: fix bo list handling in CS We didn't initialized the mutex in the cloned bo list resulting in nice warnings from lockdep. Also fixes error handling in this function. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
|
#
7484667c |
|
03-Aug-2015 |
Chunming Zhou <david1.zhou@amd.com> |
drm/amdgpu: move sched job process from isr to fence callback This way can avoid interrupt lost, and can process sched job exactly. Signed-off-by: Chunming Zhou <david1.zhou@amd.com> Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
|
#
1763552e |
|
02-Aug-2015 |
Chunming Zhou <david1.zhou@amd.com> |
drm/amdgpu: add kernel fence in ib_submit_kernel_helper every sbumission should be able to get a fence. Signed-off-by: Chunming Zhou <david1.zhou@amd.com> Reviewed-by: Christian K?nig <christian.koenig@amd.com> Reviewed-by: Jammy Zhou <jammy.zhou@amd.com>
|
#
bb1e38a4 |
|
03-Aug-2015 |
Chunming Zhou <david1.zhou@amd.com> |
drm/amdgpu: use kernel fence for last_pt_update Signed-off-by: Chunming Zhou <david1.zhou@amd.com> Reviewed-by: Christian K?nig <christian.koenig@amd.com> Reviewed-by: Jammy Zhou <jammy.zhou@amd.com>
|
#
7fc11959 |
|
30-Jul-2015 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: stop using addr to check for BO move v3 It is theoretically possible that a swapped out BO gets the same GTT address, but different backing pages while being swapped in. Instead just use another VA state to note updated areas. Ported from not upstream yet radeon commit with the same name. v2: fix some bugs in the original implementation found in the radeon code. v3: squash in VCE/UVD fix Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
|
#
7f06c236 |
|
30-Jul-2015 |
monk.liu <monk.liu@amd.com> |
drm/amdgpu: move wait_queue_head from adev to ring (v2) thus unnecessary wake up could be avoid between rings v2: move wait_queue_head to fence_drv from ring Signed-off-by: monk.liu <monk.liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com>
|
#
332dfe90 |
|
30-Jul-2015 |
monk.liu <monk.liu@amd.com> |
drm/amdgpu: new implement for fence_wait_any (v2) origninal method will sleep/schedule at the granurarity of HZ/2 and based on seq signal method, the new implement is based on kernel fance interface, no unnecessary schedule at all v2: replace logic of original amdgpu_fence_wait_any Signed-off-by: monk.liu <monk.liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com>
|
#
3c704e93 |
|
28-Jul-2015 |
Chunming Zhou <david1.zhou@amd.com> |
drm/amdgpu: add helper function for kernel submission Signed-off-by: Chunming Zhou <david1.zhou@amd.com> Reviewed-by: Christian K?nig <christian.koenig@amd.com>
|
#
d1ff9086 |
|
30-Jul-2015 |
Chunming Zhou <david1.zhou@amd.com> |
drm/amdgpu: fix seq in ctx_add_fence if enabling scheduler, then the queued seq is assigned when pushing job before emitting job. Signed-off-by: Chunming Zhou <david1.zhou@amd.com> Reviewed-by: Christian K?nig <christian.koenig@amd.com>
|
#
4afcb303 |
|
30-Jul-2015 |
Jammy Zhou <Jammy.Zhou@amd.com> |
drm/amdgpu: add amdgpu.sched_hw_submission option This option can be used to specify the max number of submissions in the active HW queue. The default value is 2 now. Signed-off-by: Jammy Zhou <Jammy.Zhou@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
|
#
1333f723 |
|
30-Jul-2015 |
Jammy Zhou <Jammy.Zhou@amd.com> |
drm/amdgpu: add amdgpu.sched_jobs option This option can be used to specify the max job number in the job queue, and it is 16 by default. Signed-off-by: Jammy Zhou <Jammy.Zhou@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
|
#
176e1ab1 |
|
23-Jul-2015 |
Chunming Zhou <david1.zhou@amd.com> |
drm/amdgpu: protect fence_process from multiple context fence_process may be called from kthread, user thread and interrupt context. it is possible to called concurrently, then will wake up fence queue multiple times. Signed-off-by: Chunming Zhou <david1.zhou@amd.com> Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
|
#
d5fc5e82 |
|
21-Jul-2015 |
Chunming Zhou <david1.zhou@amd.com> |
drm/amdgpu: dispatch job for vm use kernel context to submit command for vm Signed-off-by: Chunming Zhou <david1.zhou@amd.com> Acked-by: Christian K?nig <christian.koenig@amd.com> Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
|
#
23ca0e4e |
|
05-Jul-2015 |
Chunming Zhou <david1.zhou@amd.com> |
drm/amdgpu: add kernel ctx support (v2) v2: rebase against kfd changes Signed-off-by: Chunming Zhou <david1.zhou@amd.com> Acked-by: Christian K?nig <christian.koenig@amd.com> Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
|
#
4274f5d4 |
|
21-Jul-2015 |
Chunming Zhou <david1.zhou@amd.com> |
drm/amdgpu: prepare job before push to sw queue for pte ring user mode will still use pte ring as a normal ring. if the prepare job generates another command(update pte) on its ring in scheduler, then will kill scheduler which is going to waiting later job but pending running job. Signed-off-by: Chunming Zhou <david1.zhou@amd.com> Acked-by: Christian K?nig <christian.koenig@amd.com> Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
|
#
4b559c90 |
|
21-Jul-2015 |
Chunming Zhou <david1.zhou@amd.com> |
drm/amdgpu: make sure the fence is emitted before ring to get it. Signed-off-by: Chunming Zhou <david1.zhou@amd.com> Acked-by: Christian K?nig <christian.koenig@amd.com> Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
|
#
049fc527 |
|
21-Jul-2015 |
Chunming Zhou <david1.zhou@amd.com> |
drm/amdgpu: dispatch jobs in cs BO validation is moved to scheduler except usrptr which must be validated in user process Signed-off-by: Chunming Zhou <david1.zhou@amd.com> Acked-by: Christian K?nig <christian.koenig@amd.com> Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
|
#
372bc1e1 |
|
20-Jul-2015 |
Chunming Zhou <david1.zhou@amd.com> |
drm/amdgpu: add bo list copy Signed-off-by: Chunming Zhou <david1.zhou@amd.com> Acked-by: Christian K?nig <christian.koenig@amd.com> Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
|
#
c1b69ed0 |
|
20-Jul-2015 |
Chunming Zhou <david1.zhou@amd.com> |
drm/amdgpu: add backend implementation of gpu scheduler (v2) v2: fix rebase breakage Signed-off-by: Chunming Zhou <david1.zhou@amd.com> Acked-by: Christian K?nig <christian.koenig@amd.com> Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
|
#
9cb7e5a9 |
|
20-Jul-2015 |
Chunming Zhou <david1.zhou@amd.com> |
drm/amdgpu: add context entity init Signed-off-by: Chunming Zhou <david1.zhou@amd.com> Acked-by: Christian K?nig <christian.koenig@amd.com> Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
|
#
b80d8475 |
|
16-Aug-2015 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: add scheduler initialization 1. Add kernel parameter option, default 0 2. Add scheduler initialization for amdgpu Signed-off-by: Chunming Zhou <David1.Zhou@amd.com> Signed-off-by: Jammy Zhou <Jammy.Zhou@amd.com> Acked-by: Christian K?nig <christian.koenig@amd.com> Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
|
#
2f7d10b3 |
|
21-Jul-2015 |
Jammy Zhou <Jammy.Zhou@amd.com> |
drm/amdgpu: merge amdgpu_family.h into amd_shared.h (v2) Make the definitions common for all driver components v2: fix kfd Signed-off-by: Jammy Zhou <Jammy.Zhou@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
|
#
5430a3ff |
|
21-Jul-2015 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: fix UVD/VCE fence handling We need to return the sequence number to userspace even when we don't use user fences. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
|
#
5ceb54c6 |
|
04-Aug-2015 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: add fence suspend/resume functions Added to: - handle draining the ring on suspend - properly enable/disable interrupts on suspend and resume Fix breakages from: commit 467ee3be53d240d08beed2e82a941e820c1ac323 Author: Chunming Zhou <david1.zhou@amd.com> Date: Mon Jun 1 14:14:32 2015 +0800 drm/amdgpu: always enable EOP interrupt v2 Tested-by: Audrey Grodzovsky <audrey.grodzovsky@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
c6a4079b |
|
01-Jun-2015 |
Chunming Zhou <david1.zhou@amd.com> |
drm/amdgpu: always enable EOP interrupt v2 v2 (chk): always enable EOP interrupt, independent of scheduler, remove now unused delayed_irq handling. Signed-off-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
|
#
7f8a5290 |
|
20-Jul-2015 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: rework vm_grab_id interface This makes assigning VM IDs independent from the use of VM IDs. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
|
#
0753b452 |
|
07-Jul-2015 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: remove amdgpu_fence_recreate It's not used any more. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
|
#
21c16bf6 |
|
07-Jul-2015 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: add user fence context map v2 This is a prerequisite for the GPU scheduler to make the order of submission independent from the order of execution. v2: properly implement the locking Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
|
#
91e1a520 |
|
06-Jul-2015 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: deal with foreign fences in amdgpu_sync This also requires some error handling from the callers of that function. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
|
#
0b492a4c |
|
16-Aug-2015 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: cleanup context structure v2 The comment is misleading and incorrect, remove it. Printing the id is completely meaningless and this practice can cause a race conditions on command submission. The flags and hangs fields are completely unused. Give all fields a common indentation. v2: remove fpriv reference and unused flags as well, fix debug message. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
|
#
d03846af |
|
28-Jul-2015 |
Chunming Zhou <David1.Zhou@amd.com> |
drm/amd: Add CGS interfaces CGS (Common Graphics Services) is an AMD cross component abstraction layer to designed to better encapsulate specific IP block drivers so different teams can effectively work on differnet IP block drivers independently. It provides a common interface for things like accessing registers, allocating GPU memory, and registering interrupt sources. The plan is to eventually move more and more IP drivers to this interface. The first user is the ACP IP driver. Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com> Signed-off-by: Chunming Zhou <David1.Zhou@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
cfa2104f |
|
03-Aug-2015 |
Jammy Zhou <Jammy.Zhou@amd.com> |
drm/amdgpu: add feature version for SDMA ucode Signed-off-by: Jammy Zhou <Jammy.Zhou@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com>
|
#
351643d7 |
|
03-Aug-2015 |
Jammy Zhou <Jammy.Zhou@amd.com> |
drm/amdgpu: add feature version for RLC and MEC v2 Expose feature version to user space for RLC/MEC/MEC2 ucode as well v2: fix coding style Signed-off-by: Jammy Zhou <Jammy.Zhou@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com>
|
#
8faf0e08 |
|
28-Jul-2015 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: clean up init sequence for failures If we fail during device init, record what state each block is in so that we can tear down clearly. Fixes various problems on device init failure. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
6a585777 |
|
10-Jul-2015 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: implement VCE 3.0 harvesting support (v4) For boards with bad VCE blocks, only configure the working block. v2: use the harvest info for pipe setup v3: fix mask check as noted by Leo v4: add dGPU support Reviewed-by: Christian König <christian.koenig@amd.com> (v2) Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
130e0371 |
|
12-Jun-2015 |
Oded Gabbay <oded.gabbay@gmail.com> |
drm/amdgpu: Add H/W agnostic amdgpu <--> amdkfd interface This patch adds an interface file between amdgpu and amdkfd. This interface file is H/W agnostic, thus containing functions that operate the same for any AMD APU/GPU H/W generation. The functions in this interface mirror (some) of the functions in radeon_kfd.c (the radeon<-->amdkfd interface file). The main functions are: - amdgpu_amdkfd_init - initialize the amdkfd module - amdgpu_amdkfd_load_interface - load the H/W interface according to the currently probed device - amdgpu_amdkfd_device_probe - probe the device in amdkfd - amdgpu_amdkfd_device_init - initialize the device in amdkfd - amdgpu_amdkfd_interrupt - call the ISR of amdkfd - amdgpu_amdkfd_suspend - suspend callback from amdgpu - amdgpu_amdkfd_resume - resume callback from amdgpu This patch also modifies the relevant amdgpu files, to use this new interface. Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com>
|
#
03507c4f |
|
19-Jun-2015 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: recreate fence from user seq And use common fence infrastructure for the wait. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
|
#
f1689ec1 |
|
11-Jun-2015 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: check VCE relocation buffer range port of radeon commit 2fc5703abda201f138faf63bdca743d04dbf4b1a. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com>
|
#
b7a07769 |
|
28-May-2015 |
Sonny Jiang <sonny.jiang@amd.com> |
drm/amdgpu: enable vce powergating Enable VCE dpm and powergating. VCE dpm dynamically scales the VCE clocks on demand. Signed-off-by: Sonny Jiang <sonny.jiang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com>
|
#
890ee23f |
|
01-Jun-2015 |
Chunming Zhou <david1.zhou@amd.com> |
drm/amdgpu: disable user fence interrupt (v2) amdgpu submits both kernel and user fences, but just need one interrupt, disable user fence interrupt and don't effect user fence. v2: fix merge error Signed-off-by: Chunming Zhou <david1.zhou@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
|
#
3ccec53c |
|
02-Jun-2015 |
Marek Olšák <marek.olsak@amd.com> |
drm/amdgpu: only support IBs in the buffer list (v2) amdgpu_cs_find_mapping doesn't work without all buffers being validated, so the TTM validation must be done first. v2: only use amdgpu_cs_find_mapping for UVD/VCE VM emulation Signed-off-by: Marek Olšák <marek.olsak@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com>
|
#
81c59f54 |
|
03-Jun-2015 |
Ken Wang <Qingqing.Wang@amd.com> |
drm/amdgpu: add vram_type and vram_bit_width for interface query (v2) Track the type of vram on the board and provide a query for it. User mode drivers and tools want this information for determining bandwidth information and form informational purposes. v2: fix build when CI support is not enabled Signed-off-by: Ken Wang <Qingqing.Wang@amd.com> Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
|
#
02558a00 |
|
03-Jun-2015 |
Ken Wang <Qingqing.Wang@amd.com> |
drm/amdgpu: add me/ce/pfp_feature_version interface query Provide this information to usermode drivers. We were previously missing this info. Signed-off-by: Ken Wang <Qingqing.Wang@amd.com> Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
|
#
a101a899 |
|
03-Jun-2015 |
Ken Wang <Qingqing.Wang@amd.com> |
drm/amdgpu add ce_ram_size for interface query Add a query for the CE ram size. User mode drivers will want to use this to determine how much size of the cache on the CE. Signed-off-by: Ken Wang <Qingqing.Wang@amd.com> Reviewd-by: Jammy Zhou <Jammy.Zhou@amd.com>
|
#
e176fe17 |
|
27-May-2015 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: remove mclk_lock Not needed any more. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
|
#
cfe2c978 |
|
26-May-2015 |
monk.liu <monk.liu@amd.com> |
drm/amdgpu: sync fence of clear_invalids (v2) bo_va may un-initialized, fix it. Signed-off-by: monk.liu <monk.liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Jammy Zhou <jammy.zhou@amd.com>
|
#
7e5a547f |
|
24-Apr-2015 |
Chunming Zhou <david1.zhou@amd.com> |
drm/amdgpu: implement the allocation range (v3) Pass a ttm_placement pointer to amdgpu_bo_create_restricted add min_offset to amdgpu_bo_pin_restricted. This makes it easier to allocate memory with address restrictions. With this patch we can also enable 2-ended allocation again. v2: fix rebase conflicts v3: memset placements before using Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com> Signed-off-by: Chunming Zhou <david1.zhou@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
|
#
5fc3aeeb |
|
22-May-2015 |
yanyang1 <young.yang@amd.com> |
drm/amdgpu: rename amdgpu_ip_funcs to amd_ip_funcs (v2) The structure is renamed and moved to amd_shared.h to make the component independent. This makes it easier to add new components in the future. v2: fix include path Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com> Signed-off-by: yanyang1 <young.yang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
9269a606 |
|
22-May-2015 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: drop AMDGPU_FENCE_SIGNALED_SEQ It's causing issues with VMID handling and comparing the fence value two times actually doesn't make handling faster. Port of radeon commit "d6d5c5b8364bcc4d52cddc68bcb0a330d2af20f3". Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Monk Liu <monk.liu@amd.com>
|
#
e9822622 |
|
06-May-2015 |
Leo Liu <leo.liu@amd.com> |
drm/amdgpu: recalculate VCE firmware BO size Firmware required BO size changes in terms of ASIC family Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com>
|
#
d94aed5a |
|
05-May-2015 |
Marek Olšák <marek.olsak@amd.com> |
drm/amdgpu: add and implement the GPU reset status query Signed-off-by: Marek Olšák <marek.olsak@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
|
#
86c2b790 |
|
13-May-2015 |
Jammy Zhou <Jammy.Zhou@amd.com> |
drm/amdgpu: rewording some left radeons Signed-off-by: Jammy Zhou <Jammy.Zhou@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com>
|
#
3cb485f3 |
|
11-May-2015 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: fix context switch Properly protect the state and also handle submission failures. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com> Reviewed-by: Monk Liu <monk.liu@amd.com>
|
#
d2edb07b |
|
11-May-2015 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: cleanup HDP flush handling Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com> Reviewed-by: Monk Liu <monk.liu@amd.com>
|
#
de807f81 |
|
11-May-2015 |
Jammy Zhou <Jammy.Zhou@amd.com> |
drm/amdgpu: add flags for amdgpu_ib structure Signed-off-by: Jammy Zhou <Jammy.Zhou@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com>
|
#
72efa7eb |
|
08-May-2015 |
Jammy Zhou <Jammy.Zhou@amd.com> |
drm/amdgpu: check context id for context switching (v2) check the filp is not robust, and sometimes different contexts may have same filp value. v2: check both filp and ctx_id Signed-off-by: Jammy Zhou <Jammy.Zhou@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com>
|
#
66b3cf2a |
|
08-May-2015 |
Jammy Zhou <Jammy.Zhou@amd.com> |
drm/amdgpu: add ctx_id to the WAIT_CS IOCTL (v4) It is required to support fence per context. v2: add amdgpu_ctx_get/put v3: improve get/put v4: squash hlock fix Signed-off-by: Jammy Zhou <Jammy.Zhou@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com>
|
#
0147ee0f |
|
05-May-2015 |
Marek Olšák <marek.olsak@amd.com> |
drm/amdgpu: make the CTX ioctl thread-safe The existing locks were protecting the list, but not the elements. v2: rename hlock to lock Signed-off-by: Marek Olšák <marek.olsak@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
|
#
97b2e202 |
|
20-Apr-2015 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: add amdgpu.h (v2) This is the main header file for amdgpu. v2: remove stable comments Acked-by: Christian König <christian.koenig@amd.com> Acked-by: Jammy Zhou <Jammy.Zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|