1/* 2 * Copyright 2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 27#include "reg_helper.h" 28 29#include "core_types.h" 30#include "link_encoder.h" 31#include "dcn31/dcn31_dio_link_encoder.h" 32#include "dcn32_dio_link_encoder.h" 33#include "stream_encoder.h" 34#include "dc_bios_types.h" 35#include "link_enc_cfg.h" 36 37#include "dc_dmub_srv.h" 38#include "gpio_service_interface.h" 39 40#ifndef MIN 41#define MIN(X, Y) ((X) < (Y) ? (X) : (Y)) 42#endif 43 44#define CTX \ 45 enc10->base.ctx 46#define DC_LOGGER \ 47 enc10->base.ctx->logger 48 49#define REG(reg)\ 50 (enc10->link_regs->reg) 51 52#undef FN 53#define FN(reg_name, field_name) \ 54 enc10->link_shift->field_name, enc10->link_mask->field_name 55 56#define AUX_REG(reg)\ 57 (enc10->aux_regs->reg) 58 59#define AUX_REG_READ(reg_name) \ 60 dm_read_reg(CTX, AUX_REG(reg_name)) 61 62#define AUX_REG_WRITE(reg_name, val) \ 63 dm_write_reg(CTX, AUX_REG(reg_name), val) 64 65static uint8_t phy_id_from_transmitter(enum transmitter t) 66{ 67 uint8_t phy_id; 68 69 switch (t) { 70 case TRANSMITTER_UNIPHY_A: 71 phy_id = 0; 72 break; 73 case TRANSMITTER_UNIPHY_B: 74 phy_id = 1; 75 break; 76 case TRANSMITTER_UNIPHY_C: 77 phy_id = 2; 78 break; 79 case TRANSMITTER_UNIPHY_D: 80 phy_id = 3; 81 break; 82 case TRANSMITTER_UNIPHY_E: 83 phy_id = 4; 84 break; 85 case TRANSMITTER_UNIPHY_F: 86 phy_id = 5; 87 break; 88 case TRANSMITTER_UNIPHY_G: 89 phy_id = 6; 90 break; 91 default: 92 phy_id = 0; 93 break; 94 } 95 return phy_id; 96} 97 98void enc32_hw_init(struct link_encoder *enc) 99{ 100 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc); 101 102/* 103 00 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__1to2 : 1/2 104 01 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__3to4 : 3/4 105 02 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__7to8 : 7/8 106 03 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__15to16 : 15/16 107 04 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__31to32 : 31/32 108 05 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__63to64 : 63/64 109 06 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__127to128 : 127/128 110 07 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__255to256 : 255/256 111*/ 112 113/* 114 AUX_REG_UPDATE_5(AUX_DPHY_RX_CONTROL0, 115 AUX_RX_START_WINDOW = 1 [6:4] 116 AUX_RX_RECEIVE_WINDOW = 1 default is 2 [10:8] 117 AUX_RX_HALF_SYM_DETECT_LEN = 1 [13:12] default is 1 118 AUX_RX_TRANSITION_FILTER_EN = 1 [16] default is 1 119 AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT [17] is 0 default is 0 120 AUX_RX_ALLOW_BELOW_THRESHOLD_START [18] is 1 default is 1 121 AUX_RX_ALLOW_BELOW_THRESHOLD_STOP [19] is 1 default is 1 122 AUX_RX_PHASE_DETECT_LEN, [21,20] = 0x3 default is 3 123 AUX_RX_DETECTION_THRESHOLD [30:28] = 1 124*/ 125 AUX_REG_WRITE(AUX_DPHY_RX_CONTROL0, 0x103d1110); 126 127 AUX_REG_WRITE(AUX_DPHY_TX_CONTROL, 0x21c7a); 128 129 //AUX_DPHY_TX_REF_CONTROL'AUX_TX_REF_DIV HW default is 0x32; 130 // Set AUX_TX_REF_DIV Divider to generate 2 MHz reference from refclk 131 // 27MHz -> 0xd 132 // 100MHz -> 0x32 133 // 48MHz -> 0x18 134 135 // Set TMDS_CTL0 to 1. This is a legacy setting. 136 REG_UPDATE(TMDS_CTL_BITS, TMDS_CTL0, 1); 137 138 dcn10_aux_initialize(enc10); 139} 140 141 142void dcn32_link_encoder_enable_dp_output( 143 struct link_encoder *enc, 144 const struct dc_link_settings *link_settings, 145 enum clock_source_id clock_source) 146{ 147 if (!enc->ctx->dc->debug.avoid_vbios_exec_table) { 148 dcn10_link_encoder_enable_dp_output(enc, link_settings, clock_source); 149 return; 150 } 151} 152 153static bool query_dp_alt_from_dmub(struct link_encoder *enc, 154 union dmub_rb_cmd *cmd) 155{ 156 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc); 157 158 memset(cmd, 0, sizeof(*cmd)); 159 cmd->query_dp_alt.header.type = DMUB_CMD__VBIOS; 160 cmd->query_dp_alt.header.sub_type = 161 DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT; 162 cmd->query_dp_alt.header.payload_bytes = sizeof(cmd->query_dp_alt.data); 163 cmd->query_dp_alt.data.phy_id = phy_id_from_transmitter(enc10->base.transmitter); 164 165 if (!dc_wake_and_execute_dmub_cmd(enc->ctx, cmd, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY)) 166 return false; 167 168 return true; 169} 170 171bool dcn32_link_encoder_is_in_alt_mode(struct link_encoder *enc) 172{ 173 union dmub_rb_cmd cmd; 174 175 if (!query_dp_alt_from_dmub(enc, &cmd)) 176 return false; 177 178 return (cmd.query_dp_alt.data.is_dp_alt_disable == 0); 179} 180 181void dcn32_link_encoder_get_max_link_cap(struct link_encoder *enc, 182 struct dc_link_settings *link_settings) 183{ 184 union dmub_rb_cmd cmd; 185 186 dcn10_link_encoder_get_max_link_cap(enc, link_settings); 187 188 if (!query_dp_alt_from_dmub(enc, &cmd)) 189 return; 190 191 if (cmd.query_dp_alt.data.is_usb && 192 cmd.query_dp_alt.data.is_dp4 == 0) 193 link_settings->lane_count = MIN(LANE_COUNT_TWO, link_settings->lane_count); 194} 195 196 197static const struct link_encoder_funcs dcn32_link_enc_funcs = { 198 .read_state = link_enc2_read_state, 199 .validate_output_with_stream = 200 dcn30_link_encoder_validate_output_with_stream, 201 .hw_init = enc32_hw_init, 202 .setup = dcn10_link_encoder_setup, 203 .enable_tmds_output = dcn10_link_encoder_enable_tmds_output, 204 .enable_dp_output = dcn32_link_encoder_enable_dp_output, 205 .enable_dp_mst_output = dcn10_link_encoder_enable_dp_mst_output, 206 .disable_output = dcn10_link_encoder_disable_output, 207 .dp_set_lane_settings = dcn10_link_encoder_dp_set_lane_settings, 208 .dp_set_phy_pattern = dcn10_link_encoder_dp_set_phy_pattern, 209 .update_mst_stream_allocation_table = 210 dcn10_link_encoder_update_mst_stream_allocation_table, 211 .psr_program_dp_dphy_fast_training = 212 dcn10_psr_program_dp_dphy_fast_training, 213 .psr_program_secondary_packet = dcn10_psr_program_secondary_packet, 214 .connect_dig_be_to_fe = dcn10_link_encoder_connect_dig_be_to_fe, 215 .enable_hpd = dcn10_link_encoder_enable_hpd, 216 .disable_hpd = dcn10_link_encoder_disable_hpd, 217 .is_dig_enabled = dcn10_is_dig_enabled, 218 .destroy = dcn10_link_encoder_destroy, 219 .fec_set_enable = enc2_fec_set_enable, 220 .fec_set_ready = enc2_fec_set_ready, 221 .fec_is_active = enc2_fec_is_active, 222 .get_dig_frontend = dcn10_get_dig_frontend, 223 .get_dig_mode = dcn10_get_dig_mode, 224 .is_in_alt_mode = dcn32_link_encoder_is_in_alt_mode, 225 .get_max_link_cap = dcn32_link_encoder_get_max_link_cap, 226 .set_dio_phy_mux = dcn31_link_encoder_set_dio_phy_mux, 227}; 228 229void dcn32_link_encoder_construct( 230 struct dcn20_link_encoder *enc20, 231 const struct encoder_init_data *init_data, 232 const struct encoder_feature_support *enc_features, 233 const struct dcn10_link_enc_registers *link_regs, 234 const struct dcn10_link_enc_aux_registers *aux_regs, 235 const struct dcn10_link_enc_hpd_registers *hpd_regs, 236 const struct dcn10_link_enc_shift *link_shift, 237 const struct dcn10_link_enc_mask *link_mask) 238{ 239 struct bp_connector_speed_cap_info bp_cap_info = {0}; 240 const struct dc_vbios_funcs *bp_funcs = init_data->ctx->dc_bios->funcs; 241 enum bp_result result = BP_RESULT_OK; 242 struct dcn10_link_encoder *enc10 = &enc20->enc10; 243 244 enc10->base.funcs = &dcn32_link_enc_funcs; 245 enc10->base.ctx = init_data->ctx; 246 enc10->base.id = init_data->encoder; 247 248 enc10->base.hpd_source = init_data->hpd_source; 249 enc10->base.connector = init_data->connector; 250 251 enc10->base.preferred_engine = ENGINE_ID_UNKNOWN; 252 253 enc10->base.features = *enc_features; 254 255 if (enc10->base.connector.id == CONNECTOR_ID_USBC) 256 enc10->base.features.flags.bits.DP_IS_USB_C = 1; 257 258 enc10->base.transmitter = init_data->transmitter; 259 260 /* set the flag to indicate whether driver poll the I2C data pin 261 * while doing the DP sink detect 262 */ 263 264/* if (dal_adapter_service_is_feature_supported(as, 265 FEATURE_DP_SINK_DETECT_POLL_DATA_PIN)) 266 enc10->base.features.flags.bits. 267 DP_SINK_DETECT_POLL_DATA_PIN = true;*/ 268 269 enc10->base.output_signals = 270 SIGNAL_TYPE_DVI_SINGLE_LINK | 271 SIGNAL_TYPE_DVI_DUAL_LINK | 272 SIGNAL_TYPE_LVDS | 273 SIGNAL_TYPE_DISPLAY_PORT | 274 SIGNAL_TYPE_DISPLAY_PORT_MST | 275 SIGNAL_TYPE_EDP | 276 SIGNAL_TYPE_HDMI_TYPE_A; 277 278 enc10->link_regs = link_regs; 279 enc10->aux_regs = aux_regs; 280 enc10->hpd_regs = hpd_regs; 281 enc10->link_shift = link_shift; 282 enc10->link_mask = link_mask; 283 284 switch (enc10->base.transmitter) { 285 case TRANSMITTER_UNIPHY_A: 286 enc10->base.preferred_engine = ENGINE_ID_DIGA; 287 break; 288 case TRANSMITTER_UNIPHY_B: 289 enc10->base.preferred_engine = ENGINE_ID_DIGB; 290 break; 291 case TRANSMITTER_UNIPHY_C: 292 enc10->base.preferred_engine = ENGINE_ID_DIGC; 293 break; 294 case TRANSMITTER_UNIPHY_D: 295 enc10->base.preferred_engine = ENGINE_ID_DIGD; 296 break; 297 case TRANSMITTER_UNIPHY_E: 298 enc10->base.preferred_engine = ENGINE_ID_DIGE; 299 break; 300 default: 301 ASSERT_CRITICAL(false); 302 enc10->base.preferred_engine = ENGINE_ID_UNKNOWN; 303 } 304 305 /* default to one to mirror Windows behavior */ 306 enc10->base.features.flags.bits.HDMI_6GB_EN = 1; 307 308 if (bp_funcs->get_connector_speed_cap_info) 309 result = bp_funcs->get_connector_speed_cap_info(enc10->base.ctx->dc_bios, 310 enc10->base.connector, &bp_cap_info); 311 312 /* Override features with DCE-specific values */ 313 if (result == BP_RESULT_OK) { 314 enc10->base.features.flags.bits.IS_HBR2_CAPABLE = 315 bp_cap_info.DP_HBR2_EN; 316 enc10->base.features.flags.bits.IS_HBR3_CAPABLE = 317 bp_cap_info.DP_HBR3_EN; 318 enc10->base.features.flags.bits.HDMI_6GB_EN = bp_cap_info.HDMI_6GB_EN; 319 enc10->base.features.flags.bits.IS_DP2_CAPABLE = 1; 320 enc10->base.features.flags.bits.IS_UHBR10_CAPABLE = bp_cap_info.DP_UHBR10_EN; 321 enc10->base.features.flags.bits.IS_UHBR13_5_CAPABLE = bp_cap_info.DP_UHBR13_5_EN; 322 enc10->base.features.flags.bits.IS_UHBR20_CAPABLE = bp_cap_info.DP_UHBR20_EN; 323 } else { 324 DC_LOG_WARNING("%s: Failed to get encoder_cap_info from VBIOS with error code %d!\n", 325 __func__, 326 result); 327 } 328 if (enc10->base.ctx->dc->debug.hdmi20_disable) { 329 enc10->base.features.flags.bits.HDMI_6GB_EN = 0; 330 } 331} 332