resource/dcn32/dcn32_resource.c

116 #define SR(reg_name)\
117 		REG_STRUCT.reg_name = BASE(reg ## reg_name ## _BASE_IDX) +  \
118 					reg ## reg_name
119 #define SR_ARR(reg_name, id) \
120 	REG_STRUCT[id].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
122 #define SR_ARR_INIT(reg_name, id, value) \
123 	REG_STRUCT[id].reg_name = value
125 #define SRI(reg_name, block, id)\
126 	REG_STRUCT.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
127 		reg ## block ## id ## _ ## reg_name
129 #define SRI_ARR(reg_name, block, id)\
130 	REG_STRUCT[id].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
131 		reg ## block ## id ## _ ## reg_name
133 #define SR_ARR_I2C(reg_name, id) \
134 	REG_STRUCT[id-1].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
136 #define SRI_ARR_I2C(reg_name, block, id)\
137 	REG_STRUCT[id-1].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
138 		reg ## block ## id ## _ ## reg_name
140 #define SRI_ARR_ALPHABET(reg_name, block, index, id)\
141 	REG_STRUCT[index].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
142 		reg ## block ## id ## _ ## reg_name
144 #define SRI2(reg_name, block, id)\
145 	.reg_name = BASE(reg ## reg_name ## _BASE_IDX) +	\
146 		reg ## reg_name
147 #define SRI2_ARR(reg_name, block, id)\
148 	REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) +	\
149 		reg ## reg_name
151 #define SRIR(var_name, reg_name, block, id)\
152 	.var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
153 		reg ## block ## id ## _ ## reg_name
155 #define SRII(reg_name, block, id)\
156 	REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
157 					reg ## block ## id ## _ ## reg_name
159 #define SRII_ARR_2(reg_name, block, id, inst)\
160 	REG_STRUCT[inst].reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
161 		reg ## block ## id ## _ ## reg_name
163 #define SRII_MPC_RMU(reg_name, block, id)\
164 	.RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
165 		reg ## block ## id ## _ ## reg_name
167 #define SRII_DWB(reg_name, temp_name, block, id)\
168 	REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
171 #define SF_DWB2(reg_name, block, id, field_name, post_fix)	\
172 	.field_name = reg_name ## __ ## field_name ## post_fix
174 #define DCCG_SRII(reg_name, block, id)\
175 	REG_STRUCT.block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
176 		reg ## block ## id ## _ ## reg_name
178 #define VUPDATE_SRII(reg_name, block, id)\
179 	REG_STRUCT.reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
180 		reg ## reg_name ## _ ## block ## id
188 #define NBIO_SR(reg_name)\
189 	REG_STRUCT.reg_name = NBIO_BASE(regBIF_BX0_ ## reg_name ## _BASE_IDX) + \
190 			regBIF_BX0_ ## reg_name
191 #define NBIO_SR_ARR(reg_name, id)\
192 	REG_STRUCT[id].reg_name = NBIO_BASE(regBIF_BX0_ ## reg_name ## _BASE_IDX) + \
193 		regBIF_BX0_ ## reg_name
197 #define REG(reg_name) \
198 	(ctx->dcn_reg_offsets[reg ## reg_name ## _BASE_IDX] + reg ## reg_name)