Searched refs:cache_line_size (Results 1 - 25 of 65) sorted by last modified time

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/linux-master/drivers/net/ethernet/broadcom/bnxt/
H A Dbnxt.c13623 bnxt_hwrm_set_cache_line_size(bp, cache_line_size());
/linux-master/arch/x86/kvm/
H A Dx86.c8036 page_line_mask = ~(cache_line_size() - 1);
/linux-master/drivers/net/ethernet/mellanox/mlx5/core/
H A Dmain.c612 cache_line_size() >= 128 ? 1 : 0);
/linux-master/kernel/trace/
H A Dring_buffer.c1517 bpage = kzalloc_node(ALIGN(sizeof(*bpage), cache_line_size()),
1587 cpu_buffer = kzalloc_node(ALIGN(sizeof(*cpu_buffer), cache_line_size()),
1603 bpage = kzalloc_node(ALIGN(sizeof(*bpage), cache_line_size()),
1688 buffer = kzalloc(ALIGN(sizeof(*buffer), cache_line_size()),
1718 buffer->buffers = kzalloc(ALIGN(bsize, cache_line_size()),
/linux-master/drivers/scsi/cxlflash/
H A Dmain.c3409 buf = kmalloc(ulen + cache_line_size() - 1, GFP_KERNEL);
3415 kbuf = PTR_ALIGN(buf, cache_line_size());
/linux-master/block/
H A Dblk-mq.c3400 cache_line_size());
/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn321/
H A Ddcn321_resource.c1702 dc->caps.cache_line_size = 64;
2034 dc->dml2_options.mall_cfg.cache_line_size_bytes = dc->caps.cache_line_size;
/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn32/
H A Ddcn32_resource.c2054 dc->caps.cache_line_size = 64;
2398 dc->dml2_options.mall_cfg.cache_line_size_bytes = dc->caps.cache_line_size;
/linux-master/drivers/gpu/drm/amd/display/dc/dcn32/
H A Ddcn32_resource_helpers.c46 cache_lines_used = total_size_in_mall_bytes / dc->caps.cache_line_size + 2;
48 total_cache_lines = dc->caps.max_cab_allocation_bytes / dc->caps.cache_line_size;
/linux-master/drivers/vfio/pci/mlx5/
H A Dcmd.c1095 int cqe_size = cache_line_size() == 128 ? 128 : 64;
/linux-master/arch/mips/mm/
H A Dpage.c87 static int cache_line_size; variable
88 #define cache_line_mask() (cache_line_size - 1)
136 cache_line_size = cpu_dcache_line_size();
205 cache_line_size = cpu_scache_line_size();
207 cache_line_size = cpu_dcache_line_size();
214 max(cache_line_size >> 1,
217 max(cache_line_size >> 1,
238 } else if (cache_line_size == (half_clear_loop_size << 1)) {
299 off = cache_line_size ? min(8, pref_bias_clear_store / cache_line_size)
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/linux-master/mm/
H A Dvmscan.c3324 int n = clamp_t(int, cache_line_size() / sizeof(pte_t), 2, 8);
H A Dslab_common.c125 ralign = cache_line_size();
H A Dslub.c5659 cache_line_size(),
/linux-master/include/linux/
H A Dpci-epf.h39 * @cache_line_size: specifies the system cacheline size in units of DWORDs
51 u8 cache_line_size; member in struct:pci_epf_header
/linux-master/drivers/pci/controller/dwc/
H A Dpcie-designware-ep.c122 hdr->cache_line_size);
/linux-master/drivers/pci/controller/cadence/
H A Dpcie-cadence-ep.c58 hdr->cache_line_size);
/linux-master/drivers/iommu/
H A Diova.c727 cache_line_size());
/linux-master/drivers/gpu/drm/amd/display/dc/
H A Ddc.h272 uint32_t cache_line_size; member in struct:dc_caps
/linux-master/drivers/gpu/drm/amd/amdkfd/
H A Dkfd_topology.c356 sysfs_show_32bit_prop(buffer, offs, "cache_line_size",
1567 pcache->cacheline_size = pcache_info[cache_type].cache_line_size;
1636 pcache->cacheline_size = pcache_info[cache_type].cache_line_size;
H A Dkfd_crat.c58 .cache_line_size = 64,
68 .cache_line_size = 64,
78 .cache_line_size = 64,
94 .cache_line_size = 64,
104 .cache_line_size = 64,
114 .cache_line_size = 64,
144 .cache_line_size = 64,
154 .cache_line_size = 64,
164 .cache_line_size = 64,
174 .cache_line_size
[all...]
H A Dkfd_crat.h170 uint16_t cache_line_size; member in struct:crat_subtype_cache
306 uint32_t cache_line_size; member in struct:kfd_gpu_cache_info
/linux-master/drivers/accel/habanalabs/gaudi2/
H A Dgaudi2.c2446 prop->cache_line_size = DEVICE_CACHE_LINE_SIZE;
/linux-master/drivers/accel/habanalabs/gaudi/
H A Dgaudi.c575 prop->cache_line_size = DEVICE_CACHE_LINE_SIZE;
/linux-master/drivers/accel/habanalabs/common/
H A Dhabanalabs.h666 * @cache_line_size: device cache line size.
797 u16 cache_line_size; member in struct:asic_fixed_properties

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