Searched refs:write_csr (Results 1 - 18 of 18) sorted by relevance

/linux-master/drivers/infiniband/hw/hfi1/
H A Deprom.c51 write_csr(dd, ASIC_EEP_ADDR_CMD, CMD_READ_DATA(offset));
54 write_csr(dd, ASIC_EEP_ADDR_CMD, CMD_NOP); /* close open page */
152 write_csr(dd, ASIC_EEP_CTL_STAT, ASIC_EEP_CTL_STAT_EP_RESET_SMASK);
154 write_csr(dd, ASIC_EEP_CTL_STAT,
158 write_csr(dd, ASIC_EEP_ADDR_CMD, CMD_RELEASE_POWERDOWN_NOID);
H A Dfirmware.c237 write_csr(dd, DC_DC8051_CFG_RAM_ACCESS_CTRL, reg);
239 write_csr(dd, DC_DC8051_CFG_RAM_ACCESS_CTRL,
274 write_csr(dd, DC_DC8051_CFG_RAM_ACCESS_SETUP, 0);
283 write_csr(dd, DC_DC8051_CFG_RAM_ACCESS_CTRL, 0);
306 write_csr(dd, DC_DC8051_CFG_RAM_ACCESS_SETUP, reg);
311 write_csr(dd, DC_DC8051_CFG_RAM_ACCESS_CTRL, reg);
325 write_csr(dd, DC_DC8051_CFG_RAM_ACCESS_WR_DATA, reg);
342 write_csr(dd, DC_DC8051_CFG_RAM_ACCESS_CTRL, 0);
343 write_csr(dd, DC_DC8051_CFG_RAM_ACCESS_SETUP, 0);
745 write_csr(d
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H A Dchip.c1316 * write_csr - write CSR at the indicated offset
1321 void write_csr(const struct hfi1_devdata *dd, u32 offset, u64 value) function
1358 write_csr(dd, csr, value);
5684 write_csr(dd, SEND_EGRESS_ERR_INFO, info);
6100 write_csr(dd, dd->hfi1_id ? ASIC_QSFP2_INVERT :
6136 write_csr(dd, dd->hfi1_id ? ASIC_QSFP2_INVERT :
6191 write_csr(dd, DC_DC8051_CFG_CSR_ACCESS_SEL,
6202 write_csr(dd, DC_DC8051_CFG_CSR_ACCESS_SEL,
6326 write_csr(dd, DC_DC8051_CFG_EXT_DEV_0,
6348 write_csr(d
[all...]
H A Dpcie.c831 write_csr(dd, ASIC_PCIE_SD_INTRPT_LIST + (index * 8),
850 write_csr(dd, ASIC_PCIE_SD_HOST_CMD, reg);
925 write_csr(dd, CCE_PCIE_CTRL, pcie_ctrl);
1022 write_csr(dd, ASIC_CFG_THERM_POLL_EN, 0x0);
1234 write_csr(dd, CCE_DC_CTRL, CCE_DC_CTRL_DC_RESET_SMASK);
1289 write_csr(dd, MISC_CFG_FW_CTRL, fw_ctrl);
1311 write_csr(dd, CCE_DC_CTRL, 0);
1367 write_csr(dd, ASIC_CFG_THERM_POLL_EN, 0x1);
H A Dchip.h576 void write_csr(const struct hfi1_devdata *dd, u32 offset, u64 value);
594 write_csr(dd, offset0 + (0x100 * ctxt), value);
629 write_csr(dd, offset0 + (0x1000 * ctxt), value);
H A Dpio.c23 write_csr(dd, SEND_CTRL, sendctrl | SEND_CTRL_CM_RESET_SMASK);
81 write_csr(dd, SEND_CTRL, reg);
1226 write_csr(dd, SEND_PIO_ERR_CLEAR,
1231 write_csr(dd, SEND_PIO_INIT_CTXT,
1304 write_csr(dd, SEND_PIO_INIT_CTXT, pio);
H A Ddebugfs.c579 write_csr(dd, ASIC_CFG_SCRATCH, scratch0);
1040 write_csr(dd, ASIC_GPIO_OUT, gpio_val);
1041 write_csr(dd, ASIC_GPIO_OE, gpio_val);
H A Dqsfp.c43 write_csr(dd, target_oe, reg);
67 write_csr(dd, target_oe, reg);
H A Dhfi.h2383 write_csr(dd, DCC_CFG_LED_CNTRL, 0x1F);
2385 write_csr(dd, DCC_CFG_LED_CNTRL, 0x10);
H A Dmad.c1762 write_csr(dd, SEND_SC2VLT0, *val++);
1763 write_csr(dd, SEND_SC2VLT1, *val++);
1764 write_csr(dd, SEND_SC2VLT2, *val++);
1765 write_csr(dd, SEND_SC2VLT3, *val++);
3491 * write_csr(dd, DCC_PRF_PORT_MARK_FECN_CNT, 0);
3566 * write_csr(dd, DCC_PRF_PORT_VL_MARK_FECN_CNT + offset, 0);
3631 write_csr(dd, RCV_ERR_INFO,
H A Dinit.c532 write_csr(dd, SEND_STATIC_RATE_CONTROL, src);
H A Ddriver.c1313 write_csr(dd, DCC_CFG_LED_CNTRL, 0);
H A Dsdma.c3378 write_csr(sde->dd,
/linux-master/drivers/net/ethernet/amd/
H A Dpcnet32.c243 void (*write_csr) (unsigned long, int, u16); member in struct:pcnet32_access
383 .write_csr = pcnet32_wio_write_csr,
438 .write_csr = pcnet32_dwio_write_csr,
464 lp->a->write_csr(ioaddr, CSR3, val);
690 a->write_csr(ioaddr, CSR5, csr5 | CSR5_SUSPEND);
715 lp->a->write_csr(ioaddr, CSR5, csr5 & ~CSR5_SUSPEND);
763 lp->a->write_csr(ioaddr, CSR0, CSR0_STOP);
776 lp->a->write_csr(ioaddr, CSR15, csr15);
893 lp->a->write_csr(ioaddr, CSR0, CSR0_STOP); /* stop the chip */
989 lp->a->write_csr(ioadd
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/linux-master/drivers/firewire/
H A Dcore.h92 void (*write_csr)(struct fw_card *card, int csr_offset, u32 value); member in struct:fw_card_driver
H A Dcore-card.c610 * .read/write_csr() should never be called anymore after the dummy driver
697 .write_csr = dummy_write_csr,
H A Dcore-transaction.c1214 card->driver->write_csr(card, reg, be32_to_cpu(*data));
1221 card->driver->write_csr(card, CSR_STATE_CLEAR,
H A Dohci.c3568 .write_csr = ohci_write_csr,

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