| /u-boot/drivers/ddr/fsl/ |
| H A D | mpc85xx_ddr_gen1.c | 48 out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2);
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| H A D | mpc85xx_ddr_gen2.c | 70 out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2);
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| H A D | mpc85xx_ddr_gen3.c | 128 out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2);
214 out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2 & 0xf07fffff);
339 out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2);
512 /* C: Set timing_cfg_2[cpo] to 0b11111 */
513 setbits_be32(&ddr->timing_cfg_2, TIMING_CFG_2_CPO_MASK);
515 in_be32(&ddr->timing_cfg_2));
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| H A D | arm_ddr_gen3.c | 96 ddr_out32(&ddr->timing_cfg_2, regs->timing_cfg_2);
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| H A D | ctrl_regs.c | 714 ddr->timing_cfg_2 = (0
724 debug("FSLDDR: timing_cfg_2 = 0x%08x\n", ddr->timing_cfg_2);
1934 unsigned int wr_lat = ((ddr->timing_cfg_2 & 0x00780000) >> 19) +
1935 ((ddr->timing_cfg_2 & 0x00040000) >> 14);
1936 /* rodt_on = timing_cfg_1[caslat] - timing_cfg_2[wrlat] + 1 */
2032 int wr_lat = ((ddr->timing_cfg_2 & 0x00780000) >> 19) +
2033 ((ddr->timing_cfg_2 & 0x00040000) >> 14);
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| H A D | fsl_ddr_gen4.c | 172 ddr_out32(&ddr->timing_cfg_2, regs->timing_cfg_2);
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| H A D | interactive.c | 635 CFG_REGS(timing_cfg_2),
726 CFG_REGS(timing_cfg_2),
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| /u-boot/board/socrates/ |
| H A D | sdram.c | 41 ddr->timing_cfg_2 = CFG_SYS_DDR_TIMING_2;
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| /u-boot/board/freescale/ls1043ardb/ |
| H A D | ddr.h | 62 .timing_cfg_2 = 0x0048C111,
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| /u-boot/board/gdsys/mpc8308/ |
| H A D | sdram.c | 54 out_be32(&im->ddr.timing_cfg_2, CFG_SYS_DDR_TIMING_2);
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| /u-boot/board/kontron/sl28/ |
| H A D | ddr.c | 30 .timing_cfg_2 = 0x0fc0d118,
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| /u-boot/board/freescale/ls1021atsn/ |
| H A D | ls1021atsn.c | 41 out_be32(&ddr->timing_cfg_2, DDR_TIMING_CFG_2);
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| /u-boot/board/freescale/ls1021aiot/ |
| H A D | ls1021aiot.c | 65 out_be32(&ddr->timing_cfg_2, DDR_TIMING_CFG_2);
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| /u-boot/drivers/ram/ |
| H A D | mpc83xx_sdram.c | 337 u32 timing_cfg_2; local
776 timing_cfg_2 = additive_latency << TIMING_CFG2_ADD_LAT_SHIFT |
784 out_be32(&im->ddr.timing_cfg_2, timing_cfg_2);
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| /u-boot/board/freescale/mpc837xerdb/ |
| H A D | mpc837xerdb.c | 118 im->ddr.timing_cfg_2 = CFG_SYS_DDR_TIMING_2;
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| /u-boot/board/freescale/p1_p2_rdb_pc/ |
| H A D | ddr.c | 223 .timing_cfg_2 = CFG_SYS_DDR_TIMING_2,
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| /u-boot/board/keymile/km83xx/ |
| H A D | km83xx.c | 220 out_be32(&im->ddr.timing_cfg_2, CFG_SYS_DDR_TIMING_2);
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| /u-boot/include/ |
| H A D | fsl_immap.h | 36 u32 timing_cfg_2; /* SDRAM Timing Configuration 2 */ member in struct:ccsr_ddr
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| H A D | fsl_ddr_sdram.h | 251 unsigned int timing_cfg_2; member in struct:fsl_ddr_cfg_regs_s
379 unsigned int cpo_override; /* override timing_cfg_2[CPO]*/
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| /u-boot/arch/powerpc/cpu/mpc83xx/ |
| H A D | spd_sdram.c | 630 ddr->timing_cfg_2 = (0
641 debug("DDR:timing_cfg_2=0x%08x\n", ddr->timing_cfg_2);
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| /u-boot/board/cssi/cmpcpro/ |
| H A D | cmpcpro.c | 310 out_be32(&im->ddr.timing_cfg_2, CFG_SYS_DDR_TIMING_2);
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| /u-boot/board/freescale/ls1021atwr/ |
| H A D | ls1021atwr.c | 156 out_be32(&ddr->timing_cfg_2, DDR_TIMING_CFG_2);
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| /u-boot/arch/powerpc/include/asm/ |
| H A D | immap_83xx.h | 290 u32 timing_cfg_2; /* SDRAM Timing Configuration 2 */ member in struct:ddr83xx
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