1// SPDX-License-Identifier: GPL-2.0+ 2 3#include <common.h> 4#include <asm/global_data.h> 5#include <asm/io.h> 6#include <fsl_ddr_sdram.h> 7 8DECLARE_GLOBAL_DATA_PTR; 9 10#define DCFG_GPPORCR1 0x20 11 12#define GPPORCR1_MEM_MASK (0x7 << 5) 13#define GPPORCR1_MEM_512MB_CS0 (0x0 << 5) 14#define GPPORCR1_MEM_1GB_CS0 (0x1 << 5) 15#define GPPORCR1_MEM_2GB_CS0 (0x2 << 5) 16#define GPPORCR1_MEM_4GB_CS0_1 (0x3 << 5) 17#define GPPORCR1_MEM_4GB_CS0_2 (0x4 << 5) 18#define GPPORCR1_MEM_8GB_CS0_1_2_3 (0x5 << 5) 19#define GPPORCR1_MEM_8GB_CS0_1 (0x6 << 5) 20 21static fsl_ddr_cfg_regs_t __maybe_unused ddr_cfg_regs = { 22 .cs[0].bnds = 0x0000007f, 23 .cs[0].config = 0x80044402, 24 .cs[1].bnds = 0x008000ff, 25 .cs[1].config = 0x80004402, 26 27 .timing_cfg_0 = 0x9011010c, 28 .timing_cfg_3 = 0x010c1000, 29 .timing_cfg_1 = 0xbcb48c66, 30 .timing_cfg_2 = 0x0fc0d118, 31 .ddr_sdram_cfg = 0xe70c000c, 32 .ddr_sdram_cfg_2 = 0x24401111, 33 .ddr_sdram_mode = 0x00441c70, 34 .ddr_sdram_mode_3 = 0x00001c70, 35 .ddr_sdram_mode_5 = 0x00001c70, 36 .ddr_sdram_mode_7 = 0x00001c70, 37 .ddr_sdram_mode_2 = 0x00180000, 38 .ddr_sdram_mode_4 = 0x00180000, 39 .ddr_sdram_mode_6 = 0x00180000, 40 .ddr_sdram_mode_8 = 0x00180000, 41 42 .ddr_sdram_interval = 0x0c30030c, 43 .ddr_data_init = 0xdeadbeef, 44 45 .ddr_sdram_clk_cntl = 0x02400000, 46 47 .timing_cfg_4 = 0x00000001, 48 .timing_cfg_5 = 0x04401400, 49 50 .ddr_zq_cntl = 0x89080600, 51 .ddr_wrlvl_cntl = 0x8675f606, 52 .ddr_wrlvl_cntl_2 = 0x04080700, 53 .ddr_wrlvl_cntl_3 = 0x00000009, 54 55 .ddr_cdr1 = 0x80040000, 56 .ddr_cdr2 = 0x0000bc01, 57 58 /* Erratum A-009942, set optimal CPO value */ 59 .debug[28] = 0x00700040, 60}; 61 62int fsl_initdram(void) 63{ 64 u32 gpporcr1 = in_le32(DCFG_BASE + DCFG_GPPORCR1); 65 phys_size_t dram_size; 66 67 switch (gpporcr1 & GPPORCR1_MEM_MASK) { 68 case GPPORCR1_MEM_2GB_CS0: 69 dram_size = 0x80000000; 70 ddr_cfg_regs.cs[1].bnds = 0; 71 ddr_cfg_regs.cs[1].config = 0; 72 break; 73 case GPPORCR1_MEM_4GB_CS0_1: 74 dram_size = 0x100000000ULL; 75 break; 76 case GPPORCR1_MEM_8GB_CS0_1: 77 dram_size = 0x200000000ULL; 78 ddr_cfg_regs.cs[0].bnds = 0x000000ff; 79 ddr_cfg_regs.cs[0].config = 0x80044403; 80 ddr_cfg_regs.cs[1].bnds = 0x010001ff; 81 ddr_cfg_regs.cs[1].config = 0x80044403; 82 break; 83 case GPPORCR1_MEM_512MB_CS0: 84 dram_size = 0x20000000; 85 fallthrough; /* for now */ 86 case GPPORCR1_MEM_1GB_CS0: 87 dram_size = 0x40000000; 88 fallthrough; /* for now */ 89 case GPPORCR1_MEM_4GB_CS0_2: 90 dram_size = 0x100000000ULL; 91 fallthrough; /* for now */ 92 case GPPORCR1_MEM_8GB_CS0_1_2_3: 93 dram_size = 0x200000000ULL; 94 fallthrough; /* for now */ 95 default: 96 panic("Unsupported memory configuration (%08x)\n", 97 gpporcr1 & GPPORCR1_MEM_MASK); 98 break; 99 } 100 101 if (!IS_ENABLED(CONFIG_SPL) || IS_ENABLED(CONFIG_SPL_BUILD)) 102 fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0); 103 104 gd->ram_size = dram_size; 105 106 return 0; 107} 108