1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright 2008 Freescale Semiconductor, Inc.
4 */
5
6#include <common.h>
7#include <log.h>
8#include <asm/io.h>
9#include <fsl_ddr_sdram.h>
10#include <linux/delay.h>
11
12#if (CONFIG_CHIP_SELECTS_PER_CTRL > 4)
13#error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL
14#endif
15
16void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
17			     unsigned int ctrl_num, int step)
18{
19	unsigned int i;
20	struct ccsr_ddr __iomem *ddr =
21		(struct ccsr_ddr __iomem *)CFG_SYS_FSL_DDR_ADDR;
22
23	if (ctrl_num != 0) {
24		printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
25		return;
26	}
27
28	for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
29		if (i == 0) {
30			out_be32(&ddr->cs0_bnds, regs->cs[i].bnds);
31			out_be32(&ddr->cs0_config, regs->cs[i].config);
32
33		} else if (i == 1) {
34			out_be32(&ddr->cs1_bnds, regs->cs[i].bnds);
35			out_be32(&ddr->cs1_config, regs->cs[i].config);
36
37		} else if (i == 2) {
38			out_be32(&ddr->cs2_bnds, regs->cs[i].bnds);
39			out_be32(&ddr->cs2_config, regs->cs[i].config);
40
41		} else if (i == 3) {
42			out_be32(&ddr->cs3_bnds, regs->cs[i].bnds);
43			out_be32(&ddr->cs3_config, regs->cs[i].config);
44		}
45	}
46
47	out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1);
48	out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2);
49	out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode);
50	out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval);
51
52	/*
53	 * 200 painful micro-seconds must elapse between
54	 * the DDR clock setup and the DDR config enable.
55	 */
56	udelay(200);
57	asm volatile("sync;isync");
58
59	out_be32(&ddr->sdram_cfg, regs->ddr_sdram_cfg);
60
61	asm("sync;isync;msync");
62	udelay(500);
63}
64
65#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
66/*
67 * Initialize all of memory for ECC, then enable errors.
68 */
69
70void
71ddr_enable_ecc(unsigned int dram_size)
72{
73	struct ccsr_ddr __iomem *ddr =
74		(struct ccsr_ddr __iomem *)(CFG_SYS_FSL_DDR_ADDR);
75
76	dma_meminit(dram_size);
77
78	/*
79	 * Enable errors for ECC.
80	 */
81	debug("DMA DDR: err_disable = 0x%08x\n", ddr->err_disable);
82	ddr->err_disable = 0x00000000;
83	asm("sync;isync;msync");
84	debug("DMA DDR: err_disable = 0x%08x\n", ddr->err_disable);
85}
86
87#endif	/* CONFIG_DDR_ECC  && ! CONFIG_ECC_INIT_VIA_DDRCONTROLLER */
88